15ae11aa4SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 25ae11aa4SDmitry Baryshkov /* 35ae11aa4SDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 45ae11aa4SDmitry Baryshkov */ 55ae11aa4SDmitry Baryshkov 65ae11aa4SDmitry Baryshkov #ifndef QCOM_PHY_QMP_PCS_V2_H_ 75ae11aa4SDmitry Baryshkov #define QCOM_PHY_QMP_PCS_V2_H_ 85ae11aa4SDmitry Baryshkov 95ae11aa4SDmitry Baryshkov /* Only for QMP V2 PHY - PCS registers */ 10027d16b5SDmitry Baryshkov #define QPHY_V2_PCS_SW_RESET 0x000 115ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 12027d16b5SDmitry Baryshkov #define QPHY_V2_PCS_START_CONTROL 0x008 135ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 145ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 155ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 165ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 175ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 185ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064 195ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c 205ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080 215ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084 225ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088 235ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 245ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 25c1ab64aaSDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 26d36e341aSDmitry Baryshkov #define QPHY_V2_PCS_FLL_CNTRL1 0x0c0 27d36e341aSDmitry Baryshkov #define QPHY_V2_PCS_FLL_CNTRL2 0x0c4 28d36e341aSDmitry Baryshkov #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 29d36e341aSDmitry Baryshkov #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc 30d36e341aSDmitry Baryshkov #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 31*e3c3f7cfSDmitry Baryshkov #define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178 325ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 335ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac 345ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 355ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 365ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 375ae11aa4SDmitry Baryshkov 38027d16b5SDmitry Baryshkov #define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */ 39027d16b5SDmitry Baryshkov 405ae11aa4SDmitry Baryshkov #endif 41