1*5ae11aa4SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 2*5ae11aa4SDmitry Baryshkov /* 3*5ae11aa4SDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4*5ae11aa4SDmitry Baryshkov */ 5*5ae11aa4SDmitry Baryshkov 6*5ae11aa4SDmitry Baryshkov #ifndef QCOM_PHY_QMP_PCS_V2_H_ 7*5ae11aa4SDmitry Baryshkov #define QCOM_PHY_QMP_PCS_V2_H_ 8*5ae11aa4SDmitry Baryshkov 9*5ae11aa4SDmitry Baryshkov /* Only for QMP V2 PHY - PCS registers */ 10*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 11*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 12*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 13*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034 14*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038 15*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c 16*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040 17*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 18*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 19*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 20*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064 21*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c 22*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080 23*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084 24*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088 25*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 26*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 27*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc 28*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c 29*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 30*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 31*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 32*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 33*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac 34*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 35*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 36*5ae11aa4SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 37*5ae11aa4SDmitry Baryshkov 38*5ae11aa4SDmitry Baryshkov #endif 39