1 /* Only for QMP V5 PHY - UFS PCS registers */ 2 /* SPDX-License-Identifier: GPL-2.0 */ 3 /* 4 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_ 8 #define QCOM_PHY_QMP_PCS_UFS_V5_H_ 9 10 /* Only for QMP V5 PHY - UFS PCS registers */ 11 #define QPHY_V5_PCS_UFS_PHY_START 0x000 12 #define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004 13 #define QPHY_V5_PCS_UFS_SW_RESET 0x008 14 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 15 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 16 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 17 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 18 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 19 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 20 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 21 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 22 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 23 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 24 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 25 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 26 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 27 #define QPHY_V5_PCS_UFS_READY_STATUS 0x180 28 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 29 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 30 31 #endif 32