1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
7 #define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
8 
9 /* Only for QMP V5_20 PHY - PCIe PCS registers */
10 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x01c
11 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5	0x084
12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS		0x090
13 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1			0x0a0
14 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST		0x0e0
15 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2		0x0fc
16 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
17 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN			0x15c
18 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3	0x184
19 #define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2		0xa24
20 #define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2		0xa28
21 
22 #endif
23