1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 26 #include "phy-qcom-qmp.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 #define REFCLK_DRV_DSBL BIT(1) 33 /* QPHY_START_CONTROL bits */ 34 #define SERDES_START BIT(0) 35 #define PCS_START BIT(1) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 40 #define PHY_INIT_COMPLETE_TIMEOUT 10000 41 42 struct qmp_phy_init_tbl { 43 unsigned int offset; 44 unsigned int val; 45 /* 46 * mask of lanes for which this register is written 47 * for cases when second lane needs different values 48 */ 49 u8 lane_mask; 50 }; 51 52 #define QMP_PHY_INIT_CFG(o, v) \ 53 { \ 54 .offset = o, \ 55 .val = v, \ 56 .lane_mask = 0xff, \ 57 } 58 59 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 60 { \ 61 .offset = o, \ 62 .val = v, \ 63 .lane_mask = l, \ 64 } 65 66 /* set of registers with offsets different per-PHY */ 67 enum qphy_reg_layout { 68 /* PCS registers */ 69 QPHY_SW_RESET, 70 QPHY_START_CTRL, 71 QPHY_PCS_STATUS, 72 QPHY_PCS_POWER_DOWN_CONTROL, 73 /* Keep last to ensure regs_layout arrays are properly initialized */ 74 QPHY_LAYOUT_SIZE 75 }; 76 77 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 78 [QPHY_SW_RESET] = 0x00, 79 [QPHY_START_CTRL] = 0x44, 80 [QPHY_PCS_STATUS] = 0x14, 81 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 82 }; 83 84 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 85 [QPHY_SW_RESET] = 0x00, 86 [QPHY_START_CTRL] = 0x08, 87 [QPHY_PCS_STATUS] = 0x174, 88 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 89 }; 90 91 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 92 [QPHY_SW_RESET] = 0x00, 93 [QPHY_START_CTRL] = 0x08, 94 [QPHY_PCS_STATUS] = 0x174, 95 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 96 }; 97 98 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 99 [QPHY_SW_RESET] = 0x00, 100 [QPHY_START_CTRL] = 0x08, 101 [QPHY_PCS_STATUS] = 0x2ac, 102 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 103 }; 104 105 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 106 [QPHY_SW_RESET] = 0x00, 107 [QPHY_START_CTRL] = 0x44, 108 [QPHY_PCS_STATUS] = 0x14, 109 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 110 }; 111 112 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 155 }; 156 157 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 158 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 159 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 160 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 161 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 162 }; 163 164 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 165 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 166 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 179 }; 180 181 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 192 }; 193 194 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 195 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 196 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 197 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 241 }; 242 243 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 244 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 245 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 246 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 247 }; 248 249 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 280 }; 281 282 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 288 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 289 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 290 }; 291 292 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 299 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 300 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 302 }; 303 304 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 305 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 306 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 307 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 308 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 310 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 311 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 312 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 313 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 314 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 315 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 316 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 317 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 318 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 319 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 320 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 321 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 322 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 323 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 324 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 325 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 326 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 327 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 328 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 329 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 330 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 331 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 332 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 333 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 334 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 335 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 336 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 337 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 338 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 339 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 340 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 341 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 342 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 343 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 344 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 345 }; 346 347 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 348 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 349 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 350 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 351 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 352 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 353 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 354 }; 355 356 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 357 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 358 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 359 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 360 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 361 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 362 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 363 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 364 }; 365 366 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 367 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 368 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 369 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 370 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 371 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 372 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 373 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 374 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 378 }; 379 380 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 381 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 382 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 383 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 438 }; 439 440 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 441 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 442 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 443 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 444 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 445 }; 446 447 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 478 }; 479 480 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 492 }; 493 494 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 508 }; 509 510 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 553 }; 554 555 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 556 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 557 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 558 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 559 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 560 }; 561 562 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 579 }; 580 581 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 583 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 589 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 597 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 601 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 603 }; 604 605 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 611 }; 612 613 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 614 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 615 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 616 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 617 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 618 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 619 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 620 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 659 }; 660 661 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 718 }; 719 720 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 721 }; 722 723 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 730 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 731 }; 732 733 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 776 }; 777 778 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 779 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 780 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 781 }; 782 783 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 820 }; 821 822 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 827 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 828 }; 829 830 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 838 }; 839 840 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 841 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 842 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 843 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 844 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 845 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 881 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 882 }; 883 884 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 885 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 886 }; 887 888 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 889 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 890 }; 891 892 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 893 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 894 }; 895 896 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 897 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 898 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 899 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 900 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 901 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 902 }; 903 904 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 905 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 906 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 907 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 908 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 909 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 916 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 917 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 918 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 922 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 923 }; 924 925 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 926 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 927 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 928 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 929 }; 930 931 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 932 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 933 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 934 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 935 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 936 }; 937 938 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 939 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 940 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 941 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 942 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 943 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 944 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 945 }; 946 947 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 948 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 949 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 950 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 951 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 952 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 953 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 954 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 955 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 956 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 957 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 958 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 959 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 960 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 961 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 962 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 963 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 964 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 965 }; 966 967 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 968 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 969 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 970 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 971 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 972 }; 973 974 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 975 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 976 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 977 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 978 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 979 }; 980 981 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1023 }; 1024 1025 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1027 }; 1028 1029 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1030 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1033 }; 1034 1035 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1036 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1066 }; 1067 1068 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1074 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1075 }; 1076 1077 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1078 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1079 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1080 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1081 }; 1082 1083 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1085 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1086 }; 1087 1088 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1089 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1090 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1091 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1092 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1093 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1094 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1095 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1096 }; 1097 1098 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1099 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1100 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1101 }; 1102 1103 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1104 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1105 }; 1106 1107 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1108 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1109 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1110 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1111 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1112 }; 1113 1114 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1115 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1116 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1117 }; 1118 1119 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1120 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1121 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1122 }; 1123 1124 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1125 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1126 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1127 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1128 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1143 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1144 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1145 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1164 }; 1165 1166 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1167 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1168 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1169 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1170 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1171 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1172 }; 1173 1174 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1175 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1176 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1177 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1178 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1179 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1180 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1181 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1182 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1183 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1184 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1185 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1186 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1187 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1188 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1189 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1190 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1191 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1192 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1193 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1194 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1195 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1196 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1197 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1198 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1199 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1200 }; 1201 1202 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1203 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1204 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1205 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1206 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1207 }; 1208 1209 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1210 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1211 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1212 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1213 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1214 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1215 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1216 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1217 }; 1218 1219 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1262 }; 1263 1264 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1265 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1270 }; 1271 1272 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1273 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1295 }; 1296 1297 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1298 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1299 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1300 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1301 }; 1302 1303 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1304 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1305 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1306 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1307 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1308 }; 1309 1310 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1324 }; 1325 1326 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1348 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1349 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1355 }; 1356 1357 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1358 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1359 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1360 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1362 }; 1363 1364 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1365 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1366 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1377 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1378 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1379 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1380 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1381 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1382 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1383 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1384 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1385 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1386 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1387 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1388 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1389 1390 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1391 1392 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1393 1394 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1395 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1396 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1397 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1398 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1399 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1400 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1401 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1402 1403 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1404 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1405 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1406 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1407 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1408 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1409 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1410 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1411 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1412 }; 1413 1414 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1415 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1416 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1417 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1418 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 1419 }; 1420 1421 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1422 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1423 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1424 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1425 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1426 }; 1427 1428 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1429 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1430 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1431 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 1432 }; 1433 1434 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1435 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1436 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1444 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1445 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1446 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1447 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1448 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1449 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1450 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1451 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1452 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1453 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1454 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1455 }; 1456 1457 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1458 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1459 }; 1460 1461 struct qmp_pcie_offsets { 1462 u16 serdes; 1463 u16 pcs; 1464 u16 pcs_misc; 1465 u16 tx; 1466 u16 rx; 1467 u16 tx2; 1468 u16 rx2; 1469 }; 1470 1471 struct qmp_phy_cfg_tbls { 1472 const struct qmp_phy_init_tbl *serdes; 1473 int serdes_num; 1474 const struct qmp_phy_init_tbl *tx; 1475 int tx_num; 1476 const struct qmp_phy_init_tbl *rx; 1477 int rx_num; 1478 const struct qmp_phy_init_tbl *pcs; 1479 int pcs_num; 1480 const struct qmp_phy_init_tbl *pcs_misc; 1481 int pcs_misc_num; 1482 }; 1483 1484 /* struct qmp_phy_cfg - per-PHY initialization config */ 1485 struct qmp_phy_cfg { 1486 int lanes; 1487 1488 const struct qmp_pcie_offsets *offsets; 1489 1490 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1491 const struct qmp_phy_cfg_tbls tbls; 1492 /* 1493 * Additional init sequences for PHY blocks, providing additional 1494 * register programming. They are used for providing separate sequences 1495 * for the Root Complex and End Point use cases. 1496 * 1497 * If EP mode is not supported, both tables can be left unset. 1498 */ 1499 const struct qmp_phy_cfg_tbls *tbls_rc; 1500 const struct qmp_phy_cfg_tbls *tbls_ep; 1501 1502 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 1503 int serdes_4ln_num; 1504 1505 /* clock ids to be requested */ 1506 const char * const *clk_list; 1507 int num_clks; 1508 /* resets to be requested */ 1509 const char * const *reset_list; 1510 int num_resets; 1511 /* regulators to be requested */ 1512 const char * const *vreg_list; 1513 int num_vregs; 1514 1515 /* array of registers with different offsets */ 1516 const unsigned int *regs; 1517 1518 unsigned int pwrdn_ctrl; 1519 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1520 unsigned int phy_status; 1521 1522 bool skip_start_delay; 1523 1524 /* QMP PHY pipe clock interface rate */ 1525 unsigned long pipe_clock_rate; 1526 }; 1527 1528 struct qmp_pcie { 1529 struct device *dev; 1530 1531 const struct qmp_phy_cfg *cfg; 1532 bool tcsr_4ln_config; 1533 1534 void __iomem *serdes; 1535 void __iomem *pcs; 1536 void __iomem *pcs_misc; 1537 void __iomem *tx; 1538 void __iomem *rx; 1539 void __iomem *tx2; 1540 void __iomem *rx2; 1541 1542 void __iomem *port_b; 1543 1544 struct clk_bulk_data *clks; 1545 struct clk_bulk_data pipe_clks[2]; 1546 int num_pipe_clks; 1547 1548 struct reset_control_bulk_data *resets; 1549 struct regulator_bulk_data *vregs; 1550 1551 struct phy *phy; 1552 int mode; 1553 1554 struct clk_fixed_rate pipe_clk_fixed; 1555 }; 1556 1557 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1558 { 1559 u32 reg; 1560 1561 reg = readl(base + offset); 1562 reg |= val; 1563 writel(reg, base + offset); 1564 1565 /* ensure that above write is through */ 1566 readl(base + offset); 1567 } 1568 1569 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1570 { 1571 u32 reg; 1572 1573 reg = readl(base + offset); 1574 reg &= ~val; 1575 writel(reg, base + offset); 1576 1577 /* ensure that above write is through */ 1578 readl(base + offset); 1579 } 1580 1581 /* list of clocks required by phy */ 1582 static const char * const ipq8074_pciephy_clk_l[] = { 1583 "aux", "cfg_ahb", 1584 }; 1585 1586 static const char * const msm8996_phy_clk_l[] = { 1587 "aux", "cfg_ahb", "ref", 1588 }; 1589 1590 static const char * const sc8280xp_pciephy_clk_l[] = { 1591 "aux", "cfg_ahb", "ref", "rchng", 1592 }; 1593 1594 static const char * const sdm845_pciephy_clk_l[] = { 1595 "aux", "cfg_ahb", "ref", "refgen", 1596 }; 1597 1598 /* list of regulators */ 1599 static const char * const qmp_phy_vreg_l[] = { 1600 "vdda-phy", "vdda-pll", 1601 }; 1602 1603 /* list of resets */ 1604 static const char * const ipq8074_pciephy_reset_l[] = { 1605 "phy", "common", 1606 }; 1607 1608 static const char * const sdm845_pciephy_reset_l[] = { 1609 "phy", 1610 }; 1611 1612 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 1613 .serdes = 0, 1614 .pcs = 0x0200, 1615 .pcs_misc = 0x0600, 1616 .tx = 0x0e00, 1617 .rx = 0x1000, 1618 .tx2 = 0x1600, 1619 .rx2 = 0x1800, 1620 }; 1621 1622 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1623 .lanes = 1, 1624 1625 .tbls = { 1626 .serdes = ipq8074_pcie_serdes_tbl, 1627 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1628 .tx = ipq8074_pcie_tx_tbl, 1629 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1630 .rx = ipq8074_pcie_rx_tbl, 1631 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1632 .pcs = ipq8074_pcie_pcs_tbl, 1633 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1634 }, 1635 .clk_list = ipq8074_pciephy_clk_l, 1636 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1637 .reset_list = ipq8074_pciephy_reset_l, 1638 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1639 .vreg_list = NULL, 1640 .num_vregs = 0, 1641 .regs = pciephy_regs_layout, 1642 1643 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1644 .phy_status = PHYSTATUS, 1645 }; 1646 1647 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1648 .lanes = 1, 1649 1650 .tbls = { 1651 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1652 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1653 .tx = ipq8074_pcie_gen3_tx_tbl, 1654 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1655 .rx = ipq8074_pcie_gen3_rx_tbl, 1656 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1657 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1658 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1659 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 1660 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 1661 }, 1662 .clk_list = ipq8074_pciephy_clk_l, 1663 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1664 .reset_list = ipq8074_pciephy_reset_l, 1665 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1666 .vreg_list = NULL, 1667 .num_vregs = 0, 1668 .regs = ipq_pciephy_gen3_regs_layout, 1669 1670 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1671 .phy_status = PHYSTATUS, 1672 1673 .pipe_clock_rate = 250000000, 1674 }; 1675 1676 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1677 .lanes = 1, 1678 1679 .tbls = { 1680 .serdes = ipq6018_pcie_serdes_tbl, 1681 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1682 .tx = ipq6018_pcie_tx_tbl, 1683 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1684 .rx = ipq6018_pcie_rx_tbl, 1685 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1686 .pcs = ipq6018_pcie_pcs_tbl, 1687 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1688 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1689 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1690 }, 1691 .clk_list = ipq8074_pciephy_clk_l, 1692 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1693 .reset_list = ipq8074_pciephy_reset_l, 1694 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1695 .vreg_list = NULL, 1696 .num_vregs = 0, 1697 .regs = ipq_pciephy_gen3_regs_layout, 1698 1699 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1700 .phy_status = PHYSTATUS, 1701 }; 1702 1703 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1704 .lanes = 1, 1705 1706 .tbls = { 1707 .serdes = sdm845_qmp_pcie_serdes_tbl, 1708 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1709 .tx = sdm845_qmp_pcie_tx_tbl, 1710 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1711 .rx = sdm845_qmp_pcie_rx_tbl, 1712 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1713 .pcs = sdm845_qmp_pcie_pcs_tbl, 1714 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1715 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1716 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1717 }, 1718 .clk_list = sdm845_pciephy_clk_l, 1719 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1720 .reset_list = sdm845_pciephy_reset_l, 1721 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1722 .vreg_list = qmp_phy_vreg_l, 1723 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1724 .regs = sdm845_qmp_pciephy_regs_layout, 1725 1726 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1727 .phy_status = PHYSTATUS, 1728 }; 1729 1730 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1731 .lanes = 1, 1732 1733 .tbls = { 1734 .serdes = sdm845_qhp_pcie_serdes_tbl, 1735 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1736 .tx = sdm845_qhp_pcie_tx_tbl, 1737 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1738 .rx = sdm845_qhp_pcie_rx_tbl, 1739 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1740 .pcs = sdm845_qhp_pcie_pcs_tbl, 1741 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1742 }, 1743 .clk_list = sdm845_pciephy_clk_l, 1744 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1745 .reset_list = sdm845_pciephy_reset_l, 1746 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1747 .vreg_list = qmp_phy_vreg_l, 1748 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1749 .regs = sdm845_qhp_pciephy_regs_layout, 1750 1751 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1752 .phy_status = PHYSTATUS, 1753 }; 1754 1755 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1756 .lanes = 1, 1757 1758 .tbls = { 1759 .serdes = sm8250_qmp_pcie_serdes_tbl, 1760 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1761 .tx = sm8250_qmp_pcie_tx_tbl, 1762 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1763 .rx = sm8250_qmp_pcie_rx_tbl, 1764 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1765 .pcs = sm8250_qmp_pcie_pcs_tbl, 1766 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1767 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1768 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1769 }, 1770 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1771 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1772 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1773 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1774 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1775 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1776 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1777 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1778 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1779 }, 1780 .clk_list = sdm845_pciephy_clk_l, 1781 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1782 .reset_list = sdm845_pciephy_reset_l, 1783 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1784 .vreg_list = qmp_phy_vreg_l, 1785 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1786 .regs = sm8250_pcie_regs_layout, 1787 1788 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1789 .phy_status = PHYSTATUS, 1790 }; 1791 1792 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1793 .lanes = 2, 1794 1795 .tbls = { 1796 .serdes = sm8250_qmp_pcie_serdes_tbl, 1797 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1798 .tx = sm8250_qmp_pcie_tx_tbl, 1799 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1800 .rx = sm8250_qmp_pcie_rx_tbl, 1801 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1802 .pcs = sm8250_qmp_pcie_pcs_tbl, 1803 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1804 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1805 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1806 }, 1807 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1808 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1809 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1810 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1811 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1812 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1813 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1814 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1815 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1816 }, 1817 .clk_list = sdm845_pciephy_clk_l, 1818 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1819 .reset_list = sdm845_pciephy_reset_l, 1820 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1821 .vreg_list = qmp_phy_vreg_l, 1822 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1823 .regs = sm8250_pcie_regs_layout, 1824 1825 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1826 .phy_status = PHYSTATUS, 1827 }; 1828 1829 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1830 .lanes = 1, 1831 1832 .tbls = { 1833 .serdes = msm8998_pcie_serdes_tbl, 1834 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1835 .tx = msm8998_pcie_tx_tbl, 1836 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1837 .rx = msm8998_pcie_rx_tbl, 1838 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1839 .pcs = msm8998_pcie_pcs_tbl, 1840 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1841 }, 1842 .clk_list = msm8996_phy_clk_l, 1843 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1844 .reset_list = ipq8074_pciephy_reset_l, 1845 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1846 .vreg_list = qmp_phy_vreg_l, 1847 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1848 .regs = pciephy_regs_layout, 1849 1850 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1851 .phy_status = PHYSTATUS, 1852 1853 .skip_start_delay = true, 1854 }; 1855 1856 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1857 .lanes = 1, 1858 1859 .tbls = { 1860 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1861 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1862 .tx = sc8180x_qmp_pcie_tx_tbl, 1863 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1864 .rx = sc8180x_qmp_pcie_rx_tbl, 1865 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1866 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1867 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1868 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1869 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1870 }, 1871 .clk_list = sdm845_pciephy_clk_l, 1872 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1873 .reset_list = sdm845_pciephy_reset_l, 1874 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1875 .vreg_list = qmp_phy_vreg_l, 1876 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1877 .regs = sm8250_pcie_regs_layout, 1878 1879 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1880 .phy_status = PHYSTATUS, 1881 }; 1882 1883 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 1884 .lanes = 1, 1885 1886 .offsets = &qmp_pcie_offsets_v5, 1887 1888 .tbls = { 1889 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1890 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1891 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 1892 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 1893 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 1894 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 1895 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 1896 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 1897 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 1898 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 1899 }, 1900 1901 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1902 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 1903 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 1904 }, 1905 1906 .clk_list = sc8280xp_pciephy_clk_l, 1907 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1908 .reset_list = sdm845_pciephy_reset_l, 1909 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1910 .vreg_list = qmp_phy_vreg_l, 1911 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1912 .regs = sm8250_pcie_regs_layout, 1913 1914 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1915 .phy_status = PHYSTATUS, 1916 }; 1917 1918 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 1919 .lanes = 2, 1920 1921 .offsets = &qmp_pcie_offsets_v5, 1922 1923 .tbls = { 1924 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1925 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1926 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 1927 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 1928 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 1929 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 1930 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 1931 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 1932 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 1933 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 1934 }, 1935 1936 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1937 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 1938 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 1939 }, 1940 1941 .clk_list = sc8280xp_pciephy_clk_l, 1942 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1943 .reset_list = sdm845_pciephy_reset_l, 1944 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1945 .vreg_list = qmp_phy_vreg_l, 1946 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1947 .regs = sm8250_pcie_regs_layout, 1948 1949 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1950 .phy_status = PHYSTATUS, 1951 }; 1952 1953 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 1954 .lanes = 4, 1955 1956 .offsets = &qmp_pcie_offsets_v5, 1957 1958 .tbls = { 1959 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1960 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1961 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 1962 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 1963 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 1964 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 1965 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 1966 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 1967 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 1968 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 1969 }, 1970 1971 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1972 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 1973 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 1974 }, 1975 1976 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 1977 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 1978 1979 .clk_list = sc8280xp_pciephy_clk_l, 1980 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1981 .reset_list = sdm845_pciephy_reset_l, 1982 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1983 .vreg_list = qmp_phy_vreg_l, 1984 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1985 .regs = sm8250_pcie_regs_layout, 1986 1987 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1988 .phy_status = PHYSTATUS, 1989 }; 1990 1991 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1992 .lanes = 2, 1993 1994 .tbls = { 1995 .serdes = sdx55_qmp_pcie_serdes_tbl, 1996 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1997 .tx = sdx55_qmp_pcie_tx_tbl, 1998 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1999 .rx = sdx55_qmp_pcie_rx_tbl, 2000 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 2001 .pcs = sdx55_qmp_pcie_pcs_tbl, 2002 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 2003 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 2004 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 2005 }, 2006 .clk_list = sdm845_pciephy_clk_l, 2007 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2008 .reset_list = sdm845_pciephy_reset_l, 2009 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2010 .vreg_list = qmp_phy_vreg_l, 2011 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2012 .regs = sm8250_pcie_regs_layout, 2013 2014 .pwrdn_ctrl = SW_PWRDN, 2015 .phy_status = PHYSTATUS_4_20, 2016 }; 2017 2018 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 2019 .lanes = 1, 2020 2021 .tbls = { 2022 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 2023 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 2024 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 2025 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 2026 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 2027 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 2028 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 2029 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 2030 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2031 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 2032 }, 2033 .clk_list = sdm845_pciephy_clk_l, 2034 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2035 .reset_list = sdm845_pciephy_reset_l, 2036 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2037 .vreg_list = qmp_phy_vreg_l, 2038 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2039 .regs = sm8250_pcie_regs_layout, 2040 2041 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2042 .phy_status = PHYSTATUS, 2043 }; 2044 2045 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 2046 .lanes = 2, 2047 2048 .tbls = { 2049 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 2050 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 2051 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 2052 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 2053 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 2054 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 2055 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 2056 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 2057 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 2058 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 2059 }, 2060 2061 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2062 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 2063 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 2064 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 2065 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 2066 }, 2067 2068 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2069 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 2070 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 2071 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 2072 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 2073 }, 2074 2075 .clk_list = sdm845_pciephy_clk_l, 2076 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2077 .reset_list = sdm845_pciephy_reset_l, 2078 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2079 .vreg_list = qmp_phy_vreg_l, 2080 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2081 .regs = sm8250_pcie_regs_layout, 2082 2083 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2084 .phy_status = PHYSTATUS_4_20, 2085 }; 2086 2087 static void qmp_pcie_configure_lane(void __iomem *base, 2088 const struct qmp_phy_init_tbl tbl[], 2089 int num, 2090 u8 lane_mask) 2091 { 2092 int i; 2093 const struct qmp_phy_init_tbl *t = tbl; 2094 2095 if (!t) 2096 return; 2097 2098 for (i = 0; i < num; i++, t++) { 2099 if (!(t->lane_mask & lane_mask)) 2100 continue; 2101 2102 writel(t->val, base + t->offset); 2103 } 2104 } 2105 2106 static void qmp_pcie_configure(void __iomem *base, 2107 const struct qmp_phy_init_tbl tbl[], 2108 int num) 2109 { 2110 qmp_pcie_configure_lane(base, tbl, num, 0xff); 2111 } 2112 2113 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2114 { 2115 const struct qmp_phy_cfg *cfg = qmp->cfg; 2116 const struct qmp_pcie_offsets *offs = cfg->offsets; 2117 void __iomem *tx3, *rx3, *tx4, *rx4; 2118 2119 tx3 = qmp->port_b + offs->tx; 2120 rx3 = qmp->port_b + offs->rx; 2121 tx4 = qmp->port_b + offs->tx2; 2122 rx4 = qmp->port_b + offs->rx2; 2123 2124 qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); 2125 qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); 2126 2127 qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); 2128 qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); 2129 } 2130 2131 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2132 { 2133 const struct qmp_phy_cfg *cfg = qmp->cfg; 2134 void __iomem *serdes = qmp->serdes; 2135 void __iomem *tx = qmp->tx; 2136 void __iomem *rx = qmp->rx; 2137 void __iomem *tx2 = qmp->tx2; 2138 void __iomem *rx2 = qmp->rx2; 2139 void __iomem *pcs = qmp->pcs; 2140 void __iomem *pcs_misc = qmp->pcs_misc; 2141 2142 if (!tbls) 2143 return; 2144 2145 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); 2146 2147 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 2148 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 2149 2150 if (cfg->lanes >= 2) { 2151 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 2152 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 2153 } 2154 2155 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); 2156 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 2157 2158 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 2159 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 2160 qmp_pcie_init_port_b(qmp, tbls); 2161 } 2162 } 2163 2164 static int qmp_pcie_init(struct phy *phy) 2165 { 2166 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2167 const struct qmp_phy_cfg *cfg = qmp->cfg; 2168 int ret; 2169 2170 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2171 if (ret) { 2172 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2173 return ret; 2174 } 2175 2176 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2177 if (ret) { 2178 dev_err(qmp->dev, "reset assert failed\n"); 2179 goto err_disable_regulators; 2180 } 2181 2182 usleep_range(200, 300); 2183 2184 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2185 if (ret) { 2186 dev_err(qmp->dev, "reset deassert failed\n"); 2187 goto err_disable_regulators; 2188 } 2189 2190 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2191 if (ret) 2192 goto err_assert_reset; 2193 2194 return 0; 2195 2196 err_assert_reset: 2197 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2198 err_disable_regulators: 2199 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2200 2201 return ret; 2202 } 2203 2204 static int qmp_pcie_exit(struct phy *phy) 2205 { 2206 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2207 const struct qmp_phy_cfg *cfg = qmp->cfg; 2208 2209 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2210 2211 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2212 2213 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2214 2215 return 0; 2216 } 2217 2218 static int qmp_pcie_power_on(struct phy *phy) 2219 { 2220 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2221 const struct qmp_phy_cfg *cfg = qmp->cfg; 2222 const struct qmp_phy_cfg_tbls *mode_tbls; 2223 void __iomem *pcs = qmp->pcs; 2224 void __iomem *status; 2225 unsigned int mask, val; 2226 int ret; 2227 2228 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2229 cfg->pwrdn_ctrl); 2230 2231 if (qmp->mode == PHY_MODE_PCIE_RC) 2232 mode_tbls = cfg->tbls_rc; 2233 else 2234 mode_tbls = cfg->tbls_ep; 2235 2236 qmp_pcie_init_registers(qmp, &cfg->tbls); 2237 qmp_pcie_init_registers(qmp, mode_tbls); 2238 2239 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 2240 if (ret) 2241 return ret; 2242 2243 /* Pull PHY out of reset state */ 2244 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2245 2246 /* start SerDes and Phy-Coding-Sublayer */ 2247 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2248 2249 if (!cfg->skip_start_delay) 2250 usleep_range(1000, 1200); 2251 2252 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2253 mask = cfg->phy_status; 2254 ret = readl_poll_timeout(status, val, !(val & mask), 200, 2255 PHY_INIT_COMPLETE_TIMEOUT); 2256 if (ret) { 2257 dev_err(qmp->dev, "phy initialization timed-out\n"); 2258 goto err_disable_pipe_clk; 2259 } 2260 2261 return 0; 2262 2263 err_disable_pipe_clk: 2264 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2265 2266 return ret; 2267 } 2268 2269 static int qmp_pcie_power_off(struct phy *phy) 2270 { 2271 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2272 const struct qmp_phy_cfg *cfg = qmp->cfg; 2273 2274 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2275 2276 /* PHY reset */ 2277 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2278 2279 /* stop SerDes and Phy-Coding-Sublayer */ 2280 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2281 SERDES_START | PCS_START); 2282 2283 /* Put PHY into POWER DOWN state: active low */ 2284 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2285 cfg->pwrdn_ctrl); 2286 2287 return 0; 2288 } 2289 2290 static int qmp_pcie_enable(struct phy *phy) 2291 { 2292 int ret; 2293 2294 ret = qmp_pcie_init(phy); 2295 if (ret) 2296 return ret; 2297 2298 ret = qmp_pcie_power_on(phy); 2299 if (ret) 2300 qmp_pcie_exit(phy); 2301 2302 return ret; 2303 } 2304 2305 static int qmp_pcie_disable(struct phy *phy) 2306 { 2307 int ret; 2308 2309 ret = qmp_pcie_power_off(phy); 2310 if (ret) 2311 return ret; 2312 2313 return qmp_pcie_exit(phy); 2314 } 2315 2316 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2317 { 2318 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2319 2320 switch (submode) { 2321 case PHY_MODE_PCIE_RC: 2322 case PHY_MODE_PCIE_EP: 2323 qmp->mode = submode; 2324 break; 2325 default: 2326 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2327 return -EINVAL; 2328 } 2329 2330 return 0; 2331 } 2332 2333 static const struct phy_ops qmp_pcie_phy_ops = { 2334 .power_on = qmp_pcie_enable, 2335 .power_off = qmp_pcie_disable, 2336 .set_mode = qmp_pcie_set_mode, 2337 .owner = THIS_MODULE, 2338 }; 2339 2340 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 2341 { 2342 const struct qmp_phy_cfg *cfg = qmp->cfg; 2343 struct device *dev = qmp->dev; 2344 int num = cfg->num_vregs; 2345 int i; 2346 2347 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2348 if (!qmp->vregs) 2349 return -ENOMEM; 2350 2351 for (i = 0; i < num; i++) 2352 qmp->vregs[i].supply = cfg->vreg_list[i]; 2353 2354 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2355 } 2356 2357 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 2358 { 2359 const struct qmp_phy_cfg *cfg = qmp->cfg; 2360 struct device *dev = qmp->dev; 2361 int i; 2362 int ret; 2363 2364 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2365 sizeof(*qmp->resets), GFP_KERNEL); 2366 if (!qmp->resets) 2367 return -ENOMEM; 2368 2369 for (i = 0; i < cfg->num_resets; i++) 2370 qmp->resets[i].id = cfg->reset_list[i]; 2371 2372 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2373 if (ret) 2374 return dev_err_probe(dev, ret, "failed to get resets\n"); 2375 2376 return 0; 2377 } 2378 2379 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 2380 { 2381 const struct qmp_phy_cfg *cfg = qmp->cfg; 2382 struct device *dev = qmp->dev; 2383 int num = cfg->num_clks; 2384 int i; 2385 2386 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2387 if (!qmp->clks) 2388 return -ENOMEM; 2389 2390 for (i = 0; i < num; i++) 2391 qmp->clks[i].id = cfg->clk_list[i]; 2392 2393 return devm_clk_bulk_get(dev, num, qmp->clks); 2394 } 2395 2396 static void phy_clk_release_provider(void *res) 2397 { 2398 of_clk_del_provider(res); 2399 } 2400 2401 /* 2402 * Register a fixed rate pipe clock. 2403 * 2404 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2405 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2406 * by the PHY driver for its operations. 2407 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2408 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2409 * Below picture shows this relationship. 2410 * 2411 * +---------------+ 2412 * | PHY block |<<---------------------------------------+ 2413 * | | | 2414 * | +-------+ | +-----+ | 2415 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2416 * clk | +-------+ | +-----+ 2417 * +---------------+ 2418 */ 2419 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 2420 { 2421 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2422 struct clk_init_data init = { }; 2423 int ret; 2424 2425 ret = of_property_read_string(np, "clock-output-names", &init.name); 2426 if (ret) { 2427 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2428 return ret; 2429 } 2430 2431 init.ops = &clk_fixed_rate_ops; 2432 2433 /* 2434 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2435 * unless other frequency is specified in the PHY config. 2436 */ 2437 if (qmp->cfg->pipe_clock_rate) 2438 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 2439 else 2440 fixed->fixed_rate = 125000000; 2441 2442 fixed->hw.init = &init; 2443 2444 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2445 if (ret) 2446 return ret; 2447 2448 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2449 if (ret) 2450 return ret; 2451 2452 /* 2453 * Roll a devm action because the clock provider is the child node, but 2454 * the child node is not actually a device. 2455 */ 2456 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2457 } 2458 2459 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 2460 { 2461 struct platform_device *pdev = to_platform_device(qmp->dev); 2462 const struct qmp_phy_cfg *cfg = qmp->cfg; 2463 struct device *dev = qmp->dev; 2464 struct clk *clk; 2465 2466 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2467 if (IS_ERR(qmp->serdes)) 2468 return PTR_ERR(qmp->serdes); 2469 2470 /* 2471 * Get memory resources for the PHY: 2472 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2473 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2474 * For single lane PHYs: pcs_misc (optional) -> 3. 2475 */ 2476 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2477 if (IS_ERR(qmp->tx)) 2478 return PTR_ERR(qmp->tx); 2479 2480 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2481 qmp->rx = qmp->tx; 2482 else 2483 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2484 if (IS_ERR(qmp->rx)) 2485 return PTR_ERR(qmp->rx); 2486 2487 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2488 if (IS_ERR(qmp->pcs)) 2489 return PTR_ERR(qmp->pcs); 2490 2491 if (cfg->lanes >= 2) { 2492 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2493 if (IS_ERR(qmp->tx2)) 2494 return PTR_ERR(qmp->tx2); 2495 2496 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2497 if (IS_ERR(qmp->rx2)) 2498 return PTR_ERR(qmp->rx2); 2499 2500 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2501 } else { 2502 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2503 } 2504 2505 if (IS_ERR(qmp->pcs_misc) && 2506 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2507 qmp->pcs_misc = qmp->pcs + 0x400; 2508 2509 if (IS_ERR(qmp->pcs_misc)) { 2510 if (cfg->tbls.pcs_misc || 2511 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 2512 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 2513 return PTR_ERR(qmp->pcs_misc); 2514 } 2515 } 2516 2517 clk = devm_get_clk_from_child(dev, np, NULL); 2518 if (IS_ERR(clk)) { 2519 return dev_err_probe(dev, PTR_ERR(clk), 2520 "failed to get pipe clock\n"); 2521 } 2522 2523 qmp->num_pipe_clks = 1; 2524 qmp->pipe_clks[0].id = "pipe"; 2525 qmp->pipe_clks[0].clk = clk; 2526 2527 return 0; 2528 } 2529 2530 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 2531 { 2532 struct regmap *tcsr; 2533 unsigned int args[2]; 2534 int ret; 2535 2536 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 2537 "qcom,4ln-config-sel", 2538 ARRAY_SIZE(args), args); 2539 if (IS_ERR(tcsr)) { 2540 ret = PTR_ERR(tcsr); 2541 if (ret == -ENOENT) 2542 return 0; 2543 2544 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 2545 return ret; 2546 } 2547 2548 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 2549 if (ret < 0) { 2550 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 2551 return ret; 2552 } 2553 2554 qmp->tcsr_4ln_config = ret; 2555 2556 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 2557 2558 return 0; 2559 } 2560 2561 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 2562 { 2563 struct platform_device *pdev = to_platform_device(qmp->dev); 2564 const struct qmp_phy_cfg *cfg = qmp->cfg; 2565 const struct qmp_pcie_offsets *offs = cfg->offsets; 2566 struct device *dev = qmp->dev; 2567 void __iomem *base; 2568 int ret; 2569 2570 if (!offs) 2571 return -EINVAL; 2572 2573 ret = qmp_pcie_get_4ln_config(qmp); 2574 if (ret) 2575 return ret; 2576 2577 base = devm_platform_ioremap_resource(pdev, 0); 2578 if (IS_ERR(base)) 2579 return PTR_ERR(base); 2580 2581 qmp->serdes = base + offs->serdes; 2582 qmp->pcs = base + offs->pcs; 2583 qmp->pcs_misc = base + offs->pcs_misc; 2584 qmp->tx = base + offs->tx; 2585 qmp->rx = base + offs->rx; 2586 2587 if (cfg->lanes >= 2) { 2588 qmp->tx2 = base + offs->tx2; 2589 qmp->rx2 = base + offs->rx2; 2590 } 2591 2592 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 2593 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 2594 if (IS_ERR(qmp->port_b)) 2595 return PTR_ERR(qmp->port_b); 2596 } 2597 2598 qmp->num_pipe_clks = 2; 2599 qmp->pipe_clks[0].id = "pipe"; 2600 qmp->pipe_clks[1].id = "pipediv2"; 2601 2602 ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks); 2603 if (ret) 2604 return ret; 2605 2606 return 0; 2607 } 2608 2609 static int qmp_pcie_probe(struct platform_device *pdev) 2610 { 2611 struct device *dev = &pdev->dev; 2612 struct phy_provider *phy_provider; 2613 struct device_node *np; 2614 struct qmp_pcie *qmp; 2615 int ret; 2616 2617 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2618 if (!qmp) 2619 return -ENOMEM; 2620 2621 qmp->dev = dev; 2622 2623 qmp->cfg = of_device_get_match_data(dev); 2624 if (!qmp->cfg) 2625 return -EINVAL; 2626 2627 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 2628 WARN_ON_ONCE(!qmp->cfg->phy_status); 2629 2630 ret = qmp_pcie_clk_init(qmp); 2631 if (ret) 2632 return ret; 2633 2634 ret = qmp_pcie_reset_init(qmp); 2635 if (ret) 2636 return ret; 2637 2638 ret = qmp_pcie_vreg_init(qmp); 2639 if (ret) 2640 return ret; 2641 2642 /* Check for legacy binding with child node. */ 2643 np = of_get_next_available_child(dev->of_node, NULL); 2644 if (np) { 2645 ret = qmp_pcie_parse_dt_legacy(qmp, np); 2646 } else { 2647 np = of_node_get(dev->of_node); 2648 ret = qmp_pcie_parse_dt(qmp); 2649 } 2650 if (ret) 2651 goto err_node_put; 2652 2653 ret = phy_pipe_clk_register(qmp, np); 2654 if (ret) 2655 goto err_node_put; 2656 2657 qmp->mode = PHY_MODE_PCIE_RC; 2658 2659 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 2660 if (IS_ERR(qmp->phy)) { 2661 ret = PTR_ERR(qmp->phy); 2662 dev_err(dev, "failed to create PHY: %d\n", ret); 2663 goto err_node_put; 2664 } 2665 2666 phy_set_drvdata(qmp->phy, qmp); 2667 2668 of_node_put(np); 2669 2670 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2671 2672 return PTR_ERR_OR_ZERO(phy_provider); 2673 2674 err_node_put: 2675 of_node_put(np); 2676 return ret; 2677 } 2678 2679 static const struct of_device_id qmp_pcie_of_match_table[] = { 2680 { 2681 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2682 .data = &ipq6018_pciephy_cfg, 2683 }, { 2684 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2685 .data = &ipq8074_pciephy_gen3_cfg, 2686 }, { 2687 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2688 .data = &ipq8074_pciephy_cfg, 2689 }, { 2690 .compatible = "qcom,msm8998-qmp-pcie-phy", 2691 .data = &msm8998_pciephy_cfg, 2692 }, { 2693 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2694 .data = &sc8180x_pciephy_cfg, 2695 }, { 2696 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 2697 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 2698 }, { 2699 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 2700 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 2701 }, { 2702 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 2703 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 2704 }, { 2705 .compatible = "qcom,sdm845-qhp-pcie-phy", 2706 .data = &sdm845_qhp_pciephy_cfg, 2707 }, { 2708 .compatible = "qcom,sdm845-qmp-pcie-phy", 2709 .data = &sdm845_qmp_pciephy_cfg, 2710 }, { 2711 .compatible = "qcom,sdx55-qmp-pcie-phy", 2712 .data = &sdx55_qmp_pciephy_cfg, 2713 }, { 2714 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2715 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2716 }, { 2717 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2718 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2719 }, { 2720 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2721 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2722 }, { 2723 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2724 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2725 }, { 2726 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2727 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2728 }, 2729 { }, 2730 }; 2731 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2732 2733 static struct platform_driver qmp_pcie_driver = { 2734 .probe = qmp_pcie_probe, 2735 .driver = { 2736 .name = "qcom-qmp-pcie-phy", 2737 .of_match_table = qmp_pcie_of_match_table, 2738 }, 2739 }; 2740 2741 module_platform_driver(qmp_pcie_driver); 2742 2743 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2744 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2745 MODULE_LICENSE("GPL v2"); 2746