1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 #define REFCLK_DRV_DSBL BIT(1) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 #define PLL_READY_GATE_EN BIT(3) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ 40 #define PCS_READY BIT(0) 41 42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 43 /* DP PHY soft reset */ 44 #define SW_DPPHY_RESET BIT(0) 45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_DPPHY_RESET_MUX BIT(1) 47 /* USB3 PHY soft reset */ 48 #define SW_USB3PHY_RESET BIT(2) 49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 50 #define SW_USB3PHY_RESET_MUX BIT(3) 51 52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 53 #define USB3_MODE BIT(0) /* enables USB3 mode */ 54 #define DP_MODE BIT(1) /* enables DP mode */ 55 56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 57 #define ARCVR_DTCT_EN BIT(0) 58 #define ALFPS_DTCT_EN BIT(1) 59 #define ARCVR_DTCT_EVENT_SEL BIT(4) 60 61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 62 #define IRQ_CLEAR BIT(0) 63 64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 65 #define RCVR_DETECT BIT(0) 66 67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 68 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 69 70 #define PHY_INIT_COMPLETE_TIMEOUT 10000 71 #define POWER_DOWN_DELAY_US_MIN 10 72 #define POWER_DOWN_DELAY_US_MAX 11 73 74 #define MAX_PROP_NAME 32 75 76 /* Define the assumed distance between lanes for underspecified device trees. */ 77 #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 78 79 struct qmp_phy_init_tbl { 80 unsigned int offset; 81 unsigned int val; 82 /* 83 * register part of layout ? 84 * if yes, then offset gives index in the reg-layout 85 */ 86 bool in_layout; 87 /* 88 * mask of lanes for which this register is written 89 * for cases when second lane needs different values 90 */ 91 u8 lane_mask; 92 }; 93 94 #define QMP_PHY_INIT_CFG(o, v) \ 95 { \ 96 .offset = o, \ 97 .val = v, \ 98 .lane_mask = 0xff, \ 99 } 100 101 #define QMP_PHY_INIT_CFG_L(o, v) \ 102 { \ 103 .offset = o, \ 104 .val = v, \ 105 .in_layout = true, \ 106 .lane_mask = 0xff, \ 107 } 108 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 110 { \ 111 .offset = o, \ 112 .val = v, \ 113 .lane_mask = l, \ 114 } 115 116 /* set of registers with offsets different per-PHY */ 117 enum qphy_reg_layout { 118 /* Common block control registers */ 119 QPHY_COM_SW_RESET, 120 QPHY_COM_POWER_DOWN_CONTROL, 121 QPHY_COM_START_CONTROL, 122 QPHY_COM_PCS_READY_STATUS, 123 /* PCS registers */ 124 QPHY_SW_RESET, 125 QPHY_START_CTRL, 126 QPHY_PCS_READY_STATUS, 127 QPHY_PCS_STATUS, 128 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 129 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 130 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 131 QPHY_PCS_POWER_DOWN_CONTROL, 132 /* PCS_MISC registers */ 133 QPHY_PCS_MISC_TYPEC_CTRL, 134 /* Keep last to ensure regs_layout arrays are properly initialized */ 135 QPHY_LAYOUT_SIZE 136 }; 137 138 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 139 [QPHY_SW_RESET] = 0x00, 140 [QPHY_START_CTRL] = 0x44, 141 [QPHY_PCS_STATUS] = 0x14, 142 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 143 }; 144 145 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 146 [QPHY_COM_SW_RESET] = 0x400, 147 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 148 [QPHY_COM_START_CONTROL] = 0x408, 149 [QPHY_COM_PCS_READY_STATUS] = 0x448, 150 [QPHY_SW_RESET] = 0x00, 151 [QPHY_START_CTRL] = 0x08, 152 [QPHY_PCS_STATUS] = 0x174, 153 }; 154 155 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 156 [QPHY_SW_RESET] = 0x00, 157 [QPHY_START_CTRL] = 0x08, 158 [QPHY_PCS_STATUS] = 0x174, 159 }; 160 161 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 162 [QPHY_SW_RESET] = 0x00, 163 [QPHY_START_CTRL] = 0x08, 164 [QPHY_PCS_STATUS] = 0x2ac, 165 }; 166 167 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 168 [QPHY_SW_RESET] = 0x00, 169 [QPHY_START_CTRL] = 0x44, 170 [QPHY_PCS_STATUS] = 0x14, 171 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 172 }; 173 174 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 175 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 176 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 177 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 178 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 179 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 180 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 181 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 182 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 183 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 184 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 185 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 186 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 187 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 195 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 196 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 205 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 206 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 217 }; 218 219 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 220 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 221 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 222 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 223 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 224 }; 225 226 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 227 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 228 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 229 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 230 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 231 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 232 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 233 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 234 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 235 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 236 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 237 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 238 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 239 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 240 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 241 }; 242 243 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 244 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 245 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 246 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 247 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 248 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 249 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 250 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 251 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 252 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 253 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 254 }; 255 256 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 257 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 258 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 259 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 260 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 261 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 262 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 263 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 264 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 265 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 266 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 267 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 268 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 269 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 270 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 271 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 272 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 273 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 274 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 275 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 276 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 277 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 278 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 279 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 280 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 281 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 282 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 283 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 284 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 285 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 286 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 287 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 288 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 289 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 290 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 291 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 292 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 293 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 294 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 295 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 296 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 297 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 298 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 299 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 300 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 301 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 302 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 303 }; 304 305 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 306 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 307 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 308 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 309 }; 310 311 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 312 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 313 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 314 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 315 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 316 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 317 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 318 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 319 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 320 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 321 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 322 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 323 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 324 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 325 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 326 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 327 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 328 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 329 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 330 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 331 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 332 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 333 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 334 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 335 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 336 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 337 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 338 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 339 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 340 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 341 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 342 }; 343 344 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 345 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 346 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 347 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 348 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 349 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 350 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 351 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 352 }; 353 354 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 355 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 356 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 357 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 358 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 359 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 360 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 361 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 362 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 363 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 364 }; 365 366 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 367 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 368 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 369 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 370 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 371 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 372 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 373 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 374 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 375 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 376 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 377 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 378 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 379 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 380 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 381 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 382 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 383 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 384 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 385 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 386 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 387 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 388 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 389 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 390 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 391 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 392 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 393 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 394 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 395 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 396 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 397 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 398 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 399 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 400 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 401 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 402 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 403 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 404 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 405 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 406 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 407 }; 408 409 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 410 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 411 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 412 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 413 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 414 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 415 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 416 }; 417 418 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 419 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 420 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 421 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 422 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 423 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 424 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 425 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 426 }; 427 428 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 429 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 430 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 431 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 432 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 433 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 434 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 435 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 436 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 437 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 438 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 439 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 440 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 441 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 442 }; 443 444 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 445 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 446 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 447 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 448 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 449 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 450 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 451 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 452 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 453 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 454 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 455 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 456 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 457 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 458 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 459 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 460 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 461 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 462 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 463 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 464 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 465 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 466 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 467 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 468 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 469 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 470 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 471 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 472 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 473 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 474 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 475 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 476 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 477 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 478 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 479 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 480 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 481 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 482 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 483 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 484 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 485 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 486 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 487 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 488 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 489 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 490 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 491 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 492 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 493 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 494 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 495 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 496 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 497 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 498 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 499 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 500 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 501 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 502 }; 503 504 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 505 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 506 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 507 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 508 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 509 }; 510 511 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 542 }; 543 544 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 545 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 546 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 547 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 548 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 549 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 550 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 551 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 552 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 553 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 554 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 555 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 556 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 557 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 558 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 559 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 560 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 561 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 562 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 563 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 567 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 569 }; 570 571 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 572 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 573 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 574 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 575 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 576 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 577 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 578 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 579 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 580 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 581 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 582 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 583 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 584 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 585 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 586 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 587 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 588 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 589 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 590 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 591 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 592 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 593 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 594 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 595 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 596 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 597 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 598 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 599 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 600 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 601 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 602 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 603 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 604 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 605 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 606 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 607 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 608 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 609 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 610 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 611 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 613 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 614 }; 615 616 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 617 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 618 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 619 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 620 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 621 }; 622 623 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 624 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 625 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 626 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 627 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 628 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 629 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 630 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 631 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 632 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 633 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 634 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 635 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 636 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 637 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 638 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 639 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 640 }; 641 642 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 643 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 644 645 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 646 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 647 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 648 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 649 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 650 651 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 652 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 653 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 654 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 655 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 656 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 657 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 658 659 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 660 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 661 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 662 663 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 664 }; 665 666 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 667 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 668 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 669 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 670 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 671 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 672 }; 673 674 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 720 }; 721 722 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 730 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 731 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 735 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 736 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 737 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 738 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 739 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 740 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 741 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 742 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 743 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 744 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 745 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 746 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 747 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 748 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 749 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 750 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 751 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 752 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 753 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 754 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 755 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 756 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 757 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 758 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 759 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 760 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 761 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 762 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 763 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 764 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 765 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 766 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 767 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 768 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 769 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 770 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 771 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 772 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 773 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 774 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 775 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 776 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 777 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 778 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 779 }; 780 781 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 782 }; 783 784 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 785 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 786 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 787 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 788 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 789 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 790 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 791 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 792 }; 793 794 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 795 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 796 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 797 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 798 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 799 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 800 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 801 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 802 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 803 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 804 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 805 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 837 }; 838 839 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 840 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 841 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 842 }; 843 844 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 845 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 846 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 847 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 852 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 853 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 854 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 855 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 856 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 881 }; 882 883 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 884 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 885 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 886 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 887 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 888 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 889 }; 890 891 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 892 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 893 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 894 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 895 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 896 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 899 }; 900 901 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 903 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 904 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 905 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 906 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 907 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 908 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 909 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 910 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 911 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 912 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 913 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 914 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 915 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 916 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 917 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 918 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 919 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 920 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 923 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 924 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 925 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 933 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 934 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 935 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 936 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 937 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 938 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 939 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 940 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 941 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 942 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 943 }; 944 945 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 946 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 947 }; 948 949 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 950 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 951 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 952 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 953 }; 954 955 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 960 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 961 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 962 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 963 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 964 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 965 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 966 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 967 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 968 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 969 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 970 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 971 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 972 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 973 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 974 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 975 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 976 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 977 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 978 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 979 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 980 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 981 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 982 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 983 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 984 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 985 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 986 }; 987 988 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 989 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 990 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 991 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 992 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 993 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 994 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 995 }; 996 997 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 998 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 999 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1000 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1001 }; 1002 1003 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1004 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1005 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1006 }; 1007 1008 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1009 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1010 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1011 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1012 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1013 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1014 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1015 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1016 }; 1017 1018 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1019 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1020 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1021 }; 1022 1023 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1024 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1025 }; 1026 1027 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1032 }; 1033 1034 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1035 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1036 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1037 }; 1038 1039 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1040 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1041 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1042 }; 1043 1044 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1045 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1074 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1076 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1077 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1078 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1079 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1080 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1081 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1082 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1083 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1084 }; 1085 1086 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1087 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1088 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1089 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1090 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1091 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1092 }; 1093 1094 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1095 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1096 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1097 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1098 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1099 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1100 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1101 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1102 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1103 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1104 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1105 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1106 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1107 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1108 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1109 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1110 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1111 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1112 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1113 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1114 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1115 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1116 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1117 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1118 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1119 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1120 }; 1121 1122 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1123 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1124 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1125 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1126 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1127 }; 1128 1129 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1130 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1131 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1132 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1133 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1134 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1135 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1136 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1137 }; 1138 1139 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1140 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1182 }; 1183 1184 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1185 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1190 }; 1191 1192 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1193 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1215 }; 1216 1217 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1218 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1219 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1220 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1221 }; 1222 1223 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1224 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1225 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1226 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1227 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1228 }; 1229 1230 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1264 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1265 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1272 }; 1273 1274 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1275 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1279 }; 1280 1281 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1282 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1299 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1300 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1301 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1302 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1306 1307 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1308 1309 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1310 1311 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1319 1320 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1326 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1327 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1329 }; 1330 1331 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1332 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1333 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1334 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1335 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1336 }; 1337 1338 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1339 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1340 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1341 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1342 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1343 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1344 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1345 }; 1346 1347 struct qmp_phy; 1348 1349 /* struct qmp_phy_cfg - per-PHY initialization config */ 1350 struct qmp_phy_cfg { 1351 /* phy-type - PCIE/UFS/USB */ 1352 unsigned int type; 1353 /* number of lanes provided by phy */ 1354 int nlanes; 1355 1356 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1357 const struct qmp_phy_init_tbl *serdes_tbl; 1358 int serdes_tbl_num; 1359 const struct qmp_phy_init_tbl *serdes_tbl_sec; 1360 int serdes_tbl_num_sec; 1361 const struct qmp_phy_init_tbl *tx_tbl; 1362 int tx_tbl_num; 1363 const struct qmp_phy_init_tbl *tx_tbl_sec; 1364 int tx_tbl_num_sec; 1365 const struct qmp_phy_init_tbl *rx_tbl; 1366 int rx_tbl_num; 1367 const struct qmp_phy_init_tbl *rx_tbl_sec; 1368 int rx_tbl_num_sec; 1369 const struct qmp_phy_init_tbl *pcs_tbl; 1370 int pcs_tbl_num; 1371 const struct qmp_phy_init_tbl *pcs_tbl_sec; 1372 int pcs_tbl_num_sec; 1373 const struct qmp_phy_init_tbl *pcs_misc_tbl; 1374 int pcs_misc_tbl_num; 1375 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 1376 int pcs_misc_tbl_num_sec; 1377 1378 /* clock ids to be requested */ 1379 const char * const *clk_list; 1380 int num_clks; 1381 /* resets to be requested */ 1382 const char * const *reset_list; 1383 int num_resets; 1384 /* regulators to be requested */ 1385 const char * const *vreg_list; 1386 int num_vregs; 1387 1388 /* array of registers with different offsets */ 1389 const unsigned int *regs; 1390 1391 unsigned int start_ctrl; 1392 unsigned int pwrdn_ctrl; 1393 unsigned int mask_com_pcs_ready; 1394 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1395 unsigned int phy_status; 1396 1397 /* true, if PHY needs delay after POWER_DOWN */ 1398 bool has_pwrdn_delay; 1399 /* power_down delay in usec */ 1400 int pwrdn_delay_min; 1401 int pwrdn_delay_max; 1402 1403 /* true, if PHY has secondary tx/rx lanes to be configured */ 1404 bool is_dual_lane_phy; 1405 1406 /* QMP PHY pipe clock interface rate */ 1407 unsigned long pipe_clock_rate; 1408 }; 1409 1410 /** 1411 * struct qmp_phy - per-lane phy descriptor 1412 * 1413 * @phy: generic phy 1414 * @cfg: phy specific configuration 1415 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1416 * @tx: iomapped memory space for lane's tx 1417 * @rx: iomapped memory space for lane's rx 1418 * @pcs: iomapped memory space for lane's pcs 1419 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1420 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1421 * @pcs_misc: iomapped memory space for lane's pcs_misc 1422 * @pipe_clk: pipe clock 1423 * @index: lane index 1424 * @qmp: QMP phy to which this lane belongs 1425 * @mode: current PHY mode 1426 */ 1427 struct qmp_phy { 1428 struct phy *phy; 1429 const struct qmp_phy_cfg *cfg; 1430 void __iomem *serdes; 1431 void __iomem *tx; 1432 void __iomem *rx; 1433 void __iomem *pcs; 1434 void __iomem *tx2; 1435 void __iomem *rx2; 1436 void __iomem *pcs_misc; 1437 struct clk *pipe_clk; 1438 unsigned int index; 1439 struct qcom_qmp *qmp; 1440 enum phy_mode mode; 1441 }; 1442 1443 /** 1444 * struct qcom_qmp - structure holding QMP phy block attributes 1445 * 1446 * @dev: device 1447 * 1448 * @clks: array of clocks required by phy 1449 * @resets: array of resets required by phy 1450 * @vregs: regulator supplies bulk data 1451 * 1452 * @phys: array of per-lane phy descriptors 1453 */ 1454 struct qcom_qmp { 1455 struct device *dev; 1456 1457 struct clk_bulk_data *clks; 1458 struct reset_control_bulk_data *resets; 1459 struct regulator_bulk_data *vregs; 1460 1461 struct qmp_phy **phys; 1462 }; 1463 1464 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1465 { 1466 u32 reg; 1467 1468 reg = readl(base + offset); 1469 reg |= val; 1470 writel(reg, base + offset); 1471 1472 /* ensure that above write is through */ 1473 readl(base + offset); 1474 } 1475 1476 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1477 { 1478 u32 reg; 1479 1480 reg = readl(base + offset); 1481 reg &= ~val; 1482 writel(reg, base + offset); 1483 1484 /* ensure that above write is through */ 1485 readl(base + offset); 1486 } 1487 1488 /* list of clocks required by phy */ 1489 static const char * const msm8996_phy_clk_l[] = { 1490 "aux", "cfg_ahb", "ref", 1491 }; 1492 1493 1494 static const char * const sdm845_pciephy_clk_l[] = { 1495 "aux", "cfg_ahb", "ref", "refgen", 1496 }; 1497 1498 /* list of regulators */ 1499 static const char * const qmp_phy_vreg_l[] = { 1500 "vdda-phy", "vdda-pll", 1501 }; 1502 1503 static const char * const ipq8074_pciephy_clk_l[] = { 1504 "aux", "cfg_ahb", 1505 }; 1506 1507 /* list of resets */ 1508 static const char * const ipq8074_pciephy_reset_l[] = { 1509 "phy", "common", 1510 }; 1511 1512 static const char * const sdm845_pciephy_reset_l[] = { 1513 "phy", 1514 }; 1515 1516 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1517 .type = PHY_TYPE_PCIE, 1518 .nlanes = 1, 1519 1520 .serdes_tbl = ipq8074_pcie_serdes_tbl, 1521 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1522 .tx_tbl = ipq8074_pcie_tx_tbl, 1523 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1524 .rx_tbl = ipq8074_pcie_rx_tbl, 1525 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1526 .pcs_tbl = ipq8074_pcie_pcs_tbl, 1527 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1528 .clk_list = ipq8074_pciephy_clk_l, 1529 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1530 .reset_list = ipq8074_pciephy_reset_l, 1531 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1532 .vreg_list = NULL, 1533 .num_vregs = 0, 1534 .regs = pciephy_regs_layout, 1535 1536 .start_ctrl = SERDES_START | PCS_START, 1537 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1538 .phy_status = PHYSTATUS, 1539 1540 .has_pwrdn_delay = true, 1541 .pwrdn_delay_min = 995, /* us */ 1542 .pwrdn_delay_max = 1005, /* us */ 1543 }; 1544 1545 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1546 .type = PHY_TYPE_PCIE, 1547 .nlanes = 1, 1548 1549 .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, 1550 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1551 .tx_tbl = ipq8074_pcie_gen3_tx_tbl, 1552 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1553 .rx_tbl = ipq8074_pcie_gen3_rx_tbl, 1554 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1555 .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, 1556 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1557 .clk_list = ipq8074_pciephy_clk_l, 1558 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1559 .reset_list = ipq8074_pciephy_reset_l, 1560 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1561 .vreg_list = NULL, 1562 .num_vregs = 0, 1563 .regs = ipq_pciephy_gen3_regs_layout, 1564 1565 .start_ctrl = SERDES_START | PCS_START, 1566 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1567 1568 .has_pwrdn_delay = true, 1569 .pwrdn_delay_min = 995, /* us */ 1570 .pwrdn_delay_max = 1005, /* us */ 1571 1572 .pipe_clock_rate = 250000000, 1573 }; 1574 1575 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1576 .type = PHY_TYPE_PCIE, 1577 .nlanes = 1, 1578 1579 .serdes_tbl = ipq6018_pcie_serdes_tbl, 1580 .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1581 .tx_tbl = ipq6018_pcie_tx_tbl, 1582 .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1583 .rx_tbl = ipq6018_pcie_rx_tbl, 1584 .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1585 .pcs_tbl = ipq6018_pcie_pcs_tbl, 1586 .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1587 .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl, 1588 .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1589 .clk_list = ipq8074_pciephy_clk_l, 1590 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1591 .reset_list = ipq8074_pciephy_reset_l, 1592 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1593 .vreg_list = NULL, 1594 .num_vregs = 0, 1595 .regs = ipq_pciephy_gen3_regs_layout, 1596 1597 .start_ctrl = SERDES_START | PCS_START, 1598 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1599 1600 .has_pwrdn_delay = true, 1601 .pwrdn_delay_min = 995, /* us */ 1602 .pwrdn_delay_max = 1005, /* us */ 1603 }; 1604 1605 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1606 .type = PHY_TYPE_PCIE, 1607 .nlanes = 1, 1608 1609 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, 1610 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1611 .tx_tbl = sdm845_qmp_pcie_tx_tbl, 1612 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1613 .rx_tbl = sdm845_qmp_pcie_rx_tbl, 1614 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1615 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, 1616 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1617 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, 1618 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1619 .clk_list = sdm845_pciephy_clk_l, 1620 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1621 .reset_list = sdm845_pciephy_reset_l, 1622 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1623 .vreg_list = qmp_phy_vreg_l, 1624 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1625 .regs = sdm845_qmp_pciephy_regs_layout, 1626 1627 .start_ctrl = PCS_START | SERDES_START, 1628 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1629 .phy_status = PHYSTATUS, 1630 1631 .has_pwrdn_delay = true, 1632 .pwrdn_delay_min = 995, /* us */ 1633 .pwrdn_delay_max = 1005, /* us */ 1634 }; 1635 1636 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1637 .type = PHY_TYPE_PCIE, 1638 .nlanes = 1, 1639 1640 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, 1641 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1642 .tx_tbl = sdm845_qhp_pcie_tx_tbl, 1643 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1644 .rx_tbl = sdm845_qhp_pcie_rx_tbl, 1645 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1646 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, 1647 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1648 .clk_list = sdm845_pciephy_clk_l, 1649 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1650 .reset_list = sdm845_pciephy_reset_l, 1651 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1652 .vreg_list = qmp_phy_vreg_l, 1653 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1654 .regs = sdm845_qhp_pciephy_regs_layout, 1655 1656 .start_ctrl = PCS_START | SERDES_START, 1657 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1658 .phy_status = PHYSTATUS, 1659 1660 .has_pwrdn_delay = true, 1661 .pwrdn_delay_min = 995, /* us */ 1662 .pwrdn_delay_max = 1005, /* us */ 1663 }; 1664 1665 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1666 .type = PHY_TYPE_PCIE, 1667 .nlanes = 1, 1668 1669 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 1670 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1671 .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1672 .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1673 .tx_tbl = sm8250_qmp_pcie_tx_tbl, 1674 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1675 .rx_tbl = sm8250_qmp_pcie_rx_tbl, 1676 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1677 .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, 1678 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1679 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 1680 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1681 .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1682 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1683 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 1684 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1685 .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1686 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1687 .clk_list = sdm845_pciephy_clk_l, 1688 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1689 .reset_list = sdm845_pciephy_reset_l, 1690 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1691 .vreg_list = qmp_phy_vreg_l, 1692 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1693 .regs = sm8250_pcie_regs_layout, 1694 1695 .start_ctrl = PCS_START | SERDES_START, 1696 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1697 .phy_status = PHYSTATUS, 1698 1699 .has_pwrdn_delay = true, 1700 .pwrdn_delay_min = 995, /* us */ 1701 .pwrdn_delay_max = 1005, /* us */ 1702 }; 1703 1704 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1705 .type = PHY_TYPE_PCIE, 1706 .nlanes = 2, 1707 1708 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 1709 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1710 .tx_tbl = sm8250_qmp_pcie_tx_tbl, 1711 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1712 .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, 1713 .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1714 .rx_tbl = sm8250_qmp_pcie_rx_tbl, 1715 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1716 .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, 1717 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1718 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 1719 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1720 .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1721 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1722 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 1723 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1724 .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1725 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1726 .clk_list = sdm845_pciephy_clk_l, 1727 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1728 .reset_list = sdm845_pciephy_reset_l, 1729 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1730 .vreg_list = qmp_phy_vreg_l, 1731 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1732 .regs = sm8250_pcie_regs_layout, 1733 1734 .start_ctrl = PCS_START | SERDES_START, 1735 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1736 .phy_status = PHYSTATUS, 1737 1738 .is_dual_lane_phy = true, 1739 .has_pwrdn_delay = true, 1740 .pwrdn_delay_min = 995, /* us */ 1741 .pwrdn_delay_max = 1005, /* us */ 1742 }; 1743 1744 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1745 .type = PHY_TYPE_PCIE, 1746 .nlanes = 1, 1747 1748 .serdes_tbl = msm8998_pcie_serdes_tbl, 1749 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1750 .tx_tbl = msm8998_pcie_tx_tbl, 1751 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1752 .rx_tbl = msm8998_pcie_rx_tbl, 1753 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1754 .pcs_tbl = msm8998_pcie_pcs_tbl, 1755 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1756 .clk_list = msm8996_phy_clk_l, 1757 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1758 .reset_list = ipq8074_pciephy_reset_l, 1759 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1760 .vreg_list = qmp_phy_vreg_l, 1761 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1762 .regs = pciephy_regs_layout, 1763 1764 .start_ctrl = SERDES_START | PCS_START, 1765 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1766 .phy_status = PHYSTATUS, 1767 }; 1768 1769 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1770 .type = PHY_TYPE_PCIE, 1771 .nlanes = 1, 1772 1773 .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, 1774 .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1775 .tx_tbl = sc8180x_qmp_pcie_tx_tbl, 1776 .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1777 .rx_tbl = sc8180x_qmp_pcie_rx_tbl, 1778 .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1779 .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, 1780 .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1781 .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, 1782 .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1783 .clk_list = sdm845_pciephy_clk_l, 1784 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1785 .reset_list = sdm845_pciephy_reset_l, 1786 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1787 .vreg_list = qmp_phy_vreg_l, 1788 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1789 .regs = sm8250_pcie_regs_layout, 1790 1791 .start_ctrl = PCS_START | SERDES_START, 1792 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1793 1794 .has_pwrdn_delay = true, 1795 .pwrdn_delay_min = 995, /* us */ 1796 .pwrdn_delay_max = 1005, /* us */ 1797 }; 1798 1799 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1800 .type = PHY_TYPE_PCIE, 1801 .nlanes = 2, 1802 1803 .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, 1804 .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1805 .tx_tbl = sdx55_qmp_pcie_tx_tbl, 1806 .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1807 .rx_tbl = sdx55_qmp_pcie_rx_tbl, 1808 .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1809 .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, 1810 .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1811 .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, 1812 .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1813 .clk_list = sdm845_pciephy_clk_l, 1814 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1815 .reset_list = sdm845_pciephy_reset_l, 1816 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1817 .vreg_list = qmp_phy_vreg_l, 1818 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1819 .regs = sm8250_pcie_regs_layout, 1820 1821 .start_ctrl = PCS_START | SERDES_START, 1822 .pwrdn_ctrl = SW_PWRDN, 1823 .phy_status = PHYSTATUS_4_20, 1824 1825 .is_dual_lane_phy = true, 1826 .has_pwrdn_delay = true, 1827 .pwrdn_delay_min = 995, /* us */ 1828 .pwrdn_delay_max = 1005, /* us */ 1829 }; 1830 1831 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1832 .type = PHY_TYPE_PCIE, 1833 .nlanes = 1, 1834 1835 .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1836 .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1837 .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, 1838 .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1839 .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, 1840 .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1841 .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1842 .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1843 .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1844 .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1845 .clk_list = sdm845_pciephy_clk_l, 1846 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1847 .reset_list = sdm845_pciephy_reset_l, 1848 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1849 .vreg_list = qmp_phy_vreg_l, 1850 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1851 .regs = sm8250_pcie_regs_layout, 1852 1853 .start_ctrl = SERDES_START | PCS_START, 1854 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1855 .phy_status = PHYSTATUS, 1856 1857 .has_pwrdn_delay = true, 1858 .pwrdn_delay_min = 995, /* us */ 1859 .pwrdn_delay_max = 1005, /* us */ 1860 }; 1861 1862 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1863 .type = PHY_TYPE_PCIE, 1864 .nlanes = 2, 1865 1866 .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1867 .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1868 .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, 1869 .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1870 .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, 1871 .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1872 .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1873 .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1874 .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1875 .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1876 .clk_list = sdm845_pciephy_clk_l, 1877 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1878 .reset_list = sdm845_pciephy_reset_l, 1879 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1880 .vreg_list = qmp_phy_vreg_l, 1881 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1882 .regs = sm8250_pcie_regs_layout, 1883 1884 .start_ctrl = SERDES_START | PCS_START, 1885 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1886 .phy_status = PHYSTATUS_4_20, 1887 1888 .is_dual_lane_phy = true, 1889 .has_pwrdn_delay = true, 1890 .pwrdn_delay_min = 995, /* us */ 1891 .pwrdn_delay_max = 1005, /* us */ 1892 }; 1893 1894 static void qcom_qmp_phy_pcie_configure_lane(void __iomem *base, 1895 const unsigned int *regs, 1896 const struct qmp_phy_init_tbl tbl[], 1897 int num, 1898 u8 lane_mask) 1899 { 1900 int i; 1901 const struct qmp_phy_init_tbl *t = tbl; 1902 1903 if (!t) 1904 return; 1905 1906 for (i = 0; i < num; i++, t++) { 1907 if (!(t->lane_mask & lane_mask)) 1908 continue; 1909 1910 if (t->in_layout) 1911 writel(t->val, base + regs[t->offset]); 1912 else 1913 writel(t->val, base + t->offset); 1914 } 1915 } 1916 1917 static void qcom_qmp_phy_pcie_configure(void __iomem *base, 1918 const unsigned int *regs, 1919 const struct qmp_phy_init_tbl tbl[], 1920 int num) 1921 { 1922 qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff); 1923 } 1924 1925 static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) 1926 { 1927 const struct qmp_phy_cfg *cfg = qphy->cfg; 1928 void __iomem *serdes = qphy->serdes; 1929 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1930 int serdes_tbl_num = cfg->serdes_tbl_num; 1931 1932 qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 1933 if (cfg->serdes_tbl_sec) 1934 qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 1935 cfg->serdes_tbl_num_sec); 1936 1937 return 0; 1938 } 1939 1940 static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) 1941 { 1942 struct qcom_qmp *qmp = qphy->qmp; 1943 const struct qmp_phy_cfg *cfg = qphy->cfg; 1944 void __iomem *pcs = qphy->pcs; 1945 int ret; 1946 1947 /* turn on regulator supplies */ 1948 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1949 if (ret) { 1950 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1951 return ret; 1952 } 1953 1954 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1955 if (ret) { 1956 dev_err(qmp->dev, "reset assert failed\n"); 1957 goto err_disable_regulators; 1958 } 1959 1960 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1961 if (ret) { 1962 dev_err(qmp->dev, "reset deassert failed\n"); 1963 goto err_disable_regulators; 1964 } 1965 1966 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1967 if (ret) 1968 goto err_assert_reset; 1969 1970 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1971 qphy_setbits(pcs, 1972 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1973 cfg->pwrdn_ctrl); 1974 else 1975 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 1976 cfg->pwrdn_ctrl); 1977 1978 return 0; 1979 1980 err_assert_reset: 1981 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1982 err_disable_regulators: 1983 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1984 1985 return ret; 1986 } 1987 1988 static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) 1989 { 1990 struct qcom_qmp *qmp = qphy->qmp; 1991 const struct qmp_phy_cfg *cfg = qphy->cfg; 1992 1993 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1994 1995 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1996 1997 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1998 1999 return 0; 2000 } 2001 2002 static int qcom_qmp_phy_pcie_init(struct phy *phy) 2003 { 2004 struct qmp_phy *qphy = phy_get_drvdata(phy); 2005 struct qcom_qmp *qmp = qphy->qmp; 2006 int ret; 2007 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 2008 2009 ret = qcom_qmp_phy_pcie_com_init(qphy); 2010 if (ret) 2011 return ret; 2012 2013 return 0; 2014 } 2015 2016 static int qcom_qmp_phy_pcie_power_on(struct phy *phy) 2017 { 2018 struct qmp_phy *qphy = phy_get_drvdata(phy); 2019 struct qcom_qmp *qmp = qphy->qmp; 2020 const struct qmp_phy_cfg *cfg = qphy->cfg; 2021 void __iomem *tx = qphy->tx; 2022 void __iomem *rx = qphy->rx; 2023 void __iomem *pcs = qphy->pcs; 2024 void __iomem *pcs_misc = qphy->pcs_misc; 2025 void __iomem *status; 2026 unsigned int mask, val, ready; 2027 int ret; 2028 2029 qcom_qmp_phy_pcie_serdes_init(qphy); 2030 2031 ret = clk_prepare_enable(qphy->pipe_clk); 2032 if (ret) { 2033 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2034 return ret; 2035 } 2036 2037 /* Tx, Rx, and PCS configurations */ 2038 qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, 2039 cfg->tx_tbl, cfg->tx_tbl_num, 1); 2040 if (cfg->tx_tbl_sec) 2041 qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 2042 cfg->tx_tbl_num_sec, 1); 2043 2044 /* Configuration for other LANE for USB-DP combo PHY */ 2045 if (cfg->is_dual_lane_phy) { 2046 qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, 2047 cfg->tx_tbl, cfg->tx_tbl_num, 2); 2048 if (cfg->tx_tbl_sec) 2049 qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, 2050 cfg->tx_tbl_sec, 2051 cfg->tx_tbl_num_sec, 2); 2052 } 2053 2054 qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, 2055 cfg->rx_tbl, cfg->rx_tbl_num, 1); 2056 if (cfg->rx_tbl_sec) 2057 qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, 2058 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 2059 2060 if (cfg->is_dual_lane_phy) { 2061 qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, 2062 cfg->rx_tbl, cfg->rx_tbl_num, 2); 2063 if (cfg->rx_tbl_sec) 2064 qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, 2065 cfg->rx_tbl_sec, 2066 cfg->rx_tbl_num_sec, 2); 2067 } 2068 2069 qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2070 if (cfg->pcs_tbl_sec) 2071 qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 2072 cfg->pcs_tbl_num_sec); 2073 2074 qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 2075 cfg->pcs_misc_tbl_num); 2076 if (cfg->pcs_misc_tbl_sec) 2077 qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 2078 cfg->pcs_misc_tbl_num_sec); 2079 2080 /* 2081 * Pull out PHY from POWER DOWN state. 2082 * This is active low enable signal to power-down PHY. 2083 */ 2084 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 2085 2086 if (cfg->has_pwrdn_delay) 2087 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2088 2089 /* Pull PHY out of reset state */ 2090 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2091 2092 /* start SerDes and Phy-Coding-Sublayer */ 2093 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2094 2095 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2096 mask = cfg->phy_status; 2097 ready = 0; 2098 2099 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2100 PHY_INIT_COMPLETE_TIMEOUT); 2101 if (ret) { 2102 dev_err(qmp->dev, "phy initialization timed-out\n"); 2103 goto err_disable_pipe_clk; 2104 } 2105 2106 return 0; 2107 2108 err_disable_pipe_clk: 2109 clk_disable_unprepare(qphy->pipe_clk); 2110 2111 return ret; 2112 } 2113 2114 static int qcom_qmp_phy_pcie_power_off(struct phy *phy) 2115 { 2116 struct qmp_phy *qphy = phy_get_drvdata(phy); 2117 const struct qmp_phy_cfg *cfg = qphy->cfg; 2118 2119 clk_disable_unprepare(qphy->pipe_clk); 2120 2121 /* PHY reset */ 2122 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2123 2124 /* stop SerDes and Phy-Coding-Sublayer */ 2125 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2126 2127 /* Put PHY into POWER DOWN state: active low */ 2128 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2129 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2130 cfg->pwrdn_ctrl); 2131 } else { 2132 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2133 cfg->pwrdn_ctrl); 2134 } 2135 2136 return 0; 2137 } 2138 2139 static int qcom_qmp_phy_pcie_exit(struct phy *phy) 2140 { 2141 struct qmp_phy *qphy = phy_get_drvdata(phy); 2142 2143 qcom_qmp_phy_pcie_com_exit(qphy); 2144 2145 return 0; 2146 } 2147 2148 static int qcom_qmp_phy_pcie_enable(struct phy *phy) 2149 { 2150 int ret; 2151 2152 ret = qcom_qmp_phy_pcie_init(phy); 2153 if (ret) 2154 return ret; 2155 2156 ret = qcom_qmp_phy_pcie_power_on(phy); 2157 if (ret) 2158 qcom_qmp_phy_pcie_exit(phy); 2159 2160 return ret; 2161 } 2162 2163 static int qcom_qmp_phy_pcie_disable(struct phy *phy) 2164 { 2165 int ret; 2166 2167 ret = qcom_qmp_phy_pcie_power_off(phy); 2168 if (ret) 2169 return ret; 2170 return qcom_qmp_phy_pcie_exit(phy); 2171 } 2172 2173 static int qcom_qmp_phy_pcie_set_mode(struct phy *phy, 2174 enum phy_mode mode, int submode) 2175 { 2176 struct qmp_phy *qphy = phy_get_drvdata(phy); 2177 2178 qphy->mode = mode; 2179 2180 return 0; 2181 } 2182 2183 static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2184 { 2185 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2186 int num = cfg->num_vregs; 2187 int i; 2188 2189 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2190 if (!qmp->vregs) 2191 return -ENOMEM; 2192 2193 for (i = 0; i < num; i++) 2194 qmp->vregs[i].supply = cfg->vreg_list[i]; 2195 2196 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2197 } 2198 2199 static int qcom_qmp_phy_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2200 { 2201 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2202 int i; 2203 int ret; 2204 2205 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2206 sizeof(*qmp->resets), GFP_KERNEL); 2207 if (!qmp->resets) 2208 return -ENOMEM; 2209 2210 for (i = 0; i < cfg->num_resets; i++) 2211 qmp->resets[i].id = cfg->reset_list[i]; 2212 2213 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2214 if (ret) 2215 return dev_err_probe(dev, ret, "failed to get resets\n"); 2216 2217 return 0; 2218 } 2219 2220 static int qcom_qmp_phy_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2221 { 2222 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2223 int num = cfg->num_clks; 2224 int i; 2225 2226 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2227 if (!qmp->clks) 2228 return -ENOMEM; 2229 2230 for (i = 0; i < num; i++) 2231 qmp->clks[i].id = cfg->clk_list[i]; 2232 2233 return devm_clk_bulk_get(dev, num, qmp->clks); 2234 } 2235 2236 static void phy_clk_release_provider(void *res) 2237 { 2238 of_clk_del_provider(res); 2239 } 2240 2241 /* 2242 * Register a fixed rate pipe clock. 2243 * 2244 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2245 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2246 * by the PHY driver for its operations. 2247 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2248 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2249 * Below picture shows this relationship. 2250 * 2251 * +---------------+ 2252 * | PHY block |<<---------------------------------------+ 2253 * | | | 2254 * | +-------+ | +-----+ | 2255 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2256 * clk | +-------+ | +-----+ 2257 * +---------------+ 2258 */ 2259 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2260 { 2261 struct clk_fixed_rate *fixed; 2262 struct clk_init_data init = { }; 2263 int ret; 2264 2265 ret = of_property_read_string(np, "clock-output-names", &init.name); 2266 if (ret) { 2267 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2268 return ret; 2269 } 2270 2271 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2272 if (!fixed) 2273 return -ENOMEM; 2274 2275 init.ops = &clk_fixed_rate_ops; 2276 2277 /* 2278 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2279 * unless other frequency is specified in the PHY config. 2280 */ 2281 if (qmp->phys[0]->cfg->pipe_clock_rate) 2282 fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2283 else 2284 fixed->fixed_rate = 125000000; 2285 2286 fixed->hw.init = &init; 2287 2288 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2289 if (ret) 2290 return ret; 2291 2292 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2293 if (ret) 2294 return ret; 2295 2296 /* 2297 * Roll a devm action because the clock provider is the child node, but 2298 * the child node is not actually a device. 2299 */ 2300 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2301 } 2302 2303 static const struct phy_ops qcom_qmp_phy_pcie_ops = { 2304 .power_on = qcom_qmp_phy_pcie_enable, 2305 .power_off = qcom_qmp_phy_pcie_disable, 2306 .set_mode = qcom_qmp_phy_pcie_set_mode, 2307 .owner = THIS_MODULE, 2308 }; 2309 2310 static 2311 int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, 2312 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2313 { 2314 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2315 struct phy *generic_phy; 2316 struct qmp_phy *qphy; 2317 char prop_name[MAX_PROP_NAME]; 2318 int ret; 2319 2320 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2321 if (!qphy) 2322 return -ENOMEM; 2323 2324 qphy->cfg = cfg; 2325 qphy->serdes = serdes; 2326 /* 2327 * Get memory resources for each phy lane: 2328 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2329 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2330 * For single lane PHYs: pcs_misc (optional) -> 3. 2331 */ 2332 qphy->tx = of_iomap(np, 0); 2333 if (!qphy->tx) 2334 return -ENOMEM; 2335 2336 qphy->rx = of_iomap(np, 1); 2337 if (!qphy->rx) 2338 return -ENOMEM; 2339 2340 qphy->pcs = of_iomap(np, 2); 2341 if (!qphy->pcs) 2342 return -ENOMEM; 2343 2344 /* 2345 * If this is a dual-lane PHY, then there should be registers for the 2346 * second lane. Some old device trees did not specify this, so fall 2347 * back to old legacy behavior of assuming they can be reached at an 2348 * offset from the first lane. 2349 */ 2350 if (cfg->is_dual_lane_phy) { 2351 qphy->tx2 = of_iomap(np, 3); 2352 qphy->rx2 = of_iomap(np, 4); 2353 if (!qphy->tx2 || !qphy->rx2) { 2354 dev_warn(dev, 2355 "Underspecified device tree, falling back to legacy register regions\n"); 2356 2357 /* In the old version, pcs_misc is at index 3. */ 2358 qphy->pcs_misc = qphy->tx2; 2359 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; 2360 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; 2361 2362 } else { 2363 qphy->pcs_misc = of_iomap(np, 5); 2364 } 2365 2366 } else { 2367 qphy->pcs_misc = of_iomap(np, 3); 2368 } 2369 2370 if (!qphy->pcs_misc && 2371 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2372 qphy->pcs_misc = qphy->pcs + 0x400; 2373 2374 if (!qphy->pcs_misc) 2375 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2376 2377 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 2378 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 2379 if (IS_ERR(qphy->pipe_clk)) { 2380 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2381 "failed to get lane%d pipe clock\n", id); 2382 } 2383 2384 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); 2385 if (IS_ERR(generic_phy)) { 2386 ret = PTR_ERR(generic_phy); 2387 dev_err(dev, "failed to create qphy %d\n", ret); 2388 return ret; 2389 } 2390 2391 qphy->phy = generic_phy; 2392 qphy->index = id; 2393 qphy->qmp = qmp; 2394 qmp->phys[id] = qphy; 2395 phy_set_drvdata(generic_phy, qphy); 2396 2397 return 0; 2398 } 2399 2400 static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { 2401 { 2402 .compatible = "qcom,msm8998-qmp-pcie-phy", 2403 .data = &msm8998_pciephy_cfg, 2404 }, { 2405 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2406 .data = &ipq8074_pciephy_cfg, 2407 }, { 2408 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2409 .data = &ipq8074_pciephy_gen3_cfg, 2410 }, { 2411 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2412 .data = &ipq6018_pciephy_cfg, 2413 }, { 2414 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2415 .data = &sc8180x_pciephy_cfg, 2416 }, { 2417 .compatible = "qcom,sdm845-qhp-pcie-phy", 2418 .data = &sdm845_qhp_pciephy_cfg, 2419 }, { 2420 .compatible = "qcom,sdm845-qmp-pcie-phy", 2421 .data = &sdm845_qmp_pciephy_cfg, 2422 }, { 2423 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2424 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2425 }, { 2426 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2427 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2428 }, { 2429 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2430 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2431 }, { 2432 .compatible = "qcom,sdx55-qmp-pcie-phy", 2433 .data = &sdx55_qmp_pciephy_cfg, 2434 }, { 2435 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2436 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2437 }, { 2438 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2439 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2440 }, 2441 { }, 2442 }; 2443 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_of_match_table); 2444 2445 static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) 2446 { 2447 struct qcom_qmp *qmp; 2448 struct device *dev = &pdev->dev; 2449 struct device_node *child; 2450 struct phy_provider *phy_provider; 2451 void __iomem *serdes; 2452 const struct qmp_phy_cfg *cfg = NULL; 2453 int num, id; 2454 int ret; 2455 2456 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2457 if (!qmp) 2458 return -ENOMEM; 2459 2460 qmp->dev = dev; 2461 dev_set_drvdata(dev, qmp); 2462 2463 /* Get the specific init parameters of QMP phy */ 2464 cfg = of_device_get_match_data(dev); 2465 if (!cfg) 2466 return -EINVAL; 2467 2468 /* per PHY serdes; usually located at base address */ 2469 serdes = devm_platform_ioremap_resource(pdev, 0); 2470 if (IS_ERR(serdes)) 2471 return PTR_ERR(serdes); 2472 2473 ret = qcom_qmp_phy_pcie_clk_init(dev, cfg); 2474 if (ret) 2475 return ret; 2476 2477 ret = qcom_qmp_phy_pcie_reset_init(dev, cfg); 2478 if (ret) 2479 return ret; 2480 2481 ret = qcom_qmp_phy_pcie_vreg_init(dev, cfg); 2482 if (ret) { 2483 if (ret != -EPROBE_DEFER) 2484 dev_err(dev, "failed to get regulator supplies: %d\n", 2485 ret); 2486 return ret; 2487 } 2488 2489 num = of_get_available_child_count(dev->of_node); 2490 /* do we have a rogue child node ? */ 2491 if (num > 1) 2492 return -EINVAL; 2493 2494 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2495 if (!qmp->phys) 2496 return -ENOMEM; 2497 2498 pm_runtime_set_active(dev); 2499 pm_runtime_enable(dev); 2500 /* 2501 * Prevent runtime pm from being ON by default. Users can enable 2502 * it using power/control in sysfs. 2503 */ 2504 pm_runtime_forbid(dev); 2505 2506 id = 0; 2507 for_each_available_child_of_node(dev->of_node, child) { 2508 /* Create per-lane phy */ 2509 ret = qcom_qmp_phy_pcie_create(dev, child, id, serdes, cfg); 2510 if (ret) { 2511 dev_err(dev, "failed to create lane%d phy, %d\n", 2512 id, ret); 2513 goto err_node_put; 2514 } 2515 2516 /* 2517 * Register the pipe clock provided by phy. 2518 * See function description to see details of this pipe clock. 2519 */ 2520 ret = phy_pipe_clk_register(qmp, child); 2521 if (ret) { 2522 dev_err(qmp->dev, 2523 "failed to register pipe clock source\n"); 2524 goto err_node_put; 2525 } 2526 2527 id++; 2528 } 2529 2530 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2531 if (!IS_ERR(phy_provider)) 2532 dev_info(dev, "Registered Qcom-QMP phy\n"); 2533 else 2534 pm_runtime_disable(dev); 2535 2536 return PTR_ERR_OR_ZERO(phy_provider); 2537 2538 err_node_put: 2539 pm_runtime_disable(dev); 2540 of_node_put(child); 2541 return ret; 2542 } 2543 2544 static struct platform_driver qcom_qmp_phy_pcie_driver = { 2545 .probe = qcom_qmp_phy_pcie_probe, 2546 .driver = { 2547 .name = "qcom-qmp-pcie-phy", 2548 .of_match_table = qcom_qmp_phy_pcie_of_match_table, 2549 }, 2550 }; 2551 2552 module_platform_driver(qcom_qmp_phy_pcie_driver); 2553 2554 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2555 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2556 MODULE_LICENSE("GPL v2"); 2557