1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include "phy-qcom-qmp.h" 24 25 /* QPHY_SW_RESET bit */ 26 #define SW_RESET BIT(0) 27 /* QPHY_POWER_DOWN_CONTROL */ 28 #define SW_PWRDN BIT(0) 29 #define REFCLK_DRV_DSBL BIT(1) 30 /* QPHY_START_CONTROL bits */ 31 #define SERDES_START BIT(0) 32 #define PCS_START BIT(1) 33 #define PLL_READY_GATE_EN BIT(3) 34 /* QPHY_PCS_STATUS bit */ 35 #define PHYSTATUS BIT(6) 36 /* QPHY_COM_PCS_READY_STATUS bit */ 37 #define PCS_READY BIT(0) 38 39 #define PHY_INIT_COMPLETE_TIMEOUT 10000 40 #define POWER_DOWN_DELAY_US_MIN 10 41 #define POWER_DOWN_DELAY_US_MAX 20 42 43 struct qmp_phy_init_tbl { 44 unsigned int offset; 45 unsigned int val; 46 /* 47 * mask of lanes for which this register is written 48 * for cases when second lane needs different values 49 */ 50 u8 lane_mask; 51 }; 52 53 #define QMP_PHY_INIT_CFG(o, v) \ 54 { \ 55 .offset = o, \ 56 .val = v, \ 57 .lane_mask = 0xff, \ 58 } 59 60 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 61 { \ 62 .offset = o, \ 63 .val = v, \ 64 .lane_mask = l, \ 65 } 66 67 /* set of registers with offsets different per-PHY */ 68 enum qphy_reg_layout { 69 /* Common block control registers */ 70 QPHY_COM_SW_RESET, 71 QPHY_COM_POWER_DOWN_CONTROL, 72 QPHY_COM_START_CONTROL, 73 QPHY_COM_PCS_READY_STATUS, 74 /* PCS registers */ 75 QPHY_SW_RESET, 76 QPHY_START_CTRL, 77 QPHY_PCS_STATUS, 78 /* Keep last to ensure regs_layout arrays are properly initialized */ 79 QPHY_LAYOUT_SIZE 80 }; 81 82 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 83 [QPHY_COM_SW_RESET] = 0x400, 84 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 85 [QPHY_COM_START_CONTROL] = 0x408, 86 [QPHY_COM_PCS_READY_STATUS] = 0x448, 87 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 88 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 89 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 90 }; 91 92 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { 93 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 94 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 95 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 96 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 97 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), 98 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 99 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 100 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 101 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), 102 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 103 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 104 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 105 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), 106 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 107 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 108 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 109 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 110 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 111 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), 112 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), 113 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 114 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 115 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 116 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), 117 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 118 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 119 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 120 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 121 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 122 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 123 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 124 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 125 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), 126 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 127 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 128 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 129 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), 130 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 131 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 132 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 133 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 134 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 135 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), 136 }; 137 138 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { 139 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 140 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 141 }; 142 143 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { 144 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 145 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), 146 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), 147 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 148 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), 149 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 150 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), 151 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 152 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 153 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), 154 }; 155 156 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 157 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c), 158 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), 159 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 160 161 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05), 162 163 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05), 164 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02), 165 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00), 166 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3), 167 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 168 }; 169 170 /* struct qmp_phy_cfg - per-PHY initialization config */ 171 struct qmp_phy_cfg { 172 /* number of PHYs provided by this block */ 173 int num_phys; 174 175 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 176 const struct qmp_phy_init_tbl *serdes_tbl; 177 int serdes_tbl_num; 178 const struct qmp_phy_init_tbl *tx_tbl; 179 int tx_tbl_num; 180 const struct qmp_phy_init_tbl *rx_tbl; 181 int rx_tbl_num; 182 const struct qmp_phy_init_tbl *pcs_tbl; 183 int pcs_tbl_num; 184 185 /* clock ids to be requested */ 186 const char * const *clk_list; 187 int num_clks; 188 /* resets to be requested */ 189 const char * const *reset_list; 190 int num_resets; 191 /* regulators to be requested */ 192 const char * const *vreg_list; 193 int num_vregs; 194 195 /* array of registers with different offsets */ 196 const unsigned int *regs; 197 }; 198 199 /** 200 * struct qmp_phy - per-lane phy descriptor 201 * 202 * @phy: generic phy 203 * @cfg: phy specific configuration 204 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 205 * @tx: iomapped memory space for lane's tx 206 * @rx: iomapped memory space for lane's rx 207 * @pcs: iomapped memory space for lane's pcs 208 * @pipe_clk: pipe clock 209 * @index: lane index 210 * @qmp: QMP phy to which this lane belongs 211 * @lane_rst: lane's reset controller 212 */ 213 struct qmp_phy { 214 struct phy *phy; 215 const struct qmp_phy_cfg *cfg; 216 void __iomem *serdes; 217 void __iomem *tx; 218 void __iomem *rx; 219 void __iomem *pcs; 220 struct clk *pipe_clk; 221 unsigned int index; 222 struct qcom_qmp *qmp; 223 struct reset_control *lane_rst; 224 }; 225 226 /** 227 * struct qcom_qmp - structure holding QMP phy block attributes 228 * 229 * @dev: device 230 * 231 * @clks: array of clocks required by phy 232 * @resets: array of resets required by phy 233 * @vregs: regulator supplies bulk data 234 * 235 * @phys: array of per-lane phy descriptors 236 * @phy_mutex: mutex lock for PHY common block initialization 237 * @init_count: phy common block initialization count 238 */ 239 struct qcom_qmp { 240 struct device *dev; 241 242 struct clk_bulk_data *clks; 243 struct reset_control_bulk_data *resets; 244 struct regulator_bulk_data *vregs; 245 246 struct qmp_phy **phys; 247 248 struct mutex phy_mutex; 249 int init_count; 250 }; 251 252 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 253 { 254 u32 reg; 255 256 reg = readl(base + offset); 257 reg |= val; 258 writel(reg, base + offset); 259 260 /* ensure that above write is through */ 261 readl(base + offset); 262 } 263 264 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 265 { 266 u32 reg; 267 268 reg = readl(base + offset); 269 reg &= ~val; 270 writel(reg, base + offset); 271 272 /* ensure that above write is through */ 273 readl(base + offset); 274 } 275 276 /* list of clocks required by phy */ 277 static const char * const msm8996_phy_clk_l[] = { 278 "aux", "cfg_ahb", "ref", 279 }; 280 281 /* list of resets */ 282 static const char * const msm8996_pciephy_reset_l[] = { 283 "phy", "common", "cfg", 284 }; 285 286 /* list of regulators */ 287 static const char * const qmp_phy_vreg_l[] = { 288 "vdda-phy", "vdda-pll", 289 }; 290 291 static const struct qmp_phy_cfg msm8996_pciephy_cfg = { 292 .num_phys = 3, 293 294 .serdes_tbl = msm8996_pcie_serdes_tbl, 295 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), 296 .tx_tbl = msm8996_pcie_tx_tbl, 297 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), 298 .rx_tbl = msm8996_pcie_rx_tbl, 299 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), 300 .pcs_tbl = msm8996_pcie_pcs_tbl, 301 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), 302 .clk_list = msm8996_phy_clk_l, 303 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 304 .reset_list = msm8996_pciephy_reset_l, 305 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), 306 .vreg_list = qmp_phy_vreg_l, 307 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 308 .regs = pciephy_regs_layout, 309 }; 310 311 static void qmp_pcie_msm8996_configure_lane(void __iomem *base, 312 const struct qmp_phy_init_tbl tbl[], 313 int num, 314 u8 lane_mask) 315 { 316 int i; 317 const struct qmp_phy_init_tbl *t = tbl; 318 319 if (!t) 320 return; 321 322 for (i = 0; i < num; i++, t++) { 323 if (!(t->lane_mask & lane_mask)) 324 continue; 325 326 writel(t->val, base + t->offset); 327 } 328 } 329 330 static void qmp_pcie_msm8996_configure(void __iomem *base, 331 const struct qmp_phy_init_tbl tbl[], 332 int num) 333 { 334 qmp_pcie_msm8996_configure_lane(base, tbl, num, 0xff); 335 } 336 337 static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy) 338 { 339 struct qcom_qmp *qmp = qphy->qmp; 340 const struct qmp_phy_cfg *cfg = qphy->cfg; 341 void __iomem *serdes = qphy->serdes; 342 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 343 int serdes_tbl_num = cfg->serdes_tbl_num; 344 void __iomem *status; 345 unsigned int val; 346 int ret; 347 348 qmp_pcie_msm8996_configure(serdes, serdes_tbl, serdes_tbl_num); 349 350 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 351 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 352 SERDES_START | PCS_START); 353 354 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 355 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 356 PHY_INIT_COMPLETE_TIMEOUT); 357 if (ret) { 358 dev_err(qmp->dev, 359 "phy common block init timed-out\n"); 360 return ret; 361 } 362 363 return 0; 364 } 365 366 static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy) 367 { 368 struct qcom_qmp *qmp = qphy->qmp; 369 const struct qmp_phy_cfg *cfg = qphy->cfg; 370 void __iomem *serdes = qphy->serdes; 371 int ret; 372 373 mutex_lock(&qmp->phy_mutex); 374 if (qmp->init_count++) { 375 mutex_unlock(&qmp->phy_mutex); 376 return 0; 377 } 378 379 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 380 if (ret) { 381 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 382 goto err_unlock; 383 } 384 385 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 386 if (ret) { 387 dev_err(qmp->dev, "reset assert failed\n"); 388 goto err_disable_regulators; 389 } 390 391 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 392 if (ret) { 393 dev_err(qmp->dev, "reset deassert failed\n"); 394 goto err_disable_regulators; 395 } 396 397 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 398 if (ret) 399 goto err_assert_reset; 400 401 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 402 SW_PWRDN); 403 404 mutex_unlock(&qmp->phy_mutex); 405 406 return 0; 407 408 err_assert_reset: 409 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 410 err_disable_regulators: 411 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 412 err_unlock: 413 mutex_unlock(&qmp->phy_mutex); 414 415 return ret; 416 } 417 418 static int qmp_pcie_msm8996_com_exit(struct qmp_phy *qphy) 419 { 420 struct qcom_qmp *qmp = qphy->qmp; 421 const struct qmp_phy_cfg *cfg = qphy->cfg; 422 void __iomem *serdes = qphy->serdes; 423 424 mutex_lock(&qmp->phy_mutex); 425 if (--qmp->init_count) { 426 mutex_unlock(&qmp->phy_mutex); 427 return 0; 428 } 429 430 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 431 SERDES_START | PCS_START); 432 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 433 SW_RESET); 434 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 435 SW_PWRDN); 436 437 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 438 439 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 440 441 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 442 443 mutex_unlock(&qmp->phy_mutex); 444 445 return 0; 446 } 447 448 static int qmp_pcie_msm8996_init(struct phy *phy) 449 { 450 struct qmp_phy *qphy = phy_get_drvdata(phy); 451 struct qcom_qmp *qmp = qphy->qmp; 452 int ret; 453 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 454 455 ret = qmp_pcie_msm8996_com_init(qphy); 456 if (ret) 457 return ret; 458 459 return 0; 460 } 461 462 static int qmp_pcie_msm8996_power_on(struct phy *phy) 463 { 464 struct qmp_phy *qphy = phy_get_drvdata(phy); 465 struct qcom_qmp *qmp = qphy->qmp; 466 const struct qmp_phy_cfg *cfg = qphy->cfg; 467 void __iomem *tx = qphy->tx; 468 void __iomem *rx = qphy->rx; 469 void __iomem *pcs = qphy->pcs; 470 void __iomem *status; 471 unsigned int val; 472 int ret; 473 474 qmp_pcie_msm8996_serdes_init(qphy); 475 476 ret = reset_control_deassert(qphy->lane_rst); 477 if (ret) { 478 dev_err(qmp->dev, "lane%d reset deassert failed\n", 479 qphy->index); 480 return ret; 481 } 482 483 ret = clk_prepare_enable(qphy->pipe_clk); 484 if (ret) { 485 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 486 goto err_reset_lane; 487 } 488 489 /* Tx, Rx, and PCS configurations */ 490 qmp_pcie_msm8996_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 491 qmp_pcie_msm8996_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 492 qmp_pcie_msm8996_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 493 494 /* 495 * Pull out PHY from POWER DOWN state. 496 * This is active low enable signal to power-down PHY. 497 */ 498 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 499 SW_PWRDN | REFCLK_DRV_DSBL); 500 501 usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX); 502 503 /* Pull PHY out of reset state */ 504 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 505 506 /* start SerDes and Phy-Coding-Sublayer */ 507 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], 508 PCS_START | PLL_READY_GATE_EN); 509 510 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 511 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 512 PHY_INIT_COMPLETE_TIMEOUT); 513 if (ret) { 514 dev_err(qmp->dev, "phy initialization timed-out\n"); 515 goto err_disable_pipe_clk; 516 } 517 518 return 0; 519 520 err_disable_pipe_clk: 521 clk_disable_unprepare(qphy->pipe_clk); 522 err_reset_lane: 523 reset_control_assert(qphy->lane_rst); 524 525 return ret; 526 } 527 528 static int qmp_pcie_msm8996_power_off(struct phy *phy) 529 { 530 struct qmp_phy *qphy = phy_get_drvdata(phy); 531 const struct qmp_phy_cfg *cfg = qphy->cfg; 532 533 clk_disable_unprepare(qphy->pipe_clk); 534 535 /* PHY reset */ 536 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 537 538 /* stop SerDes and Phy-Coding-Sublayer */ 539 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], 540 SERDES_START | PCS_START); 541 542 /* Put PHY into POWER DOWN state: active low */ 543 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 544 SW_PWRDN | REFCLK_DRV_DSBL); 545 546 return 0; 547 } 548 549 static int qmp_pcie_msm8996_exit(struct phy *phy) 550 { 551 struct qmp_phy *qphy = phy_get_drvdata(phy); 552 553 reset_control_assert(qphy->lane_rst); 554 555 qmp_pcie_msm8996_com_exit(qphy); 556 557 return 0; 558 } 559 560 static int qmp_pcie_msm8996_enable(struct phy *phy) 561 { 562 int ret; 563 564 ret = qmp_pcie_msm8996_init(phy); 565 if (ret) 566 return ret; 567 568 ret = qmp_pcie_msm8996_power_on(phy); 569 if (ret) 570 qmp_pcie_msm8996_exit(phy); 571 572 return ret; 573 } 574 575 static int qmp_pcie_msm8996_disable(struct phy *phy) 576 { 577 int ret; 578 579 ret = qmp_pcie_msm8996_power_off(phy); 580 if (ret) 581 return ret; 582 return qmp_pcie_msm8996_exit(phy); 583 } 584 585 static int qmp_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 586 { 587 struct qcom_qmp *qmp = dev_get_drvdata(dev); 588 int num = cfg->num_vregs; 589 int i; 590 591 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 592 if (!qmp->vregs) 593 return -ENOMEM; 594 595 for (i = 0; i < num; i++) 596 qmp->vregs[i].supply = cfg->vreg_list[i]; 597 598 return devm_regulator_bulk_get(dev, num, qmp->vregs); 599 } 600 601 static int qmp_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 602 { 603 struct qcom_qmp *qmp = dev_get_drvdata(dev); 604 int i; 605 int ret; 606 607 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 608 sizeof(*qmp->resets), GFP_KERNEL); 609 if (!qmp->resets) 610 return -ENOMEM; 611 612 for (i = 0; i < cfg->num_resets; i++) 613 qmp->resets[i].id = cfg->reset_list[i]; 614 615 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 616 if (ret) 617 return dev_err_probe(dev, ret, "failed to get resets\n"); 618 619 return 0; 620 } 621 622 static int qmp_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 623 { 624 struct qcom_qmp *qmp = dev_get_drvdata(dev); 625 int num = cfg->num_clks; 626 int i; 627 628 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 629 if (!qmp->clks) 630 return -ENOMEM; 631 632 for (i = 0; i < num; i++) 633 qmp->clks[i].id = cfg->clk_list[i]; 634 635 return devm_clk_bulk_get(dev, num, qmp->clks); 636 } 637 638 static void phy_clk_release_provider(void *res) 639 { 640 of_clk_del_provider(res); 641 } 642 643 /* 644 * Register a fixed rate pipe clock. 645 * 646 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 647 * controls it. The <s>_pipe_clk coming out of the GCC is requested 648 * by the PHY driver for its operations. 649 * We register the <s>_pipe_clksrc here. The gcc driver takes care 650 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 651 * Below picture shows this relationship. 652 * 653 * +---------------+ 654 * | PHY block |<<---------------------------------------+ 655 * | | | 656 * | +-------+ | +-----+ | 657 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 658 * clk | +-------+ | +-----+ 659 * +---------------+ 660 */ 661 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 662 { 663 struct clk_fixed_rate *fixed; 664 struct clk_init_data init = { }; 665 int ret; 666 667 ret = of_property_read_string(np, "clock-output-names", &init.name); 668 if (ret) { 669 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 670 return ret; 671 } 672 673 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 674 if (!fixed) 675 return -ENOMEM; 676 677 init.ops = &clk_fixed_rate_ops; 678 679 /* controllers using QMP phys use 125MHz pipe clock interface */ 680 fixed->fixed_rate = 125000000; 681 fixed->hw.init = &init; 682 683 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 684 if (ret) 685 return ret; 686 687 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 688 if (ret) 689 return ret; 690 691 /* 692 * Roll a devm action because the clock provider is the child node, but 693 * the child node is not actually a device. 694 */ 695 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 696 } 697 698 static const struct phy_ops qmp_pcie_msm8996_ops = { 699 .power_on = qmp_pcie_msm8996_enable, 700 .power_off = qmp_pcie_msm8996_disable, 701 .owner = THIS_MODULE, 702 }; 703 704 static void qcom_qmp_reset_control_put(void *data) 705 { 706 reset_control_put(data); 707 } 708 709 static int qmp_pcie_msm8996_create(struct device *dev, struct device_node *np, int id, 710 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 711 { 712 struct qcom_qmp *qmp = dev_get_drvdata(dev); 713 struct phy *generic_phy; 714 struct qmp_phy *qphy; 715 int ret; 716 717 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 718 if (!qphy) 719 return -ENOMEM; 720 721 qphy->cfg = cfg; 722 qphy->serdes = serdes; 723 /* 724 * Get memory resources for each PHY: 725 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 726 */ 727 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 728 if (IS_ERR(qphy->tx)) 729 return PTR_ERR(qphy->tx); 730 731 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 732 if (IS_ERR(qphy->rx)) 733 return PTR_ERR(qphy->rx); 734 735 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 736 if (IS_ERR(qphy->pcs)) 737 return PTR_ERR(qphy->pcs); 738 739 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 740 if (IS_ERR(qphy->pipe_clk)) { 741 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 742 "failed to get lane%d pipe clock\n", id); 743 } 744 745 qphy->lane_rst = of_reset_control_get_exclusive_by_index(np, 0); 746 if (IS_ERR(qphy->lane_rst)) { 747 dev_err(dev, "failed to get lane%d reset\n", id); 748 return PTR_ERR(qphy->lane_rst); 749 } 750 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 751 qphy->lane_rst); 752 if (ret) 753 return ret; 754 755 generic_phy = devm_phy_create(dev, np, &qmp_pcie_msm8996_ops); 756 if (IS_ERR(generic_phy)) { 757 ret = PTR_ERR(generic_phy); 758 dev_err(dev, "failed to create qphy %d\n", ret); 759 return ret; 760 } 761 762 qphy->phy = generic_phy; 763 qphy->index = id; 764 qphy->qmp = qmp; 765 qmp->phys[id] = qphy; 766 phy_set_drvdata(generic_phy, qphy); 767 768 return 0; 769 } 770 771 static const struct of_device_id qmp_pcie_msm8996_of_match_table[] = { 772 { 773 .compatible = "qcom,msm8996-qmp-pcie-phy", 774 .data = &msm8996_pciephy_cfg, 775 }, 776 { }, 777 }; 778 MODULE_DEVICE_TABLE(of, qmp_pcie_msm8996_of_match_table); 779 780 static int qmp_pcie_msm8996_probe(struct platform_device *pdev) 781 { 782 struct qcom_qmp *qmp; 783 struct device *dev = &pdev->dev; 784 struct device_node *child; 785 struct phy_provider *phy_provider; 786 void __iomem *serdes; 787 const struct qmp_phy_cfg *cfg = NULL; 788 int num, id, expected_phys; 789 int ret; 790 791 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 792 if (!qmp) 793 return -ENOMEM; 794 795 qmp->dev = dev; 796 dev_set_drvdata(dev, qmp); 797 798 cfg = of_device_get_match_data(dev); 799 if (!cfg) 800 return -EINVAL; 801 802 serdes = devm_platform_ioremap_resource(pdev, 0); 803 if (IS_ERR(serdes)) 804 return PTR_ERR(serdes); 805 806 expected_phys = cfg->num_phys; 807 808 mutex_init(&qmp->phy_mutex); 809 810 ret = qmp_pcie_msm8996_clk_init(dev, cfg); 811 if (ret) 812 return ret; 813 814 ret = qmp_pcie_msm8996_reset_init(dev, cfg); 815 if (ret) 816 return ret; 817 818 ret = qmp_pcie_msm8996_vreg_init(dev, cfg); 819 if (ret) 820 return ret; 821 822 num = of_get_available_child_count(dev->of_node); 823 /* do we have a rogue child node ? */ 824 if (num > expected_phys) 825 return -EINVAL; 826 827 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 828 if (!qmp->phys) 829 return -ENOMEM; 830 831 id = 0; 832 for_each_available_child_of_node(dev->of_node, child) { 833 /* Create per-lane phy */ 834 ret = qmp_pcie_msm8996_create(dev, child, id, serdes, cfg); 835 if (ret) { 836 dev_err(dev, "failed to create lane%d phy, %d\n", 837 id, ret); 838 goto err_node_put; 839 } 840 841 /* 842 * Register the pipe clock provided by phy. 843 * See function description to see details of this pipe clock. 844 */ 845 ret = phy_pipe_clk_register(qmp, child); 846 if (ret) { 847 dev_err(qmp->dev, 848 "failed to register pipe clock source\n"); 849 goto err_node_put; 850 } 851 852 id++; 853 } 854 855 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 856 857 return PTR_ERR_OR_ZERO(phy_provider); 858 859 err_node_put: 860 of_node_put(child); 861 return ret; 862 } 863 864 static struct platform_driver qmp_pcie_msm8996_driver = { 865 .probe = qmp_pcie_msm8996_probe, 866 .driver = { 867 .name = "qcom-qmp-msm8996-pcie-phy", 868 .of_match_table = qmp_pcie_msm8996_of_match_table, 869 }, 870 }; 871 872 module_platform_driver(qmp_pcie_msm8996_driver); 873 874 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 875 MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver"); 876 MODULE_LICENSE("GPL v2"); 877