1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 #define REFCLK_DRV_DSBL BIT(1) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 #define PLL_READY_GATE_EN BIT(3) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ 40 #define PCS_READY BIT(0) 41 42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 43 /* DP PHY soft reset */ 44 #define SW_DPPHY_RESET BIT(0) 45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_DPPHY_RESET_MUX BIT(1) 47 /* USB3 PHY soft reset */ 48 #define SW_USB3PHY_RESET BIT(2) 49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 50 #define SW_USB3PHY_RESET_MUX BIT(3) 51 52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 53 #define USB3_MODE BIT(0) /* enables USB3 mode */ 54 #define DP_MODE BIT(1) /* enables DP mode */ 55 56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 57 #define ARCVR_DTCT_EN BIT(0) 58 #define ALFPS_DTCT_EN BIT(1) 59 #define ARCVR_DTCT_EVENT_SEL BIT(4) 60 61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 62 #define IRQ_CLEAR BIT(0) 63 64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 65 #define RCVR_DETECT BIT(0) 66 67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 68 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 69 70 #define PHY_INIT_COMPLETE_TIMEOUT 10000 71 #define POWER_DOWN_DELAY_US_MIN 10 72 #define POWER_DOWN_DELAY_US_MAX 11 73 74 #define MAX_PROP_NAME 32 75 76 /* Define the assumed distance between lanes for underspecified device trees. */ 77 #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 78 79 struct qmp_phy_init_tbl { 80 unsigned int offset; 81 unsigned int val; 82 /* 83 * register part of layout ? 84 * if yes, then offset gives index in the reg-layout 85 */ 86 bool in_layout; 87 /* 88 * mask of lanes for which this register is written 89 * for cases when second lane needs different values 90 */ 91 u8 lane_mask; 92 }; 93 94 #define QMP_PHY_INIT_CFG(o, v) \ 95 { \ 96 .offset = o, \ 97 .val = v, \ 98 .lane_mask = 0xff, \ 99 } 100 101 #define QMP_PHY_INIT_CFG_L(o, v) \ 102 { \ 103 .offset = o, \ 104 .val = v, \ 105 .in_layout = true, \ 106 .lane_mask = 0xff, \ 107 } 108 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 110 { \ 111 .offset = o, \ 112 .val = v, \ 113 .lane_mask = l, \ 114 } 115 116 /* set of registers with offsets different per-PHY */ 117 enum qphy_reg_layout { 118 /* Common block control registers */ 119 QPHY_COM_SW_RESET, 120 QPHY_COM_POWER_DOWN_CONTROL, 121 QPHY_COM_START_CONTROL, 122 QPHY_COM_PCS_READY_STATUS, 123 /* PCS registers */ 124 QPHY_SW_RESET, 125 QPHY_START_CTRL, 126 QPHY_PCS_READY_STATUS, 127 QPHY_PCS_STATUS, 128 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 129 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 130 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 131 QPHY_PCS_POWER_DOWN_CONTROL, 132 /* PCS_MISC registers */ 133 QPHY_PCS_MISC_TYPEC_CTRL, 134 /* Keep last to ensure regs_layout arrays are properly initialized */ 135 QPHY_LAYOUT_SIZE 136 }; 137 138 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 139 [QPHY_COM_SW_RESET] = 0x400, 140 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 141 [QPHY_COM_START_CONTROL] = 0x408, 142 [QPHY_COM_PCS_READY_STATUS] = 0x448, 143 [QPHY_SW_RESET] = 0x00, 144 [QPHY_START_CTRL] = 0x08, 145 [QPHY_PCS_STATUS] = 0x174, 146 }; 147 148 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { 149 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 150 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 151 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 152 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 153 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), 154 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 155 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 156 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 157 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), 158 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 160 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 161 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), 162 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 163 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 164 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 165 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 166 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 167 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), 168 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), 169 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 170 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 171 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 172 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), 173 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 174 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 175 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 176 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 177 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 178 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 179 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 180 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 181 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), 182 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 183 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 184 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 185 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), 186 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 187 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 188 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 189 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 190 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 191 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), 192 }; 193 194 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { 195 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 196 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 197 }; 198 199 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { 200 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 201 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), 202 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), 203 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 204 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), 205 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 206 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), 207 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 208 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 209 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), 210 }; 211 212 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 213 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c), 214 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), 215 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 216 217 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05), 218 219 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05), 220 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02), 221 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00), 222 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3), 223 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 224 }; 225 226 struct qmp_phy; 227 228 /* struct qmp_phy_cfg - per-PHY initialization config */ 229 struct qmp_phy_cfg { 230 /* phy-type - PCIE/UFS/USB */ 231 unsigned int type; 232 /* number of lanes provided by phy */ 233 int nlanes; 234 235 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 236 const struct qmp_phy_init_tbl *serdes_tbl; 237 int serdes_tbl_num; 238 const struct qmp_phy_init_tbl *serdes_tbl_sec; 239 int serdes_tbl_num_sec; 240 const struct qmp_phy_init_tbl *tx_tbl; 241 int tx_tbl_num; 242 const struct qmp_phy_init_tbl *tx_tbl_sec; 243 int tx_tbl_num_sec; 244 const struct qmp_phy_init_tbl *rx_tbl; 245 int rx_tbl_num; 246 const struct qmp_phy_init_tbl *rx_tbl_sec; 247 int rx_tbl_num_sec; 248 const struct qmp_phy_init_tbl *pcs_tbl; 249 int pcs_tbl_num; 250 const struct qmp_phy_init_tbl *pcs_tbl_sec; 251 int pcs_tbl_num_sec; 252 const struct qmp_phy_init_tbl *pcs_misc_tbl; 253 int pcs_misc_tbl_num; 254 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 255 int pcs_misc_tbl_num_sec; 256 257 /* clock ids to be requested */ 258 const char * const *clk_list; 259 int num_clks; 260 /* resets to be requested */ 261 const char * const *reset_list; 262 int num_resets; 263 /* regulators to be requested */ 264 const char * const *vreg_list; 265 int num_vregs; 266 267 /* array of registers with different offsets */ 268 const unsigned int *regs; 269 270 unsigned int start_ctrl; 271 unsigned int pwrdn_ctrl; 272 unsigned int mask_com_pcs_ready; 273 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 274 unsigned int phy_status; 275 276 /* true, if PHY needs delay after POWER_DOWN */ 277 bool has_pwrdn_delay; 278 /* power_down delay in usec */ 279 int pwrdn_delay_min; 280 int pwrdn_delay_max; 281 }; 282 283 /** 284 * struct qmp_phy - per-lane phy descriptor 285 * 286 * @phy: generic phy 287 * @cfg: phy specific configuration 288 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 289 * @tx: iomapped memory space for lane's tx 290 * @rx: iomapped memory space for lane's rx 291 * @pcs: iomapped memory space for lane's pcs 292 * @pcs_misc: iomapped memory space for lane's pcs_misc 293 * @pipe_clk: pipe clock 294 * @index: lane index 295 * @qmp: QMP phy to which this lane belongs 296 * @lane_rst: lane's reset controller 297 * @mode: current PHY mode 298 */ 299 struct qmp_phy { 300 struct phy *phy; 301 const struct qmp_phy_cfg *cfg; 302 void __iomem *serdes; 303 void __iomem *tx; 304 void __iomem *rx; 305 void __iomem *pcs; 306 void __iomem *pcs_misc; 307 struct clk *pipe_clk; 308 unsigned int index; 309 struct qcom_qmp *qmp; 310 struct reset_control *lane_rst; 311 enum phy_mode mode; 312 }; 313 314 /** 315 * struct qcom_qmp - structure holding QMP phy block attributes 316 * 317 * @dev: device 318 * 319 * @clks: array of clocks required by phy 320 * @resets: array of resets required by phy 321 * @vregs: regulator supplies bulk data 322 * 323 * @phys: array of per-lane phy descriptors 324 * @phy_mutex: mutex lock for PHY common block initialization 325 * @init_count: phy common block initialization count 326 */ 327 struct qcom_qmp { 328 struct device *dev; 329 330 struct clk_bulk_data *clks; 331 struct reset_control_bulk_data *resets; 332 struct regulator_bulk_data *vregs; 333 334 struct qmp_phy **phys; 335 336 struct mutex phy_mutex; 337 int init_count; 338 }; 339 340 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 341 { 342 u32 reg; 343 344 reg = readl(base + offset); 345 reg |= val; 346 writel(reg, base + offset); 347 348 /* ensure that above write is through */ 349 readl(base + offset); 350 } 351 352 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 353 { 354 u32 reg; 355 356 reg = readl(base + offset); 357 reg &= ~val; 358 writel(reg, base + offset); 359 360 /* ensure that above write is through */ 361 readl(base + offset); 362 } 363 364 /* list of clocks required by phy */ 365 static const char * const msm8996_phy_clk_l[] = { 366 "aux", "cfg_ahb", "ref", 367 }; 368 369 /* list of resets */ 370 static const char * const msm8996_pciephy_reset_l[] = { 371 "phy", "common", "cfg", 372 }; 373 374 /* list of regulators */ 375 static const char * const qmp_phy_vreg_l[] = { 376 "vdda-phy", "vdda-pll", 377 }; 378 379 static const struct qmp_phy_cfg msm8996_pciephy_cfg = { 380 .type = PHY_TYPE_PCIE, 381 .nlanes = 3, 382 383 .serdes_tbl = msm8996_pcie_serdes_tbl, 384 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), 385 .tx_tbl = msm8996_pcie_tx_tbl, 386 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), 387 .rx_tbl = msm8996_pcie_rx_tbl, 388 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), 389 .pcs_tbl = msm8996_pcie_pcs_tbl, 390 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), 391 .clk_list = msm8996_phy_clk_l, 392 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 393 .reset_list = msm8996_pciephy_reset_l, 394 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), 395 .vreg_list = qmp_phy_vreg_l, 396 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 397 .regs = pciephy_regs_layout, 398 399 .start_ctrl = PCS_START | PLL_READY_GATE_EN, 400 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 401 .mask_com_pcs_ready = PCS_READY, 402 .phy_status = PHYSTATUS, 403 404 .has_pwrdn_delay = true, 405 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 406 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 407 }; 408 409 static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base, 410 const unsigned int *regs, 411 const struct qmp_phy_init_tbl tbl[], 412 int num, 413 u8 lane_mask) 414 { 415 int i; 416 const struct qmp_phy_init_tbl *t = tbl; 417 418 if (!t) 419 return; 420 421 for (i = 0; i < num; i++, t++) { 422 if (!(t->lane_mask & lane_mask)) 423 continue; 424 425 if (t->in_layout) 426 writel(t->val, base + regs[t->offset]); 427 else 428 writel(t->val, base + t->offset); 429 } 430 } 431 432 static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base, 433 const unsigned int *regs, 434 const struct qmp_phy_init_tbl tbl[], 435 int num) 436 { 437 qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); 438 } 439 440 static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) 441 { 442 struct qcom_qmp *qmp = qphy->qmp; 443 const struct qmp_phy_cfg *cfg = qphy->cfg; 444 void __iomem *serdes = qphy->serdes; 445 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 446 int serdes_tbl_num = cfg->serdes_tbl_num; 447 void __iomem *status; 448 unsigned int mask, val; 449 int ret; 450 451 qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 452 if (cfg->serdes_tbl_sec) 453 qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 454 cfg->serdes_tbl_num_sec); 455 456 457 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 458 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 459 SERDES_START | PCS_START); 460 461 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 462 mask = cfg->mask_com_pcs_ready; 463 464 ret = readl_poll_timeout(status, val, (val & mask), 10, 465 PHY_INIT_COMPLETE_TIMEOUT); 466 if (ret) { 467 dev_err(qmp->dev, 468 "phy common block init timed-out\n"); 469 return ret; 470 } 471 472 return 0; 473 } 474 475 static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) 476 { 477 struct qcom_qmp *qmp = qphy->qmp; 478 const struct qmp_phy_cfg *cfg = qphy->cfg; 479 void __iomem *serdes = qphy->serdes; 480 int ret; 481 482 mutex_lock(&qmp->phy_mutex); 483 if (qmp->init_count++) { 484 mutex_unlock(&qmp->phy_mutex); 485 return 0; 486 } 487 488 /* turn on regulator supplies */ 489 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 490 if (ret) { 491 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 492 goto err_unlock; 493 } 494 495 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 496 if (ret) { 497 dev_err(qmp->dev, "reset assert failed\n"); 498 goto err_disable_regulators; 499 } 500 501 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 502 if (ret) { 503 dev_err(qmp->dev, "reset deassert failed\n"); 504 goto err_disable_regulators; 505 } 506 507 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 508 if (ret) 509 goto err_assert_reset; 510 511 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 512 SW_PWRDN); 513 514 mutex_unlock(&qmp->phy_mutex); 515 516 return 0; 517 518 err_assert_reset: 519 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 520 err_disable_regulators: 521 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 522 err_unlock: 523 mutex_unlock(&qmp->phy_mutex); 524 525 return ret; 526 } 527 528 static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) 529 { 530 struct qcom_qmp *qmp = qphy->qmp; 531 const struct qmp_phy_cfg *cfg = qphy->cfg; 532 void __iomem *serdes = qphy->serdes; 533 534 mutex_lock(&qmp->phy_mutex); 535 if (--qmp->init_count) { 536 mutex_unlock(&qmp->phy_mutex); 537 return 0; 538 } 539 540 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 541 SERDES_START | PCS_START); 542 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 543 SW_RESET); 544 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 545 SW_PWRDN); 546 547 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 548 549 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 550 551 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 552 553 mutex_unlock(&qmp->phy_mutex); 554 555 return 0; 556 } 557 558 static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) 559 { 560 struct qmp_phy *qphy = phy_get_drvdata(phy); 561 struct qcom_qmp *qmp = qphy->qmp; 562 int ret; 563 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 564 565 ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy); 566 if (ret) 567 return ret; 568 569 return 0; 570 } 571 572 static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) 573 { 574 struct qmp_phy *qphy = phy_get_drvdata(phy); 575 struct qcom_qmp *qmp = qphy->qmp; 576 const struct qmp_phy_cfg *cfg = qphy->cfg; 577 void __iomem *tx = qphy->tx; 578 void __iomem *rx = qphy->rx; 579 void __iomem *pcs = qphy->pcs; 580 void __iomem *pcs_misc = qphy->pcs_misc; 581 void __iomem *status; 582 unsigned int mask, val, ready; 583 int ret; 584 585 qcom_qmp_phy_pcie_msm8996_serdes_init(qphy); 586 587 ret = reset_control_deassert(qphy->lane_rst); 588 if (ret) { 589 dev_err(qmp->dev, "lane%d reset deassert failed\n", 590 qphy->index); 591 return ret; 592 } 593 594 ret = clk_prepare_enable(qphy->pipe_clk); 595 if (ret) { 596 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 597 goto err_reset_lane; 598 } 599 600 /* Tx, Rx, and PCS configurations */ 601 qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, 602 cfg->tx_tbl, cfg->tx_tbl_num, 1); 603 if (cfg->tx_tbl_sec) 604 qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 605 cfg->tx_tbl_num_sec, 1); 606 607 qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, 608 cfg->rx_tbl, cfg->rx_tbl_num, 1); 609 if (cfg->rx_tbl_sec) 610 qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, 611 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 612 613 qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 614 if (cfg->pcs_tbl_sec) 615 qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 616 cfg->pcs_tbl_num_sec); 617 618 qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 619 cfg->pcs_misc_tbl_num); 620 if (cfg->pcs_misc_tbl_sec) 621 qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 622 cfg->pcs_misc_tbl_num_sec); 623 624 /* 625 * Pull out PHY from POWER DOWN state. 626 * This is active low enable signal to power-down PHY. 627 */ 628 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 629 630 if (cfg->has_pwrdn_delay) 631 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 632 633 /* Pull PHY out of reset state */ 634 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 635 636 /* start SerDes and Phy-Coding-Sublayer */ 637 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 638 639 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 640 mask = cfg->phy_status; 641 ready = 0; 642 643 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 644 PHY_INIT_COMPLETE_TIMEOUT); 645 if (ret) { 646 dev_err(qmp->dev, "phy initialization timed-out\n"); 647 goto err_disable_pipe_clk; 648 } 649 650 return 0; 651 652 err_disable_pipe_clk: 653 clk_disable_unprepare(qphy->pipe_clk); 654 err_reset_lane: 655 reset_control_assert(qphy->lane_rst); 656 657 return ret; 658 } 659 660 static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) 661 { 662 struct qmp_phy *qphy = phy_get_drvdata(phy); 663 const struct qmp_phy_cfg *cfg = qphy->cfg; 664 665 clk_disable_unprepare(qphy->pipe_clk); 666 667 /* PHY reset */ 668 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 669 670 /* stop SerDes and Phy-Coding-Sublayer */ 671 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 672 673 /* Put PHY into POWER DOWN state: active low */ 674 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 675 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 676 cfg->pwrdn_ctrl); 677 } else { 678 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 679 cfg->pwrdn_ctrl); 680 } 681 682 return 0; 683 } 684 685 static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy) 686 { 687 struct qmp_phy *qphy = phy_get_drvdata(phy); 688 689 reset_control_assert(qphy->lane_rst); 690 691 qcom_qmp_phy_pcie_msm8996_com_exit(qphy); 692 693 return 0; 694 } 695 696 static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy) 697 { 698 int ret; 699 700 ret = qcom_qmp_phy_pcie_msm8996_init(phy); 701 if (ret) 702 return ret; 703 704 ret = qcom_qmp_phy_pcie_msm8996_power_on(phy); 705 if (ret) 706 qcom_qmp_phy_pcie_msm8996_exit(phy); 707 708 return ret; 709 } 710 711 static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy) 712 { 713 int ret; 714 715 ret = qcom_qmp_phy_pcie_msm8996_power_off(phy); 716 if (ret) 717 return ret; 718 return qcom_qmp_phy_pcie_msm8996_exit(phy); 719 } 720 721 static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy, 722 enum phy_mode mode, int submode) 723 { 724 struct qmp_phy *qphy = phy_get_drvdata(phy); 725 726 qphy->mode = mode; 727 728 return 0; 729 } 730 731 static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 732 { 733 struct qcom_qmp *qmp = dev_get_drvdata(dev); 734 int num = cfg->num_vregs; 735 int i; 736 737 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 738 if (!qmp->vregs) 739 return -ENOMEM; 740 741 for (i = 0; i < num; i++) 742 qmp->vregs[i].supply = cfg->vreg_list[i]; 743 744 return devm_regulator_bulk_get(dev, num, qmp->vregs); 745 } 746 747 static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 748 { 749 struct qcom_qmp *qmp = dev_get_drvdata(dev); 750 int i; 751 int ret; 752 753 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 754 sizeof(*qmp->resets), GFP_KERNEL); 755 if (!qmp->resets) 756 return -ENOMEM; 757 758 for (i = 0; i < cfg->num_resets; i++) 759 qmp->resets[i].id = cfg->reset_list[i]; 760 761 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 762 if (ret) 763 return dev_err_probe(dev, ret, "failed to get resets\n"); 764 765 return 0; 766 } 767 768 static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 769 { 770 struct qcom_qmp *qmp = dev_get_drvdata(dev); 771 int num = cfg->num_clks; 772 int i; 773 774 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 775 if (!qmp->clks) 776 return -ENOMEM; 777 778 for (i = 0; i < num; i++) 779 qmp->clks[i].id = cfg->clk_list[i]; 780 781 return devm_clk_bulk_get(dev, num, qmp->clks); 782 } 783 784 static void phy_clk_release_provider(void *res) 785 { 786 of_clk_del_provider(res); 787 } 788 789 /* 790 * Register a fixed rate pipe clock. 791 * 792 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 793 * controls it. The <s>_pipe_clk coming out of the GCC is requested 794 * by the PHY driver for its operations. 795 * We register the <s>_pipe_clksrc here. The gcc driver takes care 796 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 797 * Below picture shows this relationship. 798 * 799 * +---------------+ 800 * | PHY block |<<---------------------------------------+ 801 * | | | 802 * | +-------+ | +-----+ | 803 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 804 * clk | +-------+ | +-----+ 805 * +---------------+ 806 */ 807 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 808 { 809 struct clk_fixed_rate *fixed; 810 struct clk_init_data init = { }; 811 int ret; 812 813 ret = of_property_read_string(np, "clock-output-names", &init.name); 814 if (ret) { 815 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 816 return ret; 817 } 818 819 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 820 if (!fixed) 821 return -ENOMEM; 822 823 init.ops = &clk_fixed_rate_ops; 824 825 /* controllers using QMP phys use 125MHz pipe clock interface */ 826 fixed->fixed_rate = 125000000; 827 fixed->hw.init = &init; 828 829 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 830 if (ret) 831 return ret; 832 833 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 834 if (ret) 835 return ret; 836 837 /* 838 * Roll a devm action because the clock provider is the child node, but 839 * the child node is not actually a device. 840 */ 841 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 842 } 843 844 static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = { 845 .power_on = qcom_qmp_phy_pcie_msm8996_enable, 846 .power_off = qcom_qmp_phy_pcie_msm8996_disable, 847 .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, 848 .owner = THIS_MODULE, 849 }; 850 851 static void qcom_qmp_reset_control_put(void *data) 852 { 853 reset_control_put(data); 854 } 855 856 static 857 int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id, 858 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 859 { 860 struct qcom_qmp *qmp = dev_get_drvdata(dev); 861 struct phy *generic_phy; 862 struct qmp_phy *qphy; 863 char prop_name[MAX_PROP_NAME]; 864 int ret; 865 866 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 867 if (!qphy) 868 return -ENOMEM; 869 870 qphy->cfg = cfg; 871 qphy->serdes = serdes; 872 /* 873 * Get memory resources for each phy lane: 874 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 875 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 876 * For single lane PHYs: pcs_misc (optional) -> 3. 877 */ 878 qphy->tx = of_iomap(np, 0); 879 if (!qphy->tx) 880 return -ENOMEM; 881 882 qphy->rx = of_iomap(np, 1); 883 if (!qphy->rx) 884 return -ENOMEM; 885 886 qphy->pcs = of_iomap(np, 2); 887 if (!qphy->pcs) 888 return -ENOMEM; 889 890 qphy->pcs_misc = of_iomap(np, 3); 891 892 if (!qphy->pcs_misc) 893 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 894 895 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 896 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 897 if (IS_ERR(qphy->pipe_clk)) { 898 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 899 "failed to get lane%d pipe clock\n", id); 900 } 901 902 /* Get lane reset, if any */ 903 snprintf(prop_name, sizeof(prop_name), "lane%d", id); 904 qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); 905 if (IS_ERR(qphy->lane_rst)) { 906 dev_err(dev, "failed to get lane%d reset\n", id); 907 return PTR_ERR(qphy->lane_rst); 908 } 909 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 910 qphy->lane_rst); 911 if (ret) 912 return ret; 913 914 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); 915 if (IS_ERR(generic_phy)) { 916 ret = PTR_ERR(generic_phy); 917 dev_err(dev, "failed to create qphy %d\n", ret); 918 return ret; 919 } 920 921 qphy->phy = generic_phy; 922 qphy->index = id; 923 qphy->qmp = qmp; 924 qmp->phys[id] = qphy; 925 phy_set_drvdata(generic_phy, qphy); 926 927 return 0; 928 } 929 930 static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = { 931 { 932 .compatible = "qcom,msm8996-qmp-pcie-phy", 933 .data = &msm8996_pciephy_cfg, 934 }, 935 { }, 936 }; 937 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table); 938 939 static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) 940 { 941 struct qcom_qmp *qmp; 942 struct device *dev = &pdev->dev; 943 struct device_node *child; 944 struct phy_provider *phy_provider; 945 void __iomem *serdes; 946 const struct qmp_phy_cfg *cfg = NULL; 947 int num, id, expected_phys; 948 int ret; 949 950 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 951 if (!qmp) 952 return -ENOMEM; 953 954 qmp->dev = dev; 955 dev_set_drvdata(dev, qmp); 956 957 /* Get the specific init parameters of QMP phy */ 958 cfg = of_device_get_match_data(dev); 959 if (!cfg) 960 return -EINVAL; 961 962 /* per PHY serdes; usually located at base address */ 963 serdes = devm_platform_ioremap_resource(pdev, 0); 964 if (IS_ERR(serdes)) 965 return PTR_ERR(serdes); 966 967 expected_phys = cfg->nlanes; 968 969 mutex_init(&qmp->phy_mutex); 970 971 ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg); 972 if (ret) 973 return ret; 974 975 ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg); 976 if (ret) 977 return ret; 978 979 ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg); 980 if (ret) { 981 if (ret != -EPROBE_DEFER) 982 dev_err(dev, "failed to get regulator supplies: %d\n", 983 ret); 984 return ret; 985 } 986 987 num = of_get_available_child_count(dev->of_node); 988 /* do we have a rogue child node ? */ 989 if (num > expected_phys) 990 return -EINVAL; 991 992 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 993 if (!qmp->phys) 994 return -ENOMEM; 995 996 pm_runtime_set_active(dev); 997 pm_runtime_enable(dev); 998 /* 999 * Prevent runtime pm from being ON by default. Users can enable 1000 * it using power/control in sysfs. 1001 */ 1002 pm_runtime_forbid(dev); 1003 1004 id = 0; 1005 for_each_available_child_of_node(dev->of_node, child) { 1006 /* Create per-lane phy */ 1007 ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg); 1008 if (ret) { 1009 dev_err(dev, "failed to create lane%d phy, %d\n", 1010 id, ret); 1011 goto err_node_put; 1012 } 1013 1014 /* 1015 * Register the pipe clock provided by phy. 1016 * See function description to see details of this pipe clock. 1017 */ 1018 ret = phy_pipe_clk_register(qmp, child); 1019 if (ret) { 1020 dev_err(qmp->dev, 1021 "failed to register pipe clock source\n"); 1022 goto err_node_put; 1023 } 1024 1025 id++; 1026 } 1027 1028 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1029 if (!IS_ERR(phy_provider)) 1030 dev_info(dev, "Registered Qcom-QMP phy\n"); 1031 else 1032 pm_runtime_disable(dev); 1033 1034 return PTR_ERR_OR_ZERO(phy_provider); 1035 1036 err_node_put: 1037 pm_runtime_disable(dev); 1038 of_node_put(child); 1039 return ret; 1040 } 1041 1042 static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = { 1043 .probe = qcom_qmp_phy_pcie_msm8996_probe, 1044 .driver = { 1045 .name = "qcom-qmp-msm8996-pcie-phy", 1046 .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table, 1047 }, 1048 }; 1049 1050 module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver); 1051 1052 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1053 MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver"); 1054 MODULE_LICENSE("GPL v2"); 1055