1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy-qcom-qmp.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 /* QPHY_START_CONTROL bits */ 32 #define SERDES_START BIT(0) 33 #define PCS_START BIT(1) 34 /* QPHY_PCS_STATUS bit */ 35 #define PHYSTATUS BIT(6) 36 37 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 38 /* DP PHY soft reset */ 39 #define SW_DPPHY_RESET BIT(0) 40 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 41 #define SW_DPPHY_RESET_MUX BIT(1) 42 /* USB3 PHY soft reset */ 43 #define SW_USB3PHY_RESET BIT(2) 44 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 45 #define SW_USB3PHY_RESET_MUX BIT(3) 46 47 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 48 #define USB3_MODE BIT(0) /* enables USB3 mode */ 49 #define DP_MODE BIT(1) /* enables DP mode */ 50 51 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 52 #define ARCVR_DTCT_EN BIT(0) 53 #define ALFPS_DTCT_EN BIT(1) 54 #define ARCVR_DTCT_EVENT_SEL BIT(4) 55 56 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 57 #define IRQ_CLEAR BIT(0) 58 59 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 60 #define RCVR_DETECT BIT(0) 61 62 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 63 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 64 65 #define PHY_INIT_COMPLETE_TIMEOUT 10000 66 67 struct qmp_phy_init_tbl { 68 unsigned int offset; 69 unsigned int val; 70 /* 71 * mask of lanes for which this register is written 72 * for cases when second lane needs different values 73 */ 74 u8 lane_mask; 75 }; 76 77 #define QMP_PHY_INIT_CFG(o, v) \ 78 { \ 79 .offset = o, \ 80 .val = v, \ 81 .lane_mask = 0xff, \ 82 } 83 84 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 85 { \ 86 .offset = o, \ 87 .val = v, \ 88 .lane_mask = l, \ 89 } 90 91 /* set of registers with offsets different per-PHY */ 92 enum qphy_reg_layout { 93 /* PCS registers */ 94 QPHY_SW_RESET, 95 QPHY_START_CTRL, 96 QPHY_PCS_STATUS, 97 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 98 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 99 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 100 QPHY_PCS_POWER_DOWN_CONTROL, 101 /* Keep last to ensure regs_layout arrays are properly initialized */ 102 QPHY_LAYOUT_SIZE 103 }; 104 105 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 106 [QPHY_SW_RESET] = 0x00, 107 [QPHY_START_CTRL] = 0x08, 108 [QPHY_PCS_STATUS] = 0x174, 109 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 110 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 111 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 112 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 113 }; 114 115 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 116 [QPHY_SW_RESET] = 0x00, 117 [QPHY_START_CTRL] = 0x44, 118 [QPHY_PCS_STATUS] = 0x14, 119 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 120 121 /* In PCS_USB */ 122 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008, 123 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014, 124 }; 125 126 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 163 }; 164 165 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 166 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 167 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 169 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 170 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 171 }; 172 173 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 174 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 175 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 176 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 177 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 178 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 179 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 180 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 181 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 182 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 183 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 184 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 186 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 187 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 195 }; 196 197 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 205 }; 206 207 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 215 }; 216 217 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 225 }; 226 227 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 235 }; 236 237 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 238 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 239 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 240 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 241 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 242 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 243 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 244 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 245 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 248 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 249 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 250 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 251 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 252 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 253 }; 254 255 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 256 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 257 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 258 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 259 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 260 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 261 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 262 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 264 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 265 }; 266 267 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 268 /* FLL settings */ 269 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 274 275 /* Lock Det settings */ 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 280 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 300 301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 312 }; 313 314 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 315 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 316 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 317 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 318 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 319 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 320 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 321 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 322 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 323 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 324 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 325 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 326 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 327 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 328 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 329 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 330 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 331 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 332 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 333 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 334 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 335 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 336 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 337 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 338 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 339 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 340 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 341 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 342 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 343 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 344 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 345 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 346 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 347 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 348 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 349 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 350 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 351 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 352 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 353 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 354 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 355 }; 356 357 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 358 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 359 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 360 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 361 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 362 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 363 }; 364 365 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 366 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 367 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 368 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 369 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 370 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 371 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 372 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 373 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 374 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 375 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 376 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 377 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 378 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 379 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 380 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 381 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 382 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 383 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 384 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 385 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 386 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 387 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 388 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 389 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 390 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 391 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 392 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 393 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 394 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 395 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 396 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 397 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 398 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 399 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 400 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 401 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 402 }; 403 404 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 405 /* Lock Det settings */ 406 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 407 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 408 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 409 410 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 411 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 412 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 413 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 414 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 415 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 416 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 417 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 418 }; 419 420 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 421 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 422 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 423 }; 424 425 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 426 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 427 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 428 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 429 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 430 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 431 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 432 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 433 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 434 }; 435 436 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 457 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 458 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 459 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 460 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 475 }; 476 477 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 478 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 490 }; 491 492 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 495 }; 496 497 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 516 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 517 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 518 }; 519 520 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 528 }; 529 530 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 538 }; 539 540 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 548 }; 549 550 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 552 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 558 }; 559 560 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 561 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 562 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 563 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 564 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 565 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 566 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 567 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 568 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 569 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 570 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 571 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 572 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 573 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 574 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 575 }; 576 577 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 578 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 579 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 580 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 581 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 582 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 583 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 585 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 586 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 587 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 588 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 589 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 590 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 593 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 594 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 595 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 596 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 597 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 598 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 599 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 601 }; 602 603 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 604 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 605 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 606 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 607 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 608 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 609 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 610 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 611 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 612 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 613 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 614 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 615 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 616 }; 617 618 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 619 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 620 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 621 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 622 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 623 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 624 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 625 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 626 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 627 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 628 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 629 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 630 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 631 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 632 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 633 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 634 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 635 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 636 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 637 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 638 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 639 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 640 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 641 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 642 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 643 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 644 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 645 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 646 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 647 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 648 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 649 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 650 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 651 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 652 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 653 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 654 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 655 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 656 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 657 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 658 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 659 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 660 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 661 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 662 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 663 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 664 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 665 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 666 }; 667 668 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 669 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 670 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 671 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 672 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 673 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 674 }; 675 676 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 677 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 678 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 679 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 680 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 681 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 682 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 683 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 684 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 685 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 686 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 687 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 688 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 689 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 690 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 691 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 692 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 693 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 694 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 695 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 696 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 697 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 698 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 699 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 700 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 701 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 702 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 703 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 704 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 705 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 706 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 707 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 708 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 709 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 710 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 711 }; 712 713 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 714 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 715 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 716 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 717 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 718 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 719 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 720 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 721 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 724 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 725 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 726 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 730 }; 731 732 /* list of regulators */ 733 struct qmp_regulator_data { 734 const char *name; 735 unsigned int enable_load; 736 }; 737 738 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 739 { .name = "vdda-phy", .enable_load = 21800 }, 740 { .name = "vdda-pll", .enable_load = 36000 }, 741 }; 742 743 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 744 { 0x00, 0x0c, 0x15, 0x1a }, 745 { 0x02, 0x0e, 0x16, 0xff }, 746 { 0x02, 0x11, 0xff, 0xff }, 747 { 0x04, 0xff, 0xff, 0xff } 748 }; 749 750 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 751 { 0x02, 0x12, 0x16, 0x1a }, 752 { 0x09, 0x19, 0x1f, 0xff }, 753 { 0x10, 0x1f, 0xff, 0xff }, 754 { 0x1f, 0xff, 0xff, 0xff } 755 }; 756 757 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 758 { 0x00, 0x0c, 0x14, 0x19 }, 759 { 0x00, 0x0b, 0x12, 0xff }, 760 { 0x00, 0x0b, 0xff, 0xff }, 761 { 0x04, 0xff, 0xff, 0xff } 762 }; 763 764 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 765 { 0x08, 0x0f, 0x16, 0x1f }, 766 { 0x11, 0x1e, 0x1f, 0xff }, 767 { 0x19, 0x1f, 0xff, 0xff }, 768 { 0x1f, 0xff, 0xff, 0xff } 769 }; 770 771 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 772 { 0x20, 0x2c, 0x35, 0x3b }, 773 { 0x22, 0x2e, 0x36, 0xff }, 774 { 0x22, 0x31, 0xff, 0xff }, 775 { 0x24, 0xff, 0xff, 0xff } 776 }; 777 778 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 779 { 0x22, 0x32, 0x36, 0x3a }, 780 { 0x29, 0x39, 0x3f, 0xff }, 781 { 0x30, 0x3f, 0xff, 0xff }, 782 { 0x3f, 0xff, 0xff, 0xff } 783 }; 784 785 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 786 { 0x20, 0x2d, 0x34, 0x3a }, 787 { 0x20, 0x2e, 0x35, 0xff }, 788 { 0x20, 0x2e, 0xff, 0xff }, 789 { 0x24, 0xff, 0xff, 0xff } 790 }; 791 792 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 793 { 0x28, 0x2f, 0x36, 0x3f }, 794 { 0x31, 0x3e, 0x3f, 0xff }, 795 { 0x36, 0x3f, 0xff, 0xff }, 796 { 0x3f, 0xff, 0xff, 0xff } 797 }; 798 799 struct qmp_combo; 800 801 struct qmp_combo_offsets { 802 u16 com; 803 u16 txa; 804 u16 rxa; 805 u16 txb; 806 u16 rxb; 807 u16 usb3_serdes; 808 u16 usb3_pcs_misc; 809 u16 usb3_pcs; 810 u16 usb3_pcs_usb; 811 u16 dp_serdes; 812 u16 dp_dp_phy; 813 }; 814 815 struct qmp_phy_cfg { 816 const struct qmp_combo_offsets *offsets; 817 818 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 819 const struct qmp_phy_init_tbl *serdes_tbl; 820 int serdes_tbl_num; 821 const struct qmp_phy_init_tbl *tx_tbl; 822 int tx_tbl_num; 823 const struct qmp_phy_init_tbl *rx_tbl; 824 int rx_tbl_num; 825 const struct qmp_phy_init_tbl *pcs_tbl; 826 int pcs_tbl_num; 827 const struct qmp_phy_init_tbl *pcs_usb_tbl; 828 int pcs_usb_tbl_num; 829 830 const struct qmp_phy_init_tbl *dp_serdes_tbl; 831 int dp_serdes_tbl_num; 832 const struct qmp_phy_init_tbl *dp_tx_tbl; 833 int dp_tx_tbl_num; 834 835 /* Init sequence for DP PHY block link rates */ 836 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 837 int serdes_tbl_rbr_num; 838 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 839 int serdes_tbl_hbr_num; 840 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 841 int serdes_tbl_hbr2_num; 842 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 843 int serdes_tbl_hbr3_num; 844 845 /* DP PHY swing and pre_emphasis tables */ 846 const u8 (*swing_hbr_rbr)[4][4]; 847 const u8 (*swing_hbr3_hbr2)[4][4]; 848 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 849 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 850 851 /* DP PHY callbacks */ 852 int (*configure_dp_phy)(struct qmp_combo *qmp); 853 void (*configure_dp_tx)(struct qmp_combo *qmp); 854 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 855 void (*dp_aux_init)(struct qmp_combo *qmp); 856 857 /* clock ids to be requested */ 858 const char * const *clk_list; 859 int num_clks; 860 /* resets to be requested */ 861 const char * const *reset_list; 862 int num_resets; 863 /* regulators to be requested */ 864 const struct qmp_regulator_data *vreg_list; 865 int num_vregs; 866 867 /* array of registers with different offsets */ 868 const unsigned int *regs; 869 870 /* true, if PHY needs delay after POWER_DOWN */ 871 bool has_pwrdn_delay; 872 873 /* Offset from PCS to PCS_USB region */ 874 unsigned int pcs_usb_offset; 875 876 }; 877 878 struct qmp_combo { 879 struct device *dev; 880 881 const struct qmp_phy_cfg *cfg; 882 883 void __iomem *com; 884 885 void __iomem *serdes; 886 void __iomem *tx; 887 void __iomem *rx; 888 void __iomem *pcs; 889 void __iomem *tx2; 890 void __iomem *rx2; 891 void __iomem *pcs_misc; 892 void __iomem *pcs_usb; 893 894 void __iomem *dp_serdes; 895 void __iomem *dp_tx; 896 void __iomem *dp_tx2; 897 void __iomem *dp_dp_phy; 898 899 struct clk *pipe_clk; 900 struct clk_bulk_data *clks; 901 struct reset_control_bulk_data *resets; 902 struct regulator_bulk_data *vregs; 903 904 struct mutex phy_mutex; 905 int init_count; 906 907 struct phy *usb_phy; 908 enum phy_mode mode; 909 910 struct phy *dp_phy; 911 unsigned int dp_aux_cfg; 912 struct phy_configure_opts_dp dp_opts; 913 914 struct clk_fixed_rate pipe_clk_fixed; 915 struct clk_hw dp_link_hw; 916 struct clk_hw dp_pixel_hw; 917 }; 918 919 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 920 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 921 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 922 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 923 924 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 925 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 926 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 927 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 928 929 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp); 930 931 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 932 { 933 u32 reg; 934 935 reg = readl(base + offset); 936 reg |= val; 937 writel(reg, base + offset); 938 939 /* ensure that above write is through */ 940 readl(base + offset); 941 } 942 943 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 944 { 945 u32 reg; 946 947 reg = readl(base + offset); 948 reg &= ~val; 949 writel(reg, base + offset); 950 951 /* ensure that above write is through */ 952 readl(base + offset); 953 } 954 955 /* list of clocks required by phy */ 956 static const char * const qmp_v3_phy_clk_l[] = { 957 "aux", "cfg_ahb", "ref", "com_aux", 958 }; 959 960 static const char * const qmp_v4_phy_clk_l[] = { 961 "aux", "ref", "com_aux", 962 }; 963 964 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 965 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 966 "aux", "ref_clk_src", "com_aux" 967 }; 968 969 /* list of resets */ 970 static const char * const msm8996_usb3phy_reset_l[] = { 971 "phy", "common", 972 }; 973 974 static const char * const sc7180_usb3phy_reset_l[] = { 975 "phy", 976 }; 977 978 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 979 .com = 0x0000, 980 .txa = 0x0400, 981 .rxa = 0x0600, 982 .txb = 0x0a00, 983 .rxb = 0x0c00, 984 .usb3_serdes = 0x1000, 985 .usb3_pcs_misc = 0x1200, 986 .usb3_pcs = 0x1400, 987 .usb3_pcs_usb = 0x1700, 988 .dp_serdes = 0x2000, 989 .dp_dp_phy = 0x2200, 990 }; 991 992 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 993 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 994 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 995 .tx_tbl = qmp_v3_usb3_tx_tbl, 996 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 997 .rx_tbl = qmp_v3_usb3_rx_tbl, 998 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 999 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1000 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1001 1002 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1003 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1004 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1005 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1006 1007 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1008 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1009 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1010 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1011 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1012 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1013 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1014 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1015 1016 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1017 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1018 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1019 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1020 1021 .dp_aux_init = qmp_v3_dp_aux_init, 1022 .configure_dp_tx = qmp_v3_configure_dp_tx, 1023 .configure_dp_phy = qmp_v3_configure_dp_phy, 1024 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1025 1026 .clk_list = qmp_v3_phy_clk_l, 1027 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1028 .reset_list = sc7180_usb3phy_reset_l, 1029 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1030 .vreg_list = qmp_phy_vreg_l, 1031 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1032 .regs = qmp_v3_usb3phy_regs_layout, 1033 1034 .has_pwrdn_delay = true, 1035 }; 1036 1037 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1038 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1039 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1040 .tx_tbl = qmp_v3_usb3_tx_tbl, 1041 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1042 .rx_tbl = qmp_v3_usb3_rx_tbl, 1043 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1044 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1045 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1046 1047 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1048 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1049 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1050 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1051 1052 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1053 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1054 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1055 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1056 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1057 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1058 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1059 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1060 1061 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1062 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1063 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1064 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1065 1066 .dp_aux_init = qmp_v3_dp_aux_init, 1067 .configure_dp_tx = qmp_v3_configure_dp_tx, 1068 .configure_dp_phy = qmp_v3_configure_dp_phy, 1069 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1070 1071 .clk_list = qmp_v3_phy_clk_l, 1072 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1073 .reset_list = msm8996_usb3phy_reset_l, 1074 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1075 .vreg_list = qmp_phy_vreg_l, 1076 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1077 .regs = qmp_v3_usb3phy_regs_layout, 1078 1079 .has_pwrdn_delay = true, 1080 }; 1081 1082 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1083 .serdes_tbl = sm8150_usb3_serdes_tbl, 1084 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1085 .tx_tbl = sm8150_usb3_tx_tbl, 1086 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1087 .rx_tbl = sm8150_usb3_rx_tbl, 1088 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1089 .pcs_tbl = sm8150_usb3_pcs_tbl, 1090 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1091 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1092 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1093 1094 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1095 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1096 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1097 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1098 1099 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1100 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1101 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1102 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1103 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1104 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1105 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1106 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1107 1108 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1109 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1110 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1111 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1112 1113 .dp_aux_init = qmp_v4_dp_aux_init, 1114 .configure_dp_tx = qmp_v4_configure_dp_tx, 1115 .configure_dp_phy = qmp_v4_configure_dp_phy, 1116 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1117 1118 .clk_list = qmp_v4_phy_clk_l, 1119 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1120 .reset_list = msm8996_usb3phy_reset_l, 1121 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1122 .vreg_list = qmp_phy_vreg_l, 1123 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1124 .regs = qmp_v4_usb3phy_regs_layout, 1125 .pcs_usb_offset = 0x300, 1126 1127 .has_pwrdn_delay = true, 1128 }; 1129 1130 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1131 .offsets = &qmp_combo_offsets_v5, 1132 1133 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1134 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1135 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1136 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1137 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1138 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1139 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1140 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1141 1142 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1143 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1144 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1145 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1146 1147 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1148 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1149 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1150 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1151 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1152 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1153 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1154 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1155 1156 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1157 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1158 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1159 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1160 1161 .dp_aux_init = qmp_v4_dp_aux_init, 1162 .configure_dp_tx = qmp_v4_configure_dp_tx, 1163 .configure_dp_phy = qmp_v5_configure_dp_phy, 1164 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1165 1166 .clk_list = qmp_v4_phy_clk_l, 1167 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1168 .reset_list = msm8996_usb3phy_reset_l, 1169 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1170 .vreg_list = qmp_phy_vreg_l, 1171 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1172 .regs = qmp_v4_usb3phy_regs_layout, 1173 }; 1174 1175 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1176 .serdes_tbl = sm8150_usb3_serdes_tbl, 1177 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1178 .tx_tbl = sm8250_usb3_tx_tbl, 1179 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1180 .rx_tbl = sm8250_usb3_rx_tbl, 1181 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1182 .pcs_tbl = sm8250_usb3_pcs_tbl, 1183 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1184 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1185 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1186 1187 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1188 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1189 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1190 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1191 1192 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1193 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1194 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1195 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1196 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1197 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1198 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1199 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1200 1201 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1202 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1203 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1204 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1205 1206 .dp_aux_init = qmp_v4_dp_aux_init, 1207 .configure_dp_tx = qmp_v4_configure_dp_tx, 1208 .configure_dp_phy = qmp_v4_configure_dp_phy, 1209 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1210 1211 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1212 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1213 .reset_list = msm8996_usb3phy_reset_l, 1214 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1215 .vreg_list = qmp_phy_vreg_l, 1216 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1217 .regs = qmp_v4_usb3phy_regs_layout, 1218 .pcs_usb_offset = 0x300, 1219 1220 .has_pwrdn_delay = true, 1221 }; 1222 1223 static void qmp_combo_configure_lane(void __iomem *base, 1224 const struct qmp_phy_init_tbl tbl[], 1225 int num, 1226 u8 lane_mask) 1227 { 1228 int i; 1229 const struct qmp_phy_init_tbl *t = tbl; 1230 1231 if (!t) 1232 return; 1233 1234 for (i = 0; i < num; i++, t++) { 1235 if (!(t->lane_mask & lane_mask)) 1236 continue; 1237 1238 writel(t->val, base + t->offset); 1239 } 1240 } 1241 1242 static void qmp_combo_configure(void __iomem *base, 1243 const struct qmp_phy_init_tbl tbl[], 1244 int num) 1245 { 1246 qmp_combo_configure_lane(base, tbl, num, 0xff); 1247 } 1248 1249 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 1250 { 1251 const struct qmp_phy_cfg *cfg = qmp->cfg; 1252 void __iomem *serdes = qmp->dp_serdes; 1253 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1254 1255 qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 1256 1257 switch (dp_opts->link_rate) { 1258 case 1620: 1259 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1260 cfg->serdes_tbl_rbr_num); 1261 break; 1262 case 2700: 1263 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1264 cfg->serdes_tbl_hbr_num); 1265 break; 1266 case 5400: 1267 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1268 cfg->serdes_tbl_hbr2_num); 1269 break; 1270 case 8100: 1271 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1272 cfg->serdes_tbl_hbr3_num); 1273 break; 1274 default: 1275 /* Other link rates aren't supported */ 1276 return -EINVAL; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 1283 { 1284 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1285 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1286 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1287 1288 /* Turn on BIAS current for PHY/PLL */ 1289 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1290 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1291 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1292 1293 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1294 1295 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1296 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1297 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1298 DP_PHY_PD_CTL_DP_CLAMP_EN, 1299 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1300 1301 writel(QSERDES_V3_COM_BIAS_EN | 1302 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1303 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1304 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1305 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1306 1307 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1308 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1309 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1310 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1311 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1312 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1313 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1314 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1315 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1316 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1317 qmp->dp_aux_cfg = 0; 1318 1319 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1320 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1321 PHY_AUX_REQ_ERR_MASK, 1322 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1323 } 1324 1325 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp, 1326 unsigned int drv_lvl_reg, unsigned int emp_post_reg) 1327 { 1328 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1329 const struct qmp_phy_cfg *cfg = qmp->cfg; 1330 unsigned int v_level = 0, p_level = 0; 1331 u8 voltage_swing_cfg, pre_emphasis_cfg; 1332 int i; 1333 1334 for (i = 0; i < dp_opts->lanes; i++) { 1335 v_level = max(v_level, dp_opts->voltage[i]); 1336 p_level = max(p_level, dp_opts->pre[i]); 1337 } 1338 1339 if (dp_opts->link_rate <= 2700) { 1340 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 1341 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 1342 } else { 1343 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 1344 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 1345 } 1346 1347 /* TODO: Move check to config check */ 1348 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 1349 return -EINVAL; 1350 1351 /* Enable MUX to use Cursor values from these registers */ 1352 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 1353 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 1354 1355 writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg); 1356 writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg); 1357 writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg); 1358 writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg); 1359 1360 return 0; 1361 } 1362 1363 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 1364 { 1365 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1366 u32 bias_en, drvr_en; 1367 1368 if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL, 1369 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) 1370 return; 1371 1372 if (dp_opts->lanes == 1) { 1373 bias_en = 0x3e; 1374 drvr_en = 0x13; 1375 } else { 1376 bias_en = 0x3f; 1377 drvr_en = 0x10; 1378 } 1379 1380 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1381 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1382 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1383 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1384 } 1385 1386 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 1387 { 1388 u32 val; 1389 bool reverse = false; 1390 1391 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1392 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 1393 1394 /* 1395 * TODO: Assume orientation is CC1 for now and two lanes, need to 1396 * use type-c connector to understand orientation and lanes. 1397 * 1398 * Otherwise val changes to be like below if this code understood 1399 * the orientation of the type-c cable. 1400 * 1401 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) 1402 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 1403 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) 1404 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1405 * if (orientation == ORIENTATION_CC2) 1406 * writel(0x4c, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_MODE); 1407 */ 1408 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1409 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1410 1411 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 1412 1413 return reverse; 1414 } 1415 1416 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 1417 { 1418 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1419 u32 phy_vco_div, status; 1420 unsigned long pixel_freq; 1421 1422 qmp_combo_configure_dp_mode(qmp); 1423 1424 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 1425 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 1426 1427 switch (dp_opts->link_rate) { 1428 case 1620: 1429 phy_vco_div = 0x1; 1430 pixel_freq = 1620000000UL / 2; 1431 break; 1432 case 2700: 1433 phy_vco_div = 0x1; 1434 pixel_freq = 2700000000UL / 2; 1435 break; 1436 case 5400: 1437 phy_vco_div = 0x2; 1438 pixel_freq = 5400000000UL / 4; 1439 break; 1440 case 8100: 1441 phy_vco_div = 0x0; 1442 pixel_freq = 8100000000UL / 6; 1443 break; 1444 default: 1445 /* Other link rates aren't supported */ 1446 return -EINVAL; 1447 } 1448 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV); 1449 1450 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 1451 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 1452 1453 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1454 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1455 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1456 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1457 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1458 1459 writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL); 1460 1461 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V3_COM_C_READY_STATUS, 1462 status, 1463 ((status & BIT(0)) > 0), 1464 500, 1465 10000)) 1466 return -ETIMEDOUT; 1467 1468 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1469 1470 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 1471 status, 1472 ((status & BIT(1)) > 0), 1473 500, 1474 10000)) 1475 return -ETIMEDOUT; 1476 1477 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1478 udelay(2000); 1479 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1480 1481 return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 1482 status, 1483 ((status & BIT(1)) > 0), 1484 500, 1485 10000); 1486 } 1487 1488 /* 1489 * We need to calibrate the aux setting here as many times 1490 * as the caller tries 1491 */ 1492 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 1493 { 1494 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 1495 u8 val; 1496 1497 qmp->dp_aux_cfg++; 1498 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1499 val = cfg1_settings[qmp->dp_aux_cfg]; 1500 1501 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1502 1503 return 0; 1504 } 1505 1506 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 1507 { 1508 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1509 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1510 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1511 1512 /* Turn on BIAS current for PHY/PLL */ 1513 writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 1514 1515 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1516 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1517 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1518 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1519 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1520 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1521 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1522 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1523 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1524 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1525 qmp->dp_aux_cfg = 0; 1526 1527 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1528 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1529 PHY_AUX_REQ_ERR_MASK, 1530 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 1531 } 1532 1533 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 1534 { 1535 /* Program default values before writing proper values */ 1536 writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); 1537 writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1538 1539 writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1540 writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1541 1542 qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL, 1543 QSERDES_V4_TX_TX_EMP_POST1_LVL); 1544 } 1545 1546 static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) 1547 { 1548 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1549 u32 phy_vco_div, status; 1550 unsigned long pixel_freq; 1551 1552 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 1553 1554 qmp_combo_configure_dp_mode(qmp); 1555 1556 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1557 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1558 1559 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 1560 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 1561 1562 switch (dp_opts->link_rate) { 1563 case 1620: 1564 phy_vco_div = 0x1; 1565 pixel_freq = 1620000000UL / 2; 1566 break; 1567 case 2700: 1568 phy_vco_div = 0x1; 1569 pixel_freq = 2700000000UL / 2; 1570 break; 1571 case 5400: 1572 phy_vco_div = 0x2; 1573 pixel_freq = 5400000000UL / 4; 1574 break; 1575 case 8100: 1576 phy_vco_div = 0x0; 1577 pixel_freq = 8100000000UL / 6; 1578 break; 1579 default: 1580 /* Other link rates aren't supported */ 1581 return -EINVAL; 1582 } 1583 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 1584 1585 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 1586 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 1587 1588 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1589 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1590 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1591 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1592 1593 writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL); 1594 1595 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_C_READY_STATUS, 1596 status, 1597 ((status & BIT(0)) > 0), 1598 500, 1599 10000)) 1600 return -ETIMEDOUT; 1601 1602 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS, 1603 status, 1604 ((status & BIT(0)) > 0), 1605 500, 1606 10000)) 1607 return -ETIMEDOUT; 1608 1609 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS, 1610 status, 1611 ((status & BIT(1)) > 0), 1612 500, 1613 10000)) 1614 return -ETIMEDOUT; 1615 1616 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1617 1618 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1619 status, 1620 ((status & BIT(0)) > 0), 1621 500, 1622 10000)) 1623 return -ETIMEDOUT; 1624 1625 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1626 status, 1627 ((status & BIT(1)) > 0), 1628 500, 1629 10000)) 1630 return -ETIMEDOUT; 1631 1632 return 0; 1633 } 1634 1635 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 1636 { 1637 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1638 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1639 bool reverse = false; 1640 u32 status; 1641 int ret; 1642 1643 ret = qmp_v45_configure_dp_phy(qmp); 1644 if (ret < 0) 1645 return ret; 1646 1647 /* 1648 * At least for 7nm DP PHY this has to be done after enabling link 1649 * clock. 1650 */ 1651 1652 if (dp_opts->lanes == 1) { 1653 bias0_en = reverse ? 0x3e : 0x15; 1654 bias1_en = reverse ? 0x15 : 0x3e; 1655 drvr0_en = reverse ? 0x13 : 0x10; 1656 drvr1_en = reverse ? 0x10 : 0x13; 1657 } else if (dp_opts->lanes == 2) { 1658 bias0_en = reverse ? 0x3f : 0x15; 1659 bias1_en = reverse ? 0x15 : 0x3f; 1660 drvr0_en = 0x10; 1661 drvr1_en = 0x10; 1662 } else { 1663 bias0_en = 0x3f; 1664 bias1_en = 0x3f; 1665 drvr0_en = 0x10; 1666 drvr1_en = 0x10; 1667 } 1668 1669 writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1670 writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1671 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1672 writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1673 1674 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1675 udelay(2000); 1676 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1677 1678 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1679 status, 1680 ((status & BIT(1)) > 0), 1681 500, 1682 10000)) 1683 return -ETIMEDOUT; 1684 1685 writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV); 1686 writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV); 1687 1688 writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); 1689 writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1690 1691 writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1692 writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1693 1694 return 0; 1695 } 1696 1697 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) 1698 { 1699 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1700 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1701 bool reverse = false; 1702 u32 status; 1703 int ret; 1704 1705 ret = qmp_v45_configure_dp_phy(qmp); 1706 if (ret < 0) 1707 return ret; 1708 1709 if (dp_opts->lanes == 1) { 1710 bias0_en = reverse ? 0x3e : 0x1a; 1711 drvr0_en = reverse ? 0x13 : 0x10; 1712 bias1_en = reverse ? 0x15 : 0x3e; 1713 drvr1_en = reverse ? 0x10 : 0x13; 1714 } else if (dp_opts->lanes == 2) { 1715 bias0_en = reverse ? 0x3f : 0x15; 1716 drvr0_en = 0x10; 1717 bias1_en = reverse ? 0x15 : 0x3f; 1718 drvr1_en = 0x10; 1719 } else { 1720 bias0_en = 0x3f; 1721 bias1_en = 0x3f; 1722 drvr0_en = 0x10; 1723 drvr1_en = 0x10; 1724 } 1725 1726 writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1727 writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1728 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1729 writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1730 1731 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1732 udelay(2000); 1733 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1734 1735 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1736 status, 1737 ((status & BIT(1)) > 0), 1738 500, 1739 10000)) 1740 return -ETIMEDOUT; 1741 1742 writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV); 1743 writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); 1744 1745 writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1746 writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1747 1748 writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1749 writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1750 1751 return 0; 1752 } 1753 1754 /* 1755 * We need to calibrate the aux setting here as many times 1756 * as the caller tries 1757 */ 1758 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 1759 { 1760 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 1761 u8 val; 1762 1763 qmp->dp_aux_cfg++; 1764 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1765 val = cfg1_settings[qmp->dp_aux_cfg]; 1766 1767 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1768 1769 return 0; 1770 } 1771 1772 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 1773 { 1774 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1775 struct qmp_combo *qmp = phy_get_drvdata(phy); 1776 const struct qmp_phy_cfg *cfg = qmp->cfg; 1777 1778 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 1779 if (qmp->dp_opts.set_voltages) { 1780 cfg->configure_dp_tx(qmp); 1781 qmp->dp_opts.set_voltages = 0; 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int qmp_combo_dp_calibrate(struct phy *phy) 1788 { 1789 struct qmp_combo *qmp = phy_get_drvdata(phy); 1790 const struct qmp_phy_cfg *cfg = qmp->cfg; 1791 1792 if (cfg->calibrate_dp_phy) 1793 return cfg->calibrate_dp_phy(qmp); 1794 1795 return 0; 1796 } 1797 1798 static int qmp_combo_com_init(struct qmp_combo *qmp) 1799 { 1800 const struct qmp_phy_cfg *cfg = qmp->cfg; 1801 void __iomem *com = qmp->com; 1802 int ret; 1803 1804 mutex_lock(&qmp->phy_mutex); 1805 if (qmp->init_count++) { 1806 mutex_unlock(&qmp->phy_mutex); 1807 return 0; 1808 } 1809 1810 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1811 if (ret) { 1812 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1813 goto err_unlock; 1814 } 1815 1816 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1817 if (ret) { 1818 dev_err(qmp->dev, "reset assert failed\n"); 1819 goto err_disable_regulators; 1820 } 1821 1822 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1823 if (ret) { 1824 dev_err(qmp->dev, "reset deassert failed\n"); 1825 goto err_disable_regulators; 1826 } 1827 1828 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1829 if (ret) 1830 goto err_assert_reset; 1831 1832 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 1833 1834 /* override hardware control for reset of qmp phy */ 1835 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1836 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1837 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1838 1839 /* Default type-c orientation, i.e CC1 */ 1840 qphy_setbits(com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 1841 1842 qphy_setbits(com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); 1843 1844 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 1845 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1846 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1847 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1848 1849 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 1850 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1851 1852 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1853 SW_PWRDN); 1854 1855 mutex_unlock(&qmp->phy_mutex); 1856 1857 return 0; 1858 1859 err_assert_reset: 1860 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1861 err_disable_regulators: 1862 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1863 err_unlock: 1864 mutex_unlock(&qmp->phy_mutex); 1865 1866 return ret; 1867 } 1868 1869 static int qmp_combo_com_exit(struct qmp_combo *qmp) 1870 { 1871 const struct qmp_phy_cfg *cfg = qmp->cfg; 1872 1873 mutex_lock(&qmp->phy_mutex); 1874 if (--qmp->init_count) { 1875 mutex_unlock(&qmp->phy_mutex); 1876 return 0; 1877 } 1878 1879 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1880 1881 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1882 1883 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1884 1885 mutex_unlock(&qmp->phy_mutex); 1886 1887 return 0; 1888 } 1889 1890 static int qmp_combo_dp_init(struct phy *phy) 1891 { 1892 struct qmp_combo *qmp = phy_get_drvdata(phy); 1893 const struct qmp_phy_cfg *cfg = qmp->cfg; 1894 int ret; 1895 1896 ret = qmp_combo_com_init(qmp); 1897 if (ret) 1898 return ret; 1899 1900 cfg->dp_aux_init(qmp); 1901 1902 return 0; 1903 } 1904 1905 static int qmp_combo_dp_exit(struct phy *phy) 1906 { 1907 struct qmp_combo *qmp = phy_get_drvdata(phy); 1908 1909 qmp_combo_com_exit(qmp); 1910 1911 return 0; 1912 } 1913 1914 static int qmp_combo_dp_power_on(struct phy *phy) 1915 { 1916 struct qmp_combo *qmp = phy_get_drvdata(phy); 1917 const struct qmp_phy_cfg *cfg = qmp->cfg; 1918 void __iomem *tx = qmp->dp_tx; 1919 void __iomem *tx2 = qmp->dp_tx2; 1920 1921 qmp_combo_dp_serdes_init(qmp); 1922 1923 qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 1924 qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 1925 1926 /* Configure special DP tx tunings */ 1927 cfg->configure_dp_tx(qmp); 1928 1929 /* Configure link rate, swing, etc. */ 1930 cfg->configure_dp_phy(qmp); 1931 1932 return 0; 1933 } 1934 1935 static int qmp_combo_dp_power_off(struct phy *phy) 1936 { 1937 struct qmp_combo *qmp = phy_get_drvdata(phy); 1938 1939 /* Assert DP PHY power down */ 1940 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1941 1942 return 0; 1943 } 1944 1945 static int qmp_combo_usb_power_on(struct phy *phy) 1946 { 1947 struct qmp_combo *qmp = phy_get_drvdata(phy); 1948 const struct qmp_phy_cfg *cfg = qmp->cfg; 1949 void __iomem *serdes = qmp->serdes; 1950 void __iomem *tx = qmp->tx; 1951 void __iomem *rx = qmp->rx; 1952 void __iomem *tx2 = qmp->tx2; 1953 void __iomem *rx2 = qmp->rx2; 1954 void __iomem *pcs = qmp->pcs; 1955 void __iomem *status; 1956 unsigned int val; 1957 int ret; 1958 1959 qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 1960 1961 ret = clk_prepare_enable(qmp->pipe_clk); 1962 if (ret) { 1963 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1964 return ret; 1965 } 1966 1967 /* Tx, Rx, and PCS configurations */ 1968 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 1969 qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 1970 1971 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 1972 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 1973 1974 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1975 1976 if (cfg->has_pwrdn_delay) 1977 usleep_range(10, 20); 1978 1979 /* Pull PHY out of reset state */ 1980 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1981 1982 /* start SerDes and Phy-Coding-Sublayer */ 1983 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 1984 1985 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 1986 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 1987 PHY_INIT_COMPLETE_TIMEOUT); 1988 if (ret) { 1989 dev_err(qmp->dev, "phy initialization timed-out\n"); 1990 goto err_disable_pipe_clk; 1991 } 1992 1993 return 0; 1994 1995 err_disable_pipe_clk: 1996 clk_disable_unprepare(qmp->pipe_clk); 1997 1998 return ret; 1999 } 2000 2001 static int qmp_combo_usb_power_off(struct phy *phy) 2002 { 2003 struct qmp_combo *qmp = phy_get_drvdata(phy); 2004 const struct qmp_phy_cfg *cfg = qmp->cfg; 2005 2006 clk_disable_unprepare(qmp->pipe_clk); 2007 2008 /* PHY reset */ 2009 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2010 2011 /* stop SerDes and Phy-Coding-Sublayer */ 2012 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2013 SERDES_START | PCS_START); 2014 2015 /* Put PHY into POWER DOWN state: active low */ 2016 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2017 SW_PWRDN); 2018 2019 return 0; 2020 } 2021 2022 static int qmp_combo_usb_init(struct phy *phy) 2023 { 2024 struct qmp_combo *qmp = phy_get_drvdata(phy); 2025 int ret; 2026 2027 ret = qmp_combo_com_init(qmp); 2028 if (ret) 2029 return ret; 2030 2031 ret = qmp_combo_usb_power_on(phy); 2032 if (ret) 2033 qmp_combo_com_exit(qmp); 2034 2035 return ret; 2036 } 2037 2038 static int qmp_combo_usb_exit(struct phy *phy) 2039 { 2040 struct qmp_combo *qmp = phy_get_drvdata(phy); 2041 int ret; 2042 2043 ret = qmp_combo_usb_power_off(phy); 2044 if (ret) 2045 return ret; 2046 2047 return qmp_combo_com_exit(qmp); 2048 } 2049 2050 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2051 { 2052 struct qmp_combo *qmp = phy_get_drvdata(phy); 2053 2054 qmp->mode = mode; 2055 2056 return 0; 2057 } 2058 2059 static const struct phy_ops qmp_combo_usb_phy_ops = { 2060 .init = qmp_combo_usb_init, 2061 .exit = qmp_combo_usb_exit, 2062 .set_mode = qmp_combo_usb_set_mode, 2063 .owner = THIS_MODULE, 2064 }; 2065 2066 static const struct phy_ops qmp_combo_dp_phy_ops = { 2067 .init = qmp_combo_dp_init, 2068 .configure = qmp_combo_dp_configure, 2069 .power_on = qmp_combo_dp_power_on, 2070 .calibrate = qmp_combo_dp_calibrate, 2071 .power_off = qmp_combo_dp_power_off, 2072 .exit = qmp_combo_dp_exit, 2073 .owner = THIS_MODULE, 2074 }; 2075 2076 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2077 { 2078 const struct qmp_phy_cfg *cfg = qmp->cfg; 2079 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2080 void __iomem *pcs_misc = qmp->pcs_misc; 2081 u32 intr_mask; 2082 2083 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2084 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2085 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2086 else 2087 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2088 2089 /* Clear any pending interrupts status */ 2090 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2091 /* Writing 1 followed by 0 clears the interrupt */ 2092 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2093 2094 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2095 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2096 2097 /* Enable required PHY autonomous mode interrupts */ 2098 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2099 2100 /* Enable i/o clamp_n for autonomous mode */ 2101 if (pcs_misc) 2102 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2103 } 2104 2105 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2106 { 2107 const struct qmp_phy_cfg *cfg = qmp->cfg; 2108 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2109 void __iomem *pcs_misc = qmp->pcs_misc; 2110 2111 /* Disable i/o clamp_n on resume for normal mode */ 2112 if (pcs_misc) 2113 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2114 2115 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2116 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2117 2118 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2119 /* Writing 1 followed by 0 clears the interrupt */ 2120 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2121 } 2122 2123 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2124 { 2125 struct qmp_combo *qmp = dev_get_drvdata(dev); 2126 const struct qmp_phy_cfg *cfg = qmp->cfg; 2127 2128 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2129 2130 if (!qmp->init_count) { 2131 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2132 return 0; 2133 } 2134 2135 qmp_combo_enable_autonomous_mode(qmp); 2136 2137 clk_disable_unprepare(qmp->pipe_clk); 2138 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2139 2140 return 0; 2141 } 2142 2143 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2144 { 2145 struct qmp_combo *qmp = dev_get_drvdata(dev); 2146 const struct qmp_phy_cfg *cfg = qmp->cfg; 2147 int ret = 0; 2148 2149 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2150 2151 if (!qmp->init_count) { 2152 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2153 return 0; 2154 } 2155 2156 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2157 if (ret) 2158 return ret; 2159 2160 ret = clk_prepare_enable(qmp->pipe_clk); 2161 if (ret) { 2162 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2163 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2164 return ret; 2165 } 2166 2167 qmp_combo_disable_autonomous_mode(qmp); 2168 2169 return 0; 2170 } 2171 2172 static const struct dev_pm_ops qmp_combo_pm_ops = { 2173 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2174 qmp_combo_runtime_resume, NULL) 2175 }; 2176 2177 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2178 { 2179 const struct qmp_phy_cfg *cfg = qmp->cfg; 2180 struct device *dev = qmp->dev; 2181 int num = cfg->num_vregs; 2182 int ret, i; 2183 2184 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2185 if (!qmp->vregs) 2186 return -ENOMEM; 2187 2188 for (i = 0; i < num; i++) 2189 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2190 2191 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2192 if (ret) { 2193 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2194 return ret; 2195 } 2196 2197 for (i = 0; i < num; i++) { 2198 ret = regulator_set_load(qmp->vregs[i].consumer, 2199 cfg->vreg_list[i].enable_load); 2200 if (ret) { 2201 dev_err(dev, "failed to set load at %s\n", 2202 qmp->vregs[i].supply); 2203 return ret; 2204 } 2205 } 2206 2207 return 0; 2208 } 2209 2210 static int qmp_combo_reset_init(struct qmp_combo *qmp) 2211 { 2212 const struct qmp_phy_cfg *cfg = qmp->cfg; 2213 struct device *dev = qmp->dev; 2214 int i; 2215 int ret; 2216 2217 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2218 sizeof(*qmp->resets), GFP_KERNEL); 2219 if (!qmp->resets) 2220 return -ENOMEM; 2221 2222 for (i = 0; i < cfg->num_resets; i++) 2223 qmp->resets[i].id = cfg->reset_list[i]; 2224 2225 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2226 if (ret) 2227 return dev_err_probe(dev, ret, "failed to get resets\n"); 2228 2229 return 0; 2230 } 2231 2232 static int qmp_combo_clk_init(struct qmp_combo *qmp) 2233 { 2234 const struct qmp_phy_cfg *cfg = qmp->cfg; 2235 struct device *dev = qmp->dev; 2236 int num = cfg->num_clks; 2237 int i; 2238 2239 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2240 if (!qmp->clks) 2241 return -ENOMEM; 2242 2243 for (i = 0; i < num; i++) 2244 qmp->clks[i].id = cfg->clk_list[i]; 2245 2246 return devm_clk_bulk_get(dev, num, qmp->clks); 2247 } 2248 2249 static void phy_clk_release_provider(void *res) 2250 { 2251 of_clk_del_provider(res); 2252 } 2253 2254 /* 2255 * Register a fixed rate pipe clock. 2256 * 2257 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2258 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2259 * by the PHY driver for its operations. 2260 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2261 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2262 * Below picture shows this relationship. 2263 * 2264 * +---------------+ 2265 * | PHY block |<<---------------------------------------+ 2266 * | | | 2267 * | +-------+ | +-----+ | 2268 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2269 * clk | +-------+ | +-----+ 2270 * +---------------+ 2271 */ 2272 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 2273 { 2274 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2275 struct clk_init_data init = { }; 2276 char name[64]; 2277 2278 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 2279 init.name = name; 2280 init.ops = &clk_fixed_rate_ops; 2281 2282 /* controllers using QMP phys use 125MHz pipe clock interface */ 2283 fixed->fixed_rate = 125000000; 2284 fixed->hw.init = &init; 2285 2286 return devm_clk_hw_register(qmp->dev, &fixed->hw); 2287 } 2288 2289 /* 2290 * Display Port PLL driver block diagram for branch clocks 2291 * 2292 * +------------------------------+ 2293 * | DP_VCO_CLK | 2294 * | | 2295 * | +-------------------+ | 2296 * | | (DP PLL/VCO) | | 2297 * | +---------+---------+ | 2298 * | v | 2299 * | +----------+-----------+ | 2300 * | | hsclk_divsel_clk_src | | 2301 * | +----------+-----------+ | 2302 * +------------------------------+ 2303 * | 2304 * +---------<---------v------------>----------+ 2305 * | | 2306 * +--------v----------------+ | 2307 * | dp_phy_pll_link_clk | | 2308 * | link_clk | | 2309 * +--------+----------------+ | 2310 * | | 2311 * | | 2312 * v v 2313 * Input to DISPCC block | 2314 * for link clk, crypto clk | 2315 * and interface clock | 2316 * | 2317 * | 2318 * +--------<------------+-----------------+---<---+ 2319 * | | | 2320 * +----v---------+ +--------v-----+ +--------v------+ 2321 * | vco_divided | | vco_divided | | vco_divided | 2322 * | _clk_src | | _clk_src | | _clk_src | 2323 * | | | | | | 2324 * |divsel_six | | divsel_two | | divsel_four | 2325 * +-------+------+ +-----+--------+ +--------+------+ 2326 * | | | 2327 * v---->----------v-------------<------v 2328 * | 2329 * +----------+-----------------+ 2330 * | dp_phy_pll_vco_div_clk | 2331 * +---------+------------------+ 2332 * | 2333 * v 2334 * Input to DISPCC block 2335 * for DP pixel clock 2336 * 2337 */ 2338 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2339 { 2340 switch (req->rate) { 2341 case 1620000000UL / 2: 2342 case 2700000000UL / 2: 2343 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2344 return 0; 2345 default: 2346 return -EINVAL; 2347 } 2348 } 2349 2350 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2351 { 2352 const struct qmp_combo *qmp; 2353 const struct phy_configure_opts_dp *dp_opts; 2354 2355 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 2356 dp_opts = &qmp->dp_opts; 2357 2358 switch (dp_opts->link_rate) { 2359 case 1620: 2360 return 1620000000UL / 2; 2361 case 2700: 2362 return 2700000000UL / 2; 2363 case 5400: 2364 return 5400000000UL / 4; 2365 case 8100: 2366 return 8100000000UL / 6; 2367 default: 2368 return 0; 2369 } 2370 } 2371 2372 static const struct clk_ops qmp_dp_pixel_clk_ops = { 2373 .determine_rate = qmp_dp_pixel_clk_determine_rate, 2374 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 2375 }; 2376 2377 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2378 { 2379 switch (req->rate) { 2380 case 162000000: 2381 case 270000000: 2382 case 540000000: 2383 case 810000000: 2384 return 0; 2385 default: 2386 return -EINVAL; 2387 } 2388 } 2389 2390 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2391 { 2392 const struct qmp_combo *qmp; 2393 const struct phy_configure_opts_dp *dp_opts; 2394 2395 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 2396 dp_opts = &qmp->dp_opts; 2397 2398 switch (dp_opts->link_rate) { 2399 case 1620: 2400 case 2700: 2401 case 5400: 2402 case 8100: 2403 return dp_opts->link_rate * 100000; 2404 default: 2405 return 0; 2406 } 2407 } 2408 2409 static const struct clk_ops qmp_dp_link_clk_ops = { 2410 .determine_rate = qmp_dp_link_clk_determine_rate, 2411 .recalc_rate = qmp_dp_link_clk_recalc_rate, 2412 }; 2413 2414 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 2415 { 2416 struct qmp_combo *qmp = data; 2417 unsigned int idx = clkspec->args[0]; 2418 2419 if (idx >= 2) { 2420 pr_err("%s: invalid index %u\n", __func__, idx); 2421 return ERR_PTR(-EINVAL); 2422 } 2423 2424 if (idx == 0) 2425 return &qmp->dp_link_hw; 2426 2427 return &qmp->dp_pixel_hw; 2428 } 2429 2430 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 2431 { 2432 struct clk_init_data init = { }; 2433 char name[64]; 2434 int ret; 2435 2436 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 2437 init.ops = &qmp_dp_link_clk_ops; 2438 init.name = name; 2439 qmp->dp_link_hw.init = &init; 2440 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 2441 if (ret) 2442 return ret; 2443 2444 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 2445 init.ops = &qmp_dp_pixel_clk_ops; 2446 init.name = name; 2447 qmp->dp_pixel_hw.init = &init; 2448 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 2449 if (ret) 2450 return ret; 2451 2452 return 0; 2453 } 2454 2455 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 2456 { 2457 struct qmp_combo *qmp = data; 2458 2459 switch (clkspec->args[0]) { 2460 case QMP_USB43DP_USB3_PIPE_CLK: 2461 return &qmp->pipe_clk_fixed.hw; 2462 case QMP_USB43DP_DP_LINK_CLK: 2463 return &qmp->dp_link_hw; 2464 case QMP_USB43DP_DP_VCO_DIV_CLK: 2465 return &qmp->dp_pixel_hw; 2466 } 2467 2468 return ERR_PTR(-EINVAL); 2469 } 2470 2471 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 2472 struct device_node *dp_np) 2473 { 2474 int ret; 2475 2476 ret = phy_pipe_clk_register(qmp, usb_np); 2477 if (ret) 2478 return ret; 2479 2480 ret = phy_dp_clks_register(qmp, dp_np); 2481 if (ret) 2482 return ret; 2483 2484 /* 2485 * Register a single provider for bindings without child nodes. 2486 */ 2487 if (usb_np == qmp->dev->of_node) 2488 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 2489 2490 /* 2491 * Register multiple providers for legacy bindings with child nodes. 2492 */ 2493 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 2494 &qmp->pipe_clk_fixed.hw); 2495 if (ret) 2496 return ret; 2497 2498 /* 2499 * Roll a devm action because the clock provider is the child node, but 2500 * the child node is not actually a device. 2501 */ 2502 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 2503 if (ret) 2504 return ret; 2505 2506 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 2507 if (ret) 2508 return ret; 2509 2510 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 2511 } 2512 2513 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 2514 { 2515 struct device *dev = qmp->dev; 2516 2517 /* 2518 * Get memory resources from the DP child node: 2519 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 2520 * tx2 -> 3; rx2 -> 4 2521 * 2522 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 2523 * implementation. 2524 */ 2525 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 2526 if (IS_ERR(qmp->dp_tx)) 2527 return PTR_ERR(qmp->dp_tx); 2528 2529 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 2530 if (IS_ERR(qmp->dp_dp_phy)) 2531 return PTR_ERR(qmp->dp_dp_phy); 2532 2533 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 2534 if (IS_ERR(qmp->dp_tx2)) 2535 return PTR_ERR(qmp->dp_tx2); 2536 2537 return 0; 2538 } 2539 2540 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 2541 { 2542 const struct qmp_phy_cfg *cfg = qmp->cfg; 2543 struct device *dev = qmp->dev; 2544 2545 /* 2546 * Get memory resources from the USB child node: 2547 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 2548 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 2549 */ 2550 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2551 if (IS_ERR(qmp->tx)) 2552 return PTR_ERR(qmp->tx); 2553 2554 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2555 if (IS_ERR(qmp->rx)) 2556 return PTR_ERR(qmp->rx); 2557 2558 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2559 if (IS_ERR(qmp->pcs)) 2560 return PTR_ERR(qmp->pcs); 2561 2562 if (cfg->pcs_usb_offset) 2563 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2564 2565 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2566 if (IS_ERR(qmp->tx2)) 2567 return PTR_ERR(qmp->tx2); 2568 2569 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2570 if (IS_ERR(qmp->rx2)) 2571 return PTR_ERR(qmp->rx2); 2572 2573 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2574 if (IS_ERR(qmp->pcs_misc)) { 2575 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2576 qmp->pcs_misc = NULL; 2577 } 2578 2579 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2580 if (IS_ERR(qmp->pipe_clk)) { 2581 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2582 "failed to get pipe clock\n"); 2583 } 2584 2585 return 0; 2586 } 2587 2588 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 2589 struct device_node *dp_np) 2590 { 2591 struct platform_device *pdev = to_platform_device(qmp->dev); 2592 int ret; 2593 2594 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2595 if (IS_ERR(qmp->serdes)) 2596 return PTR_ERR(qmp->serdes); 2597 2598 qmp->com = devm_platform_ioremap_resource(pdev, 1); 2599 if (IS_ERR(qmp->com)) 2600 return PTR_ERR(qmp->com); 2601 2602 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 2603 if (IS_ERR(qmp->dp_serdes)) 2604 return PTR_ERR(qmp->dp_serdes); 2605 2606 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 2607 if (ret) 2608 return ret; 2609 2610 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 2611 if (ret) 2612 return ret; 2613 2614 return 0; 2615 } 2616 2617 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 2618 { 2619 struct platform_device *pdev = to_platform_device(qmp->dev); 2620 const struct qmp_phy_cfg *cfg = qmp->cfg; 2621 const struct qmp_combo_offsets *offs = cfg->offsets; 2622 struct device *dev = qmp->dev; 2623 void __iomem *base; 2624 2625 if (!offs) 2626 return -EINVAL; 2627 2628 base = devm_platform_ioremap_resource(pdev, 0); 2629 if (IS_ERR(base)) 2630 return PTR_ERR(base); 2631 2632 qmp->com = base + offs->com; 2633 qmp->tx = base + offs->txa; 2634 qmp->rx = base + offs->rxa; 2635 qmp->tx2 = base + offs->txb; 2636 qmp->rx2 = base + offs->rxb; 2637 2638 qmp->serdes = base + offs->usb3_serdes; 2639 qmp->pcs_misc = base + offs->usb3_pcs_misc; 2640 qmp->pcs = base + offs->usb3_pcs; 2641 qmp->pcs_usb = base + offs->usb3_pcs_usb; 2642 2643 qmp->dp_serdes = base + offs->dp_serdes; 2644 qmp->dp_tx = base + offs->txa; 2645 qmp->dp_tx2 = base + offs->txb; 2646 qmp->dp_dp_phy = base + offs->dp_dp_phy; 2647 2648 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 2649 if (IS_ERR(qmp->pipe_clk)) { 2650 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2651 "failed to get usb3_pipe clock\n"); 2652 } 2653 2654 return 0; 2655 } 2656 2657 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args) 2658 { 2659 struct qmp_combo *qmp = dev_get_drvdata(dev); 2660 2661 if (args->args_count == 0) 2662 return ERR_PTR(-EINVAL); 2663 2664 switch (args->args[0]) { 2665 case QMP_USB43DP_USB3_PHY: 2666 return qmp->usb_phy; 2667 case QMP_USB43DP_DP_PHY: 2668 return qmp->dp_phy; 2669 } 2670 2671 return ERR_PTR(-EINVAL); 2672 } 2673 2674 static int qmp_combo_probe(struct platform_device *pdev) 2675 { 2676 struct qmp_combo *qmp; 2677 struct device *dev = &pdev->dev; 2678 struct device_node *dp_np, *usb_np; 2679 struct phy_provider *phy_provider; 2680 int ret; 2681 2682 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2683 if (!qmp) 2684 return -ENOMEM; 2685 2686 qmp->dev = dev; 2687 2688 qmp->cfg = of_device_get_match_data(dev); 2689 if (!qmp->cfg) 2690 return -EINVAL; 2691 2692 mutex_init(&qmp->phy_mutex); 2693 2694 ret = qmp_combo_clk_init(qmp); 2695 if (ret) 2696 return ret; 2697 2698 ret = qmp_combo_reset_init(qmp); 2699 if (ret) 2700 return ret; 2701 2702 ret = qmp_combo_vreg_init(qmp); 2703 if (ret) 2704 return ret; 2705 2706 /* Check for legacy binding with child nodes. */ 2707 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 2708 if (usb_np) { 2709 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 2710 if (!dp_np) { 2711 of_node_put(usb_np); 2712 return -EINVAL; 2713 } 2714 2715 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 2716 } else { 2717 usb_np = of_node_get(dev->of_node); 2718 dp_np = of_node_get(dev->of_node); 2719 2720 ret = qmp_combo_parse_dt(qmp); 2721 } 2722 if (ret) 2723 goto err_node_put; 2724 2725 pm_runtime_set_active(dev); 2726 ret = devm_pm_runtime_enable(dev); 2727 if (ret) 2728 goto err_node_put; 2729 /* 2730 * Prevent runtime pm from being ON by default. Users can enable 2731 * it using power/control in sysfs. 2732 */ 2733 pm_runtime_forbid(dev); 2734 2735 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 2736 if (ret) 2737 goto err_node_put; 2738 2739 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 2740 if (IS_ERR(qmp->usb_phy)) { 2741 ret = PTR_ERR(qmp->usb_phy); 2742 dev_err(dev, "failed to create USB PHY: %d\n", ret); 2743 goto err_node_put; 2744 } 2745 2746 phy_set_drvdata(qmp->usb_phy, qmp); 2747 2748 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 2749 if (IS_ERR(qmp->dp_phy)) { 2750 ret = PTR_ERR(qmp->dp_phy); 2751 dev_err(dev, "failed to create DP PHY: %d\n", ret); 2752 goto err_node_put; 2753 } 2754 2755 phy_set_drvdata(qmp->dp_phy, qmp); 2756 2757 dev_set_drvdata(dev, qmp); 2758 2759 if (usb_np == dev->of_node) 2760 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 2761 else 2762 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2763 2764 of_node_put(usb_np); 2765 of_node_put(dp_np); 2766 2767 return PTR_ERR_OR_ZERO(phy_provider); 2768 2769 err_node_put: 2770 of_node_put(usb_np); 2771 of_node_put(dp_np); 2772 return ret; 2773 } 2774 2775 static const struct of_device_id qmp_combo_of_match_table[] = { 2776 { 2777 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 2778 .data = &sc7180_usb3dpphy_cfg, 2779 }, 2780 { 2781 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 2782 .data = &sc8180x_usb3dpphy_cfg, 2783 }, 2784 { 2785 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 2786 .data = &sc8280xp_usb43dpphy_cfg, 2787 }, 2788 { 2789 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 2790 .data = &sdm845_usb3dpphy_cfg, 2791 }, 2792 { 2793 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 2794 .data = &sm8250_usb3dpphy_cfg, 2795 }, 2796 { } 2797 }; 2798 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 2799 2800 static struct platform_driver qmp_combo_driver = { 2801 .probe = qmp_combo_probe, 2802 .driver = { 2803 .name = "qcom-qmp-combo-phy", 2804 .pm = &qmp_combo_pm_ops, 2805 .of_match_table = qmp_combo_of_match_table, 2806 }, 2807 }; 2808 2809 module_platform_driver(qmp_combo_driver); 2810 2811 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2812 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 2813 MODULE_LICENSE("GPL v2"); 2814