1 /* 2 * AppliedMicro X-Gene Multi-purpose PHY driver 3 * 4 * Copyright (c) 2014, Applied Micro Circuits Corporation 5 * Author: Loc Ho <lho@apm.com> 6 * Tuan Phan <tphan@apm.com> 7 * Suman Tripathi <stripathi@apm.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 * 22 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes. 23 * The first PLL clock macro is used for internal reference clock. The second 24 * PLL clock macro is used to generate the clock for the PHY. This driver 25 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to 26 * operate according to the mode of operation. The first PLL CMU is only 27 * required if internal clock is enabled. 28 * 29 * Logical Layer Out Of HW module units: 30 * 31 * ----------------- 32 * | Internal | |------| 33 * | Ref PLL CMU |----| | ------------- --------- 34 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes| 35 * | | | | --------- 36 * External Clock ------| | ------------- 37 * |------| 38 * 39 * The Ref PLL CMU CSR (Configuration System Registers) is accessed 40 * indirectly from the SDS offset at 0x2000. It is only required for 41 * internal reference clock. 42 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000. 43 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400. 44 * 45 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP 46 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP, 47 * it is located outside the PHY IP. This is the case for the PHY located 48 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required 49 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled. 50 * 51 * Currently, this driver only supports Gen3 SATA mode with external clock. 52 */ 53 #include <linux/module.h> 54 #include <linux/platform_device.h> 55 #include <linux/io.h> 56 #include <linux/delay.h> 57 #include <linux/phy/phy.h> 58 #include <linux/clk.h> 59 60 /* Max 2 lanes per a PHY unit */ 61 #define MAX_LANE 2 62 63 /* Register offset inside the PHY */ 64 #define SERDES_PLL_INDIRECT_OFFSET 0x0000 65 #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000 66 #define SERDES_INDIRECT_OFFSET 0x0400 67 #define SERDES_LANE_STRIDE 0x0200 68 69 /* Some default Serdes parameters */ 70 #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e } 71 #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 } 72 #define DEFAULT_SATA_TXEYETUNING { 0xa, 0xa, 0xa } 73 #define DEFAULT_SATA_SPD_SEL { 0x1, 0x3, 0x7 } 74 #define DEFAULT_SATA_TXAMP { 0x8, 0x8, 0x8 } 75 #define DEFAULT_SATA_TXCN1 { 0x2, 0x2, 0x2 } 76 #define DEFAULT_SATA_TXCN2 { 0x0, 0x0, 0x0 } 77 #define DEFAULT_SATA_TXCP1 { 0xa, 0xa, 0xa } 78 79 #define SATA_SPD_SEL_GEN3 0x7 80 #define SATA_SPD_SEL_GEN2 0x3 81 #define SATA_SPD_SEL_GEN1 0x1 82 83 #define SSC_DISABLE 0 84 #define SSC_ENABLE 1 85 86 #define FBDIV_VAL_50M 0x77 87 #define REFDIV_VAL_50M 0x1 88 #define FBDIV_VAL_100M 0x3B 89 #define REFDIV_VAL_100M 0x0 90 91 /* SATA Clock/Reset CSR */ 92 #define SATACLKENREG 0x00000000 93 #define SATA0_CORE_CLKEN 0x00000002 94 #define SATA1_CORE_CLKEN 0x00000004 95 #define SATASRESETREG 0x00000004 96 #define SATA_MEM_RESET_MASK 0x00000020 97 #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5) 98 #define SATA_SDS_RESET_MASK 0x00000004 99 #define SATA_CSR_RESET_MASK 0x00000001 100 #define SATA_CORE_RESET_MASK 0x00000002 101 #define SATA_PMCLK_RESET_MASK 0x00000010 102 #define SATA_PCLK_RESET_MASK 0x00000008 103 104 /* SDS CSR used for PHY Indirect access */ 105 #define SATA_ENET_SDS_PCS_CTL0 0x00000000 106 #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ 107 (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000)) 108 #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ 109 (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000)) 110 #define SATA_ENET_SDS_CTL0 0x0000000c 111 #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ 112 (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff)) 113 #define SATA_ENET_SDS_CTL1 0x00000010 114 #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ 115 (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f)) 116 #define SATA_ENET_SDS_RST_CTL 0x00000024 117 #define SATA_ENET_SDS_IND_CMD_REG 0x0000003c 118 #define CFG_IND_WR_CMD_MASK 0x00000001 119 #define CFG_IND_RD_CMD_MASK 0x00000002 120 #define CFG_IND_CMD_DONE_MASK 0x00000004 121 #define CFG_IND_ADDR_SET(dst, src) \ 122 (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0)) 123 #define SATA_ENET_SDS_IND_RDATA_REG 0x00000040 124 #define SATA_ENET_SDS_IND_WDATA_REG 0x00000044 125 #define SATA_ENET_CLK_MACRO_REG 0x0000004c 126 #define I_RESET_B_SET(dst, src) \ 127 (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001)) 128 #define I_PLL_FBDIV_SET(dst, src) \ 129 (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000)) 130 #define I_CUSTOMEROV_SET(dst, src) \ 131 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80)) 132 #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30) 133 #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31) 134 135 /* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */ 136 #define CMU_REG0 0x00000 137 #define CMU_REG0_PLL_REF_SEL_MASK 0x00002000 138 #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \ 139 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000)) 140 #define CMU_REG0_PDOWN_MASK 0x00004000 141 #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \ 142 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0)) 143 #define CMU_REG1 0x00002 144 #define CMU_REG1_PLL_CP_SET(dst, src) \ 145 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00)) 146 #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \ 147 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) 148 #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \ 149 (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0)) 150 #define CMU_REG1_REFCLK_CMOS_SEL_MASK 0x00000001 151 #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \ 152 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) 153 #define CMU_REG2 0x00004 154 #define CMU_REG2_PLL_REFDIV_SET(dst, src) \ 155 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) 156 #define CMU_REG2_PLL_LFRES_SET(dst, src) \ 157 (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e)) 158 #define CMU_REG2_PLL_FBDIV_SET(dst, src) \ 159 (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0)) 160 #define CMU_REG3 0x00006 161 #define CMU_REG3_VCOVARSEL_SET(dst, src) \ 162 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f)) 163 #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \ 164 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) 165 #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \ 166 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) 167 #define CMU_REG4 0x00008 168 #define CMU_REG5 0x0000a 169 #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \ 170 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) 171 #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \ 172 (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e)) 173 #define CMU_REG5_PLL_LFCAP_SET(dst, src) \ 174 (((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000)) 175 #define CMU_REG5_PLL_RESETB_MASK 0x00000001 176 #define CMU_REG6 0x0000c 177 #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \ 178 (((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600)) 179 #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \ 180 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) 181 #define CMU_REG7 0x0000e 182 #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14) 183 #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10) 184 #define CMU_REG8 0x00010 185 #define CMU_REG9 0x00012 186 #define CMU_REG9_WORD_LEN_8BIT 0x000 187 #define CMU_REG9_WORD_LEN_10BIT 0x001 188 #define CMU_REG9_WORD_LEN_16BIT 0x002 189 #define CMU_REG9_WORD_LEN_20BIT 0x003 190 #define CMU_REG9_WORD_LEN_32BIT 0x004 191 #define CMU_REG9_WORD_LEN_40BIT 0x005 192 #define CMU_REG9_WORD_LEN_64BIT 0x006 193 #define CMU_REG9_WORD_LEN_66BIT 0x007 194 #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \ 195 (((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380)) 196 #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \ 197 (((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070)) 198 #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \ 199 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) 200 #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \ 201 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) 202 #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \ 203 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) 204 #define CMU_REG10 0x00014 205 #define CMU_REG10_VREG_REFSEL_SET(dst, src) \ 206 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) 207 #define CMU_REG11 0x00016 208 #define CMU_REG12 0x00018 209 #define CMU_REG12_STATE_DELAY9_SET(dst, src) \ 210 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0)) 211 #define CMU_REG13 0x0001a 212 #define CMU_REG14 0x0001c 213 #define CMU_REG15 0x0001e 214 #define CMU_REG16 0x00020 215 #define CMU_REG16_PVT_DN_MAN_ENA_MASK 0x00000001 216 #define CMU_REG16_PVT_UP_MAN_ENA_MASK 0x00000002 217 #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \ 218 (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c)) 219 #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \ 220 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) 221 #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \ 222 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020)) 223 #define CMU_REG17 0x00022 224 #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \ 225 (((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00)) 226 #define CMU_REG17_RESERVED_7_SET(dst, src) \ 227 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0)) 228 #define CMU_REG17_PVT_TERM_MAN_ENA_MASK 0x00008000 229 #define CMU_REG18 0x00024 230 #define CMU_REG19 0x00026 231 #define CMU_REG20 0x00028 232 #define CMU_REG21 0x0002a 233 #define CMU_REG22 0x0002c 234 #define CMU_REG23 0x0002e 235 #define CMU_REG24 0x00030 236 #define CMU_REG25 0x00032 237 #define CMU_REG26 0x00034 238 #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \ 239 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) 240 #define CMU_REG27 0x00036 241 #define CMU_REG28 0x00038 242 #define CMU_REG29 0x0003a 243 #define CMU_REG30 0x0003c 244 #define CMU_REG30_LOCK_COUNT_SET(dst, src) \ 245 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006)) 246 #define CMU_REG30_PCIE_MODE_SET(dst, src) \ 247 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) 248 #define CMU_REG31 0x0003e 249 #define CMU_REG32 0x00040 250 #define CMU_REG32_FORCE_VCOCAL_START_MASK 0x00004000 251 #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \ 252 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006)) 253 #define CMU_REG32_IREF_ADJ_SET(dst, src) \ 254 (((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180)) 255 #define CMU_REG33 0x00042 256 #define CMU_REG34 0x00044 257 #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \ 258 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f)) 259 #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \ 260 (((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00)) 261 #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \ 262 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0)) 263 #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \ 264 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000)) 265 #define CMU_REG35 0x00046 266 #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \ 267 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00)) 268 #define CMU_REG36 0x00048 269 #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \ 270 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010)) 271 #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \ 272 (((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0)) 273 #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \ 274 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020)) 275 #define CMU_REG37 0x0004a 276 #define CMU_REG38 0x0004c 277 #define CMU_REG39 0x0004e 278 279 /* PHY lane CSR accessing from SDS indirectly */ 280 #define RXTX_REG0 0x000 281 #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \ 282 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) 283 #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \ 284 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) 285 #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \ 286 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) 287 #define RXTX_REG1 0x002 288 #define RXTX_REG1_RXACVCM_SET(dst, src) \ 289 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000)) 290 #define RXTX_REG1_CTLE_EQ_SET(dst, src) \ 291 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80)) 292 #define RXTX_REG1_RXVREG1_SET(dst, src) \ 293 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060)) 294 #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \ 295 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006)) 296 #define RXTX_REG2 0x004 297 #define RXTX_REG2_VTT_ENA_SET(dst, src) \ 298 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) 299 #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \ 300 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020)) 301 #define RXTX_REG2_VTT_SEL_SET(dst, src) \ 302 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0)) 303 #define RXTX_REG4 0x008 304 #define RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK 0x00000040 305 #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \ 306 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) 307 #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \ 308 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) 309 #define RXTX_REG5 0x00a 310 #define RXTX_REG5_TX_CN1_SET(dst, src) \ 311 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) 312 #define RXTX_REG5_TX_CP1_SET(dst, src) \ 313 (((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0)) 314 #define RXTX_REG5_TX_CN2_SET(dst, src) \ 315 (((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f)) 316 #define RXTX_REG6 0x00c 317 #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \ 318 (((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780)) 319 #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \ 320 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) 321 #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \ 322 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) 323 #define RXTX_REG6_TX_IDLE_SET(dst, src) \ 324 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) 325 #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \ 326 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) 327 #define RXTX_REG7 0x00e 328 #define RXTX_REG7_RESETB_RXD_MASK 0x00000100 329 #define RXTX_REG7_RESETB_RXA_MASK 0x00000080 330 #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \ 331 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) 332 #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \ 333 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) 334 #define RXTX_REG8 0x010 335 #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \ 336 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000)) 337 #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \ 338 (((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800)) 339 #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \ 340 (((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200)) 341 #define RXTX_REG8_SD_VREF_SET(dst, src) \ 342 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0)) 343 #define RXTX_REG8_SD_DISABLE_SET(dst, src) \ 344 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) 345 #define RXTX_REG7 0x00e 346 #define RXTX_REG7_RESETB_RXD_SET(dst, src) \ 347 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) 348 #define RXTX_REG7_RESETB_RXA_SET(dst, src) \ 349 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080)) 350 #define RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK 0x00004000 351 #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \ 352 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000)) 353 #define RXTX_REG11 0x016 354 #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \ 355 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) 356 #define RXTX_REG12 0x018 357 #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \ 358 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000)) 359 #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \ 360 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) 361 #define RXTX_REG12_RX_DET_TERM_ENABLE_MASK 0x00000002 362 #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \ 363 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) 364 #define RXTX_REG13 0x01a 365 #define RXTX_REG14 0x01c 366 #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \ 367 (((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f)) 368 #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \ 369 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) 370 #define RXTX_REG26 0x034 371 #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \ 372 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) 373 #define RXTX_REG26_BLWC_ENA_SET(dst, src) \ 374 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) 375 #define RXTX_REG21 0x02a 376 #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) 377 #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) 378 #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src))) 379 #define RXTX_REG22 0x02c 380 #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) 381 #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) 382 #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src))) 383 #define RXTX_REG23 0x02e 384 #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) 385 #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) 386 #define RXTX_REG24 0x030 387 #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) 388 #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) 389 #define RXTX_REG27 0x036 390 #define RXTX_REG28 0x038 391 #define RXTX_REG31 0x03e 392 #define RXTX_REG38 0x04c 393 #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \ 394 (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe)) 395 #define RXTX_REG39 0x04e 396 #define RXTX_REG40 0x050 397 #define RXTX_REG41 0x052 398 #define RXTX_REG42 0x054 399 #define RXTX_REG43 0x056 400 #define RXTX_REG44 0x058 401 #define RXTX_REG45 0x05a 402 #define RXTX_REG46 0x05c 403 #define RXTX_REG47 0x05e 404 #define RXTX_REG48 0x060 405 #define RXTX_REG49 0x062 406 #define RXTX_REG50 0x064 407 #define RXTX_REG51 0x066 408 #define RXTX_REG52 0x068 409 #define RXTX_REG53 0x06a 410 #define RXTX_REG54 0x06c 411 #define RXTX_REG55 0x06e 412 #define RXTX_REG61 0x07a 413 #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \ 414 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010)) 415 #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \ 416 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) 417 #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \ 418 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0)) 419 #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \ 420 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00)) 421 #define RXTX_REG62 0x07c 422 #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \ 423 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) 424 #define RXTX_REG81 0x0a2 425 #define RXTX_REG89_MU_TH7_SET(dst, src) \ 426 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) 427 #define RXTX_REG89_MU_TH8_SET(dst, src) \ 428 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) 429 #define RXTX_REG89_MU_TH9_SET(dst, src) \ 430 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) 431 #define RXTX_REG96 0x0c0 432 #define RXTX_REG96_MU_FREQ1_SET(dst, src) \ 433 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) 434 #define RXTX_REG96_MU_FREQ2_SET(dst, src) \ 435 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) 436 #define RXTX_REG96_MU_FREQ3_SET(dst, src) \ 437 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) 438 #define RXTX_REG99 0x0c6 439 #define RXTX_REG99_MU_PHASE1_SET(dst, src) \ 440 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) 441 #define RXTX_REG99_MU_PHASE2_SET(dst, src) \ 442 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) 443 #define RXTX_REG99_MU_PHASE3_SET(dst, src) \ 444 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) 445 #define RXTX_REG102 0x0cc 446 #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \ 447 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060)) 448 #define RXTX_REG114 0x0e4 449 #define RXTX_REG121 0x0f2 450 #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1) 451 #define RXTX_REG125 0x0fa 452 #define RXTX_REG125_PQ_REG_SET(dst, src) \ 453 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00)) 454 #define RXTX_REG125_SIGN_PQ_SET(dst, src) \ 455 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) 456 #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \ 457 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080)) 458 #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \ 459 (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c)) 460 #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \ 461 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) 462 #define RXTX_REG127 0x0fe 463 #define RXTX_REG127_FORCE_SUM_CAL_START_MASK 0x00000002 464 #define RXTX_REG127_FORCE_LAT_CAL_START_MASK 0x00000004 465 #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \ 466 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) 467 #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \ 468 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) 469 #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \ 470 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) 471 #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \ 472 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) 473 #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \ 474 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) 475 #define RXTX_REG128 0x100 476 #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \ 477 (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c)) 478 #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \ 479 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) 480 #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \ 481 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) 482 #define RXTX_REG129 0x102 483 #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \ 484 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) 485 #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \ 486 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) 487 #define RXTX_REG130 0x104 488 #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \ 489 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) 490 #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \ 491 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) 492 #define RXTX_REG145 0x122 493 #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \ 494 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) 495 #define RXTX_REG145_RXES_ENA_SET(dst, src) \ 496 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) 497 #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \ 498 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) 499 #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \ 500 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) 501 #define RXTX_REG147 0x126 502 #define RXTX_REG148 0x128 503 504 /* Clock macro type */ 505 enum cmu_type_t { 506 REF_CMU = 0, /* Clock macro is the internal reference clock */ 507 PHY_CMU = 1, /* Clock macro is the PLL for the Serdes */ 508 }; 509 510 enum mux_type_t { 511 MUX_SELECT_ATA = 0, /* Switch the MUX to ATA */ 512 MUX_SELECT_SGMMII = 0, /* Switch the MUX to SGMII */ 513 }; 514 515 enum clk_type_t { 516 CLK_EXT_DIFF = 0, /* External differential */ 517 CLK_INT_DIFF = 1, /* Internal differential */ 518 CLK_INT_SING = 2, /* Internal single ended */ 519 }; 520 521 enum xgene_phy_mode { 522 MODE_SATA = 0, /* List them for simple reference */ 523 MODE_SGMII = 1, 524 MODE_PCIE = 2, 525 MODE_USB = 3, 526 MODE_XFI = 4, 527 MODE_MAX 528 }; 529 530 struct xgene_sata_override_param { 531 u32 speed[MAX_LANE]; /* Index for override parameter per lane */ 532 u32 txspeed[3]; /* Tx speed */ 533 u32 txboostgain[MAX_LANE*3]; /* Tx freq boost and gain control */ 534 u32 txeyetuning[MAX_LANE*3]; /* Tx eye tuning */ 535 u32 txeyedirection[MAX_LANE*3]; /* Tx eye tuning direction */ 536 u32 txamplitude[MAX_LANE*3]; /* Tx amplitude control */ 537 u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */ 538 u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */ 539 u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */ 540 }; 541 542 struct xgene_phy_ctx { 543 struct device *dev; 544 struct phy *phy; 545 enum xgene_phy_mode mode; /* Mode of operation */ 546 enum clk_type_t clk_type; /* Input clock selection */ 547 void __iomem *sds_base; /* PHY CSR base addr */ 548 struct clk *clk; /* Optional clock */ 549 550 /* Override Serdes parameters */ 551 struct xgene_sata_override_param sata_param; 552 }; 553 554 /* 555 * For chip earlier than A3 version, enable this flag. 556 * To enable, pass boot argument phy_xgene.preA3Chip=1 557 */ 558 static int preA3Chip; 559 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)"); 560 module_param_named(preA3Chip, preA3Chip, int, 0444); 561 562 static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg, 563 u32 indirect_data_reg, u32 addr, u32 data) 564 { 565 unsigned long deadline = jiffies + HZ; 566 u32 val; 567 u32 cmd; 568 569 cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK; 570 cmd = CFG_IND_ADDR_SET(cmd, addr); 571 writel(data, csr_base + indirect_data_reg); 572 readl(csr_base + indirect_data_reg); /* Force a barrier */ 573 writel(cmd, csr_base + indirect_cmd_reg); 574 readl(csr_base + indirect_cmd_reg); /* Force a barrier */ 575 do { 576 val = readl(csr_base + indirect_cmd_reg); 577 } while (!(val & CFG_IND_CMD_DONE_MASK) && 578 time_before(jiffies, deadline)); 579 if (!(val & CFG_IND_CMD_DONE_MASK)) 580 pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", 581 csr_base + indirect_cmd_reg, addr, data); 582 } 583 584 static void sds_rd(void __iomem *csr_base, u32 indirect_cmd_reg, 585 u32 indirect_data_reg, u32 addr, u32 *data) 586 { 587 unsigned long deadline = jiffies + HZ; 588 u32 val; 589 u32 cmd; 590 591 cmd = CFG_IND_RD_CMD_MASK | CFG_IND_CMD_DONE_MASK; 592 cmd = CFG_IND_ADDR_SET(cmd, addr); 593 writel(cmd, csr_base + indirect_cmd_reg); 594 readl(csr_base + indirect_cmd_reg); /* Force a barrier */ 595 do { 596 val = readl(csr_base + indirect_cmd_reg); 597 } while (!(val & CFG_IND_CMD_DONE_MASK) && 598 time_before(jiffies, deadline)); 599 *data = readl(csr_base + indirect_data_reg); 600 if (!(val & CFG_IND_CMD_DONE_MASK)) 601 pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", 602 csr_base + indirect_cmd_reg, addr, *data); 603 } 604 605 static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, 606 u32 reg, u32 data) 607 { 608 void __iomem *sds_base = ctx->sds_base; 609 u32 val; 610 611 if (cmu_type == REF_CMU) 612 reg += SERDES_PLL_REF_INDIRECT_OFFSET; 613 else 614 reg += SERDES_PLL_INDIRECT_OFFSET; 615 sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG, 616 SATA_ENET_SDS_IND_WDATA_REG, reg, data); 617 sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, 618 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); 619 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); 620 } 621 622 static void cmu_rd(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, 623 u32 reg, u32 *data) 624 { 625 void __iomem *sds_base = ctx->sds_base; 626 627 if (cmu_type == REF_CMU) 628 reg += SERDES_PLL_REF_INDIRECT_OFFSET; 629 else 630 reg += SERDES_PLL_INDIRECT_OFFSET; 631 sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, 632 SATA_ENET_SDS_IND_RDATA_REG, reg, data); 633 pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data); 634 } 635 636 static void cmu_toggle1to0(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, 637 u32 reg, u32 bits) 638 { 639 u32 val; 640 641 cmu_rd(ctx, cmu_type, reg, &val); 642 val |= bits; 643 cmu_wr(ctx, cmu_type, reg, val); 644 cmu_rd(ctx, cmu_type, reg, &val); 645 val &= ~bits; 646 cmu_wr(ctx, cmu_type, reg, val); 647 } 648 649 static void cmu_clrbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, 650 u32 reg, u32 bits) 651 { 652 u32 val; 653 654 cmu_rd(ctx, cmu_type, reg, &val); 655 val &= ~bits; 656 cmu_wr(ctx, cmu_type, reg, val); 657 } 658 659 static void cmu_setbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, 660 u32 reg, u32 bits) 661 { 662 u32 val; 663 664 cmu_rd(ctx, cmu_type, reg, &val); 665 val |= bits; 666 cmu_wr(ctx, cmu_type, reg, val); 667 } 668 669 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) 670 { 671 void __iomem *sds_base = ctx->sds_base; 672 u32 val; 673 674 reg += SERDES_INDIRECT_OFFSET; 675 reg += lane * SERDES_LANE_STRIDE; 676 sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG, 677 SATA_ENET_SDS_IND_WDATA_REG, reg, data); 678 sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, 679 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); 680 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, 681 val); 682 } 683 684 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) 685 { 686 void __iomem *sds_base = ctx->sds_base; 687 688 reg += SERDES_INDIRECT_OFFSET; 689 reg += lane * SERDES_LANE_STRIDE; 690 sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, 691 SATA_ENET_SDS_IND_RDATA_REG, reg, data); 692 pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data); 693 } 694 695 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, 696 u32 bits) 697 { 698 u32 val; 699 700 serdes_rd(ctx, lane, reg, &val); 701 val &= ~bits; 702 serdes_wr(ctx, lane, reg, val); 703 } 704 705 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, 706 u32 bits) 707 { 708 u32 val; 709 710 serdes_rd(ctx, lane, reg, &val); 711 val |= bits; 712 serdes_wr(ctx, lane, reg, val); 713 } 714 715 static void xgene_phy_cfg_cmu_clk_type(struct xgene_phy_ctx *ctx, 716 enum cmu_type_t cmu_type, 717 enum clk_type_t clk_type) 718 { 719 u32 val; 720 721 /* Set the reset sequence delay for TX ready assertion */ 722 cmu_rd(ctx, cmu_type, CMU_REG12, &val); 723 val = CMU_REG12_STATE_DELAY9_SET(val, 0x1); 724 cmu_wr(ctx, cmu_type, CMU_REG12, val); 725 /* Set the programmable stage delays between various enable stages */ 726 cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222); 727 cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225); 728 729 /* Configure clock type */ 730 if (clk_type == CLK_EXT_DIFF) { 731 /* Select external clock mux */ 732 cmu_rd(ctx, cmu_type, CMU_REG0, &val); 733 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0); 734 cmu_wr(ctx, cmu_type, CMU_REG0, val); 735 /* Select CMOS as reference clock */ 736 cmu_rd(ctx, cmu_type, CMU_REG1, &val); 737 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); 738 cmu_wr(ctx, cmu_type, CMU_REG1, val); 739 dev_dbg(ctx->dev, "Set external reference clock\n"); 740 } else if (clk_type == CLK_INT_DIFF) { 741 /* Select internal clock mux */ 742 cmu_rd(ctx, cmu_type, CMU_REG0, &val); 743 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1); 744 cmu_wr(ctx, cmu_type, CMU_REG0, val); 745 /* Select CMOS as reference clock */ 746 cmu_rd(ctx, cmu_type, CMU_REG1, &val); 747 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); 748 cmu_wr(ctx, cmu_type, CMU_REG1, val); 749 dev_dbg(ctx->dev, "Set internal reference clock\n"); 750 } else if (clk_type == CLK_INT_SING) { 751 /* 752 * NOTE: This clock type is NOT support for controller 753 * whose internal clock shared in the PCIe controller 754 * 755 * Select internal clock mux 756 */ 757 cmu_rd(ctx, cmu_type, CMU_REG1, &val); 758 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); 759 cmu_wr(ctx, cmu_type, CMU_REG1, val); 760 /* Select CML as reference clock */ 761 cmu_rd(ctx, cmu_type, CMU_REG1, &val); 762 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); 763 cmu_wr(ctx, cmu_type, CMU_REG1, val); 764 dev_dbg(ctx->dev, 765 "Set internal single ended reference clock\n"); 766 } 767 } 768 769 static void xgene_phy_sata_cfg_cmu_core(struct xgene_phy_ctx *ctx, 770 enum cmu_type_t cmu_type, 771 enum clk_type_t clk_type) 772 { 773 u32 val; 774 int ref_100MHz; 775 776 if (cmu_type == REF_CMU) { 777 /* Set VCO calibration voltage threshold */ 778 cmu_rd(ctx, cmu_type, CMU_REG34, &val); 779 val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7); 780 val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc); 781 val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3); 782 val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8); 783 cmu_wr(ctx, cmu_type, CMU_REG34, val); 784 } 785 786 /* Set the VCO calibration counter */ 787 cmu_rd(ctx, cmu_type, CMU_REG0, &val); 788 if (cmu_type == REF_CMU || preA3Chip) 789 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4); 790 else 791 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7); 792 cmu_wr(ctx, cmu_type, CMU_REG0, val); 793 794 /* Configure PLL for calibration */ 795 cmu_rd(ctx, cmu_type, CMU_REG1, &val); 796 val = CMU_REG1_PLL_CP_SET(val, 0x1); 797 if (cmu_type == REF_CMU || preA3Chip) 798 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); 799 else 800 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); 801 if (cmu_type == REF_CMU) 802 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); 803 else 804 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1); 805 cmu_wr(ctx, cmu_type, CMU_REG1, val); 806 807 if (cmu_type != REF_CMU) 808 cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); 809 810 /* Configure the PLL for either 100MHz or 50MHz */ 811 cmu_rd(ctx, cmu_type, CMU_REG2, &val); 812 if (cmu_type == REF_CMU) { 813 val = CMU_REG2_PLL_LFRES_SET(val, 0xa); 814 ref_100MHz = 1; 815 } else { 816 val = CMU_REG2_PLL_LFRES_SET(val, 0x3); 817 if (clk_type == CLK_EXT_DIFF) 818 ref_100MHz = 0; 819 else 820 ref_100MHz = 1; 821 } 822 if (ref_100MHz) { 823 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M); 824 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M); 825 } else { 826 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M); 827 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M); 828 } 829 cmu_wr(ctx, cmu_type, CMU_REG2, val); 830 831 /* Configure the VCO */ 832 cmu_rd(ctx, cmu_type, CMU_REG3, &val); 833 if (cmu_type == REF_CMU) { 834 val = CMU_REG3_VCOVARSEL_SET(val, 0x3); 835 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10); 836 } else { 837 val = CMU_REG3_VCOVARSEL_SET(val, 0xF); 838 if (preA3Chip) 839 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15); 840 else 841 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a); 842 val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15); 843 } 844 cmu_wr(ctx, cmu_type, CMU_REG3, val); 845 846 /* Disable force PLL lock */ 847 cmu_rd(ctx, cmu_type, CMU_REG26, &val); 848 val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0); 849 cmu_wr(ctx, cmu_type, CMU_REG26, val); 850 851 /* Setup PLL loop filter */ 852 cmu_rd(ctx, cmu_type, CMU_REG5, &val); 853 val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3); 854 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); 855 if (cmu_type == REF_CMU || !preA3Chip) 856 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7); 857 else 858 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4); 859 cmu_wr(ctx, cmu_type, CMU_REG5, val); 860 861 /* Enable or disable manual calibration */ 862 cmu_rd(ctx, cmu_type, CMU_REG6, &val); 863 val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2); 864 val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0); 865 cmu_wr(ctx, cmu_type, CMU_REG6, val); 866 867 /* Configure lane for 20-bits */ 868 if (cmu_type == PHY_CMU) { 869 cmu_rd(ctx, cmu_type, CMU_REG9, &val); 870 val = CMU_REG9_TX_WORD_MODE_CH1_SET(val, 871 CMU_REG9_WORD_LEN_20BIT); 872 val = CMU_REG9_TX_WORD_MODE_CH0_SET(val, 873 CMU_REG9_WORD_LEN_20BIT); 874 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); 875 if (!preA3Chip) { 876 val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0); 877 val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0); 878 } 879 cmu_wr(ctx, cmu_type, CMU_REG9, val); 880 881 if (!preA3Chip) { 882 cmu_rd(ctx, cmu_type, CMU_REG10, &val); 883 val = CMU_REG10_VREG_REFSEL_SET(val, 0x1); 884 cmu_wr(ctx, cmu_type, CMU_REG10, val); 885 } 886 } 887 888 cmu_rd(ctx, cmu_type, CMU_REG16, &val); 889 val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1); 890 val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1); 891 if (cmu_type == REF_CMU || preA3Chip) 892 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4); 893 else 894 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); 895 cmu_wr(ctx, cmu_type, CMU_REG16, val); 896 897 /* Configure for SATA */ 898 cmu_rd(ctx, cmu_type, CMU_REG30, &val); 899 val = CMU_REG30_PCIE_MODE_SET(val, 0x0); 900 val = CMU_REG30_LOCK_COUNT_SET(val, 0x3); 901 cmu_wr(ctx, cmu_type, CMU_REG30, val); 902 903 /* Disable state machine bypass */ 904 cmu_wr(ctx, cmu_type, CMU_REG31, 0xF); 905 906 cmu_rd(ctx, cmu_type, CMU_REG32, &val); 907 val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3); 908 if (cmu_type == REF_CMU || preA3Chip) 909 val = CMU_REG32_IREF_ADJ_SET(val, 0x3); 910 else 911 val = CMU_REG32_IREF_ADJ_SET(val, 0x1); 912 cmu_wr(ctx, cmu_type, CMU_REG32, val); 913 914 /* Set VCO calibration threshold */ 915 if (cmu_type != REF_CMU && preA3Chip) 916 cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27); 917 else 918 cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c); 919 920 /* Set CTLE Override and override waiting from state machine */ 921 cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F); 922 } 923 924 static void xgene_phy_ssc_enable(struct xgene_phy_ctx *ctx, 925 enum cmu_type_t cmu_type) 926 { 927 u32 val; 928 929 /* Set SSC modulation value */ 930 cmu_rd(ctx, cmu_type, CMU_REG35, &val); 931 val = CMU_REG35_PLL_SSC_MOD_SET(val, 98); 932 cmu_wr(ctx, cmu_type, CMU_REG35, val); 933 934 /* Enable SSC, set vertical step and DSM value */ 935 cmu_rd(ctx, cmu_type, CMU_REG36, &val); 936 val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30); 937 val = CMU_REG36_PLL_SSC_EN_SET(val, 1); 938 val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1); 939 cmu_wr(ctx, cmu_type, CMU_REG36, val); 940 941 /* Reset the PLL */ 942 cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); 943 cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); 944 945 /* Force VCO calibration to restart */ 946 cmu_toggle1to0(ctx, cmu_type, CMU_REG32, 947 CMU_REG32_FORCE_VCOCAL_START_MASK); 948 } 949 950 static void xgene_phy_sata_cfg_lanes(struct xgene_phy_ctx *ctx) 951 { 952 u32 val; 953 u32 reg; 954 int i; 955 int lane; 956 957 for (lane = 0; lane < MAX_LANE; lane++) { 958 serdes_wr(ctx, lane, RXTX_REG147, 0x6); 959 960 /* Set boost control for quarter, half, and full rate */ 961 serdes_rd(ctx, lane, RXTX_REG0, &val); 962 val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10); 963 val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10); 964 val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10); 965 serdes_wr(ctx, lane, RXTX_REG0, val); 966 967 /* Set boost control value */ 968 serdes_rd(ctx, lane, RXTX_REG1, &val); 969 val = RXTX_REG1_RXACVCM_SET(val, 0x7); 970 val = RXTX_REG1_CTLE_EQ_SET(val, 971 ctx->sata_param.txboostgain[lane * 3 + 972 ctx->sata_param.speed[lane]]); 973 serdes_wr(ctx, lane, RXTX_REG1, val); 974 975 /* Latch VTT value based on the termination to ground and 976 enable TX FIFO */ 977 serdes_rd(ctx, lane, RXTX_REG2, &val); 978 val = RXTX_REG2_VTT_ENA_SET(val, 0x1); 979 val = RXTX_REG2_VTT_SEL_SET(val, 0x1); 980 val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1); 981 serdes_wr(ctx, lane, RXTX_REG2, val); 982 983 /* Configure Tx for 20-bits */ 984 serdes_rd(ctx, lane, RXTX_REG4, &val); 985 val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); 986 serdes_wr(ctx, lane, RXTX_REG4, val); 987 988 if (!preA3Chip) { 989 serdes_rd(ctx, lane, RXTX_REG1, &val); 990 val = RXTX_REG1_RXVREG1_SET(val, 0x2); 991 val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2); 992 serdes_wr(ctx, lane, RXTX_REG1, val); 993 } 994 995 /* Set pre-emphasis first 1 and 2, and post-emphasis values */ 996 serdes_rd(ctx, lane, RXTX_REG5, &val); 997 val = RXTX_REG5_TX_CN1_SET(val, 998 ctx->sata_param.txprecursor_cn1[lane * 3 + 999 ctx->sata_param.speed[lane]]); 1000 val = RXTX_REG5_TX_CP1_SET(val, 1001 ctx->sata_param.txpostcursor_cp1[lane * 3 + 1002 ctx->sata_param.speed[lane]]); 1003 val = RXTX_REG5_TX_CN2_SET(val, 1004 ctx->sata_param.txprecursor_cn2[lane * 3 + 1005 ctx->sata_param.speed[lane]]); 1006 serdes_wr(ctx, lane, RXTX_REG5, val); 1007 1008 /* Set TX amplitude value */ 1009 serdes_rd(ctx, lane, RXTX_REG6, &val); 1010 val = RXTX_REG6_TXAMP_CNTL_SET(val, 1011 ctx->sata_param.txamplitude[lane * 3 + 1012 ctx->sata_param.speed[lane]]); 1013 val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1); 1014 val = RXTX_REG6_TX_IDLE_SET(val, 0x0); 1015 val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0); 1016 val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0); 1017 serdes_wr(ctx, lane, RXTX_REG6, val); 1018 1019 /* Configure Rx for 20-bits */ 1020 serdes_rd(ctx, lane, RXTX_REG7, &val); 1021 val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0); 1022 val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); 1023 serdes_wr(ctx, lane, RXTX_REG7, val); 1024 1025 /* Set CDR and LOS values and enable Rx SSC */ 1026 serdes_rd(ctx, lane, RXTX_REG8, &val); 1027 val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1); 1028 val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0); 1029 val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1); 1030 val = RXTX_REG8_SD_DISABLE_SET(val, 0x0); 1031 val = RXTX_REG8_SD_VREF_SET(val, 0x4); 1032 serdes_wr(ctx, lane, RXTX_REG8, val); 1033 1034 /* Set phase adjust upper/lower limits */ 1035 serdes_rd(ctx, lane, RXTX_REG11, &val); 1036 val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0); 1037 serdes_wr(ctx, lane, RXTX_REG11, val); 1038 1039 /* Enable Latch Off; disable SUMOS and Tx termination */ 1040 serdes_rd(ctx, lane, RXTX_REG12, &val); 1041 val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1); 1042 val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0); 1043 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0); 1044 serdes_wr(ctx, lane, RXTX_REG12, val); 1045 1046 /* Set period error latch to 512T and enable BWL */ 1047 serdes_rd(ctx, lane, RXTX_REG26, &val); 1048 val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0); 1049 val = RXTX_REG26_BLWC_ENA_SET(val, 0x1); 1050 serdes_wr(ctx, lane, RXTX_REG26, val); 1051 1052 serdes_wr(ctx, lane, RXTX_REG28, 0x0); 1053 1054 /* Set DFE loop preset value */ 1055 serdes_wr(ctx, lane, RXTX_REG31, 0x0); 1056 1057 /* Set Eye Monitor counter width to 12-bit */ 1058 serdes_rd(ctx, lane, RXTX_REG61, &val); 1059 val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1); 1060 val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0); 1061 val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0); 1062 serdes_wr(ctx, lane, RXTX_REG61, val); 1063 1064 serdes_rd(ctx, lane, RXTX_REG62, &val); 1065 val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0); 1066 serdes_wr(ctx, lane, RXTX_REG62, val); 1067 1068 /* Set BW select tap X for DFE loop */ 1069 for (i = 0; i < 9; i++) { 1070 reg = RXTX_REG81 + i * 2; 1071 serdes_rd(ctx, lane, reg, &val); 1072 val = RXTX_REG89_MU_TH7_SET(val, 0xe); 1073 val = RXTX_REG89_MU_TH8_SET(val, 0xe); 1074 val = RXTX_REG89_MU_TH9_SET(val, 0xe); 1075 serdes_wr(ctx, lane, reg, val); 1076 } 1077 1078 /* Set BW select tap X for frequency adjust loop */ 1079 for (i = 0; i < 3; i++) { 1080 reg = RXTX_REG96 + i * 2; 1081 serdes_rd(ctx, lane, reg, &val); 1082 val = RXTX_REG96_MU_FREQ1_SET(val, 0x10); 1083 val = RXTX_REG96_MU_FREQ2_SET(val, 0x10); 1084 val = RXTX_REG96_MU_FREQ3_SET(val, 0x10); 1085 serdes_wr(ctx, lane, reg, val); 1086 } 1087 1088 /* Set BW select tap X for phase adjust loop */ 1089 for (i = 0; i < 3; i++) { 1090 reg = RXTX_REG99 + i * 2; 1091 serdes_rd(ctx, lane, reg, &val); 1092 val = RXTX_REG99_MU_PHASE1_SET(val, 0x7); 1093 val = RXTX_REG99_MU_PHASE2_SET(val, 0x7); 1094 val = RXTX_REG99_MU_PHASE3_SET(val, 0x7); 1095 serdes_wr(ctx, lane, reg, val); 1096 } 1097 1098 serdes_rd(ctx, lane, RXTX_REG102, &val); 1099 val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0); 1100 serdes_wr(ctx, lane, RXTX_REG102, val); 1101 1102 serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); 1103 1104 serdes_rd(ctx, lane, RXTX_REG125, &val); 1105 val = RXTX_REG125_SIGN_PQ_SET(val, 1106 ctx->sata_param.txeyedirection[lane * 3 + 1107 ctx->sata_param.speed[lane]]); 1108 val = RXTX_REG125_PQ_REG_SET(val, 1109 ctx->sata_param.txeyetuning[lane * 3 + 1110 ctx->sata_param.speed[lane]]); 1111 val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1); 1112 serdes_wr(ctx, lane, RXTX_REG125, val); 1113 1114 serdes_rd(ctx, lane, RXTX_REG127, &val); 1115 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0); 1116 serdes_wr(ctx, lane, RXTX_REG127, val); 1117 1118 serdes_rd(ctx, lane, RXTX_REG128, &val); 1119 val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3); 1120 serdes_wr(ctx, lane, RXTX_REG128, val); 1121 1122 serdes_rd(ctx, lane, RXTX_REG145, &val); 1123 val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3); 1124 val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0); 1125 if (preA3Chip) { 1126 val = RXTX_REG145_RXES_ENA_SET(val, 0x1); 1127 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1); 1128 } else { 1129 val = RXTX_REG145_RXES_ENA_SET(val, 0x0); 1130 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0); 1131 } 1132 serdes_wr(ctx, lane, RXTX_REG145, val); 1133 1134 /* 1135 * Set Rx LOS filter clock rate, sample rate, and threshold 1136 * windows 1137 */ 1138 for (i = 0; i < 4; i++) { 1139 reg = RXTX_REG148 + i * 2; 1140 serdes_wr(ctx, lane, reg, 0xFFFF); 1141 } 1142 } 1143 } 1144 1145 static int xgene_phy_cal_rdy_chk(struct xgene_phy_ctx *ctx, 1146 enum cmu_type_t cmu_type, 1147 enum clk_type_t clk_type) 1148 { 1149 void __iomem *csr_serdes = ctx->sds_base; 1150 int loop; 1151 u32 val; 1152 1153 /* Release PHY main reset */ 1154 writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL); 1155 readl(csr_serdes + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ 1156 1157 if (cmu_type != REF_CMU) { 1158 cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); 1159 /* 1160 * As per PHY design spec, the PLL reset requires a minimum 1161 * of 800us. 1162 */ 1163 usleep_range(800, 1000); 1164 1165 cmu_rd(ctx, cmu_type, CMU_REG1, &val); 1166 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); 1167 cmu_wr(ctx, cmu_type, CMU_REG1, val); 1168 /* 1169 * As per PHY design spec, the PLL auto calibration requires 1170 * a minimum of 800us. 1171 */ 1172 usleep_range(800, 1000); 1173 1174 cmu_toggle1to0(ctx, cmu_type, CMU_REG32, 1175 CMU_REG32_FORCE_VCOCAL_START_MASK); 1176 /* 1177 * As per PHY design spec, the PLL requires a minimum of 1178 * 800us to settle. 1179 */ 1180 usleep_range(800, 1000); 1181 } 1182 1183 if (!preA3Chip) 1184 goto skip_manual_cal; 1185 1186 /* 1187 * Configure the termination resister calibration 1188 * The serial receive pins, RXP/RXN, have TERMination resistor 1189 * that is required to be calibrated. 1190 */ 1191 cmu_rd(ctx, cmu_type, CMU_REG17, &val); 1192 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12); 1193 val = CMU_REG17_RESERVED_7_SET(val, 0x0); 1194 cmu_wr(ctx, cmu_type, CMU_REG17, val); 1195 cmu_toggle1to0(ctx, cmu_type, CMU_REG17, 1196 CMU_REG17_PVT_TERM_MAN_ENA_MASK); 1197 /* 1198 * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN 1199 * resistors that are required to the calibrated. 1200 * Configure the pull DOWN calibration 1201 */ 1202 cmu_rd(ctx, cmu_type, CMU_REG17, &val); 1203 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29); 1204 val = CMU_REG17_RESERVED_7_SET(val, 0x0); 1205 cmu_wr(ctx, cmu_type, CMU_REG17, val); 1206 cmu_toggle1to0(ctx, cmu_type, CMU_REG16, 1207 CMU_REG16_PVT_DN_MAN_ENA_MASK); 1208 /* Configure the pull UP calibration */ 1209 cmu_rd(ctx, cmu_type, CMU_REG17, &val); 1210 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28); 1211 val = CMU_REG17_RESERVED_7_SET(val, 0x0); 1212 cmu_wr(ctx, cmu_type, CMU_REG17, val); 1213 cmu_toggle1to0(ctx, cmu_type, CMU_REG16, 1214 CMU_REG16_PVT_UP_MAN_ENA_MASK); 1215 1216 skip_manual_cal: 1217 /* Poll the PLL calibration completion status for at least 1 ms */ 1218 loop = 100; 1219 do { 1220 cmu_rd(ctx, cmu_type, CMU_REG7, &val); 1221 if (CMU_REG7_PLL_CALIB_DONE_RD(val)) 1222 break; 1223 /* 1224 * As per PHY design spec, PLL calibration status requires 1225 * a minimum of 10us to be updated. 1226 */ 1227 usleep_range(10, 100); 1228 } while (--loop > 0); 1229 1230 cmu_rd(ctx, cmu_type, CMU_REG7, &val); 1231 dev_dbg(ctx->dev, "PLL calibration %s\n", 1232 CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed"); 1233 if (CMU_REG7_VCO_CAL_FAIL_RD(val)) { 1234 dev_err(ctx->dev, 1235 "PLL calibration failed due to VCO failure\n"); 1236 return -1; 1237 } 1238 dev_dbg(ctx->dev, "PLL calibration successful\n"); 1239 1240 cmu_rd(ctx, cmu_type, CMU_REG15, &val); 1241 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); 1242 return 0; 1243 } 1244 1245 static void xgene_phy_pdwn_force_vco(struct xgene_phy_ctx *ctx, 1246 enum cmu_type_t cmu_type, 1247 enum clk_type_t clk_type) 1248 { 1249 u32 val; 1250 1251 dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); 1252 if (cmu_type == PHY_CMU) { 1253 cmu_rd(ctx, cmu_type, CMU_REG16, &val); 1254 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); 1255 cmu_wr(ctx, cmu_type, CMU_REG16, val); 1256 } 1257 1258 cmu_toggle1to0(ctx, cmu_type, CMU_REG0, CMU_REG0_PDOWN_MASK); 1259 cmu_toggle1to0(ctx, cmu_type, CMU_REG32, 1260 CMU_REG32_FORCE_VCOCAL_START_MASK); 1261 } 1262 1263 static int xgene_phy_hw_init_sata(struct xgene_phy_ctx *ctx, 1264 enum clk_type_t clk_type, int ssc_enable) 1265 { 1266 void __iomem *sds_base = ctx->sds_base; 1267 u32 val; 1268 int i; 1269 1270 /* Configure the PHY for operation */ 1271 dev_dbg(ctx->dev, "Reset PHY\n"); 1272 /* Place PHY into reset */ 1273 writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL); 1274 val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ 1275 /* Release PHY lane from reset (active high) */ 1276 writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL); 1277 readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ 1278 /* Release all PHY module out of reset except PHY main reset */ 1279 writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL); 1280 readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ 1281 1282 /* Set the operation speed */ 1283 val = readl(sds_base + SATA_ENET_SDS_CTL1); 1284 val = CFG_I_SPD_SEL_CDR_OVR1_SET(val, 1285 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); 1286 writel(val, sds_base + SATA_ENET_SDS_CTL1); 1287 1288 dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); 1289 val = readl(sds_base + SATA_ENET_SDS_CTL0); 1290 val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421); 1291 writel(val, sds_base + SATA_ENET_SDS_CTL0); 1292 1293 /* Configure the clock macro unit (CMU) clock type */ 1294 xgene_phy_cfg_cmu_clk_type(ctx, PHY_CMU, clk_type); 1295 1296 /* Configure the clock macro */ 1297 xgene_phy_sata_cfg_cmu_core(ctx, PHY_CMU, clk_type); 1298 1299 /* Enable SSC if enabled */ 1300 if (ssc_enable) 1301 xgene_phy_ssc_enable(ctx, PHY_CMU); 1302 1303 /* Configure PHY lanes */ 1304 xgene_phy_sata_cfg_lanes(ctx); 1305 1306 /* Set Rx/Tx 20-bit */ 1307 val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0); 1308 val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3); 1309 val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3); 1310 writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0); 1311 1312 /* Start PLL calibration and try for three times */ 1313 i = 10; 1314 do { 1315 if (!xgene_phy_cal_rdy_chk(ctx, PHY_CMU, clk_type)) 1316 break; 1317 /* If failed, toggle the VCO power signal and start again */ 1318 xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type); 1319 } while (--i > 0); 1320 /* Even on failure, allow to continue any way */ 1321 if (i <= 0) 1322 dev_err(ctx->dev, "PLL calibration failed\n"); 1323 1324 return 0; 1325 } 1326 1327 static int xgene_phy_hw_initialize(struct xgene_phy_ctx *ctx, 1328 enum clk_type_t clk_type, 1329 int ssc_enable) 1330 { 1331 int rc; 1332 1333 dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); 1334 1335 if (ctx->mode == MODE_SATA) { 1336 rc = xgene_phy_hw_init_sata(ctx, clk_type, ssc_enable); 1337 if (rc) 1338 return rc; 1339 } else { 1340 dev_err(ctx->dev, "Un-supported customer pin mode %d\n", 1341 ctx->mode); 1342 return -ENODEV; 1343 } 1344 1345 return 0; 1346 } 1347 1348 /* 1349 * Receiver Offset Calibration: 1350 * 1351 * Calibrate the receiver signal path offset in two steps - summar and 1352 * latch calibrations 1353 */ 1354 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) 1355 { 1356 int i; 1357 struct { 1358 u32 reg; 1359 u32 val; 1360 } serdes_reg[] = { 1361 {RXTX_REG38, 0x0}, 1362 {RXTX_REG39, 0xff00}, 1363 {RXTX_REG40, 0xffff}, 1364 {RXTX_REG41, 0xffff}, 1365 {RXTX_REG42, 0xffff}, 1366 {RXTX_REG43, 0xffff}, 1367 {RXTX_REG44, 0xffff}, 1368 {RXTX_REG45, 0xffff}, 1369 {RXTX_REG46, 0xffff}, 1370 {RXTX_REG47, 0xfffc}, 1371 {RXTX_REG48, 0x0}, 1372 {RXTX_REG49, 0x0}, 1373 {RXTX_REG50, 0x0}, 1374 {RXTX_REG51, 0x0}, 1375 {RXTX_REG52, 0x0}, 1376 {RXTX_REG53, 0x0}, 1377 {RXTX_REG54, 0x0}, 1378 {RXTX_REG55, 0x0}, 1379 }; 1380 1381 /* Start SUMMER calibration */ 1382 serdes_setbits(ctx, lane, RXTX_REG127, 1383 RXTX_REG127_FORCE_SUM_CAL_START_MASK); 1384 /* 1385 * As per PHY design spec, the Summer calibration requires a minimum 1386 * of 100us to complete. 1387 */ 1388 usleep_range(100, 500); 1389 serdes_clrbits(ctx, lane, RXTX_REG127, 1390 RXTX_REG127_FORCE_SUM_CAL_START_MASK); 1391 /* 1392 * As per PHY design spec, the auto calibration requires a minimum 1393 * of 100us to complete. 1394 */ 1395 usleep_range(100, 500); 1396 1397 /* Start latch calibration */ 1398 serdes_setbits(ctx, lane, RXTX_REG127, 1399 RXTX_REG127_FORCE_LAT_CAL_START_MASK); 1400 /* 1401 * As per PHY design spec, the latch calibration requires a minimum 1402 * of 100us to complete. 1403 */ 1404 usleep_range(100, 500); 1405 serdes_clrbits(ctx, lane, RXTX_REG127, 1406 RXTX_REG127_FORCE_LAT_CAL_START_MASK); 1407 1408 /* Configure the PHY lane for calibration */ 1409 serdes_wr(ctx, lane, RXTX_REG28, 0x7); 1410 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); 1411 serdes_clrbits(ctx, lane, RXTX_REG4, 1412 RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK); 1413 serdes_clrbits(ctx, lane, RXTX_REG7, 1414 RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK); 1415 for (i = 0; i < ARRAY_SIZE(serdes_reg); i++) 1416 serdes_wr(ctx, lane, serdes_reg[i].reg, 1417 serdes_reg[i].val); 1418 } 1419 1420 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) 1421 { 1422 /* Reset digital Rx */ 1423 serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); 1424 /* As per PHY design spec, the reset requires a minimum of 100us. */ 1425 usleep_range(100, 150); 1426 serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); 1427 } 1428 1429 static int xgene_phy_get_avg(int accum, int samples) 1430 { 1431 return (accum + (samples / 2)) / samples; 1432 } 1433 1434 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) 1435 { 1436 int max_loop = 10; 1437 int avg_loop = 0; 1438 int lat_do = 0, lat_xo = 0, lat_eo = 0, lat_so = 0; 1439 int lat_de = 0, lat_xe = 0, lat_ee = 0, lat_se = 0; 1440 int sum_cal = 0; 1441 int lat_do_itr, lat_xo_itr, lat_eo_itr, lat_so_itr; 1442 int lat_de_itr, lat_xe_itr, lat_ee_itr, lat_se_itr; 1443 int sum_cal_itr; 1444 int fail_even; 1445 int fail_odd; 1446 u32 val; 1447 1448 dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", 1449 lane); 1450 1451 /* Enable RX Hi-Z termination */ 1452 serdes_setbits(ctx, lane, RXTX_REG12, 1453 RXTX_REG12_RX_DET_TERM_ENABLE_MASK); 1454 /* Turn off DFE */ 1455 serdes_wr(ctx, lane, RXTX_REG28, 0x0000); 1456 /* DFE Presets to zero */ 1457 serdes_wr(ctx, lane, RXTX_REG31, 0x0000); 1458 1459 /* 1460 * Receiver Offset Calibration: 1461 * Calibrate the receiver signal path offset in two steps - summar 1462 * and latch calibration. 1463 * Runs the "Receiver Offset Calibration multiple times to determine 1464 * the average value to use. 1465 */ 1466 while (avg_loop < max_loop) { 1467 /* Start the calibration */ 1468 xgene_phy_force_lat_summer_cal(ctx, lane); 1469 1470 serdes_rd(ctx, lane, RXTX_REG21, &val); 1471 lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val); 1472 lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val); 1473 fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val); 1474 1475 serdes_rd(ctx, lane, RXTX_REG22, &val); 1476 lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val); 1477 lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val); 1478 fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val); 1479 1480 serdes_rd(ctx, lane, RXTX_REG23, &val); 1481 lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val); 1482 lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val); 1483 1484 serdes_rd(ctx, lane, RXTX_REG24, &val); 1485 lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val); 1486 lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val); 1487 1488 serdes_rd(ctx, lane, RXTX_REG121, &val); 1489 sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val); 1490 1491 /* Check for failure. If passed, sum them for averaging */ 1492 if ((fail_even == 0 || fail_even == 1) && 1493 (fail_odd == 0 || fail_odd == 1)) { 1494 lat_do += lat_do_itr; 1495 lat_xo += lat_xo_itr; 1496 lat_eo += lat_eo_itr; 1497 lat_so += lat_so_itr; 1498 lat_de += lat_de_itr; 1499 lat_xe += lat_xe_itr; 1500 lat_ee += lat_ee_itr; 1501 lat_se += lat_se_itr; 1502 sum_cal += sum_cal_itr; 1503 1504 dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); 1505 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", 1506 lat_do_itr, lat_xo_itr, lat_eo_itr, 1507 lat_so_itr); 1508 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", 1509 lat_de_itr, lat_xe_itr, lat_ee_itr, 1510 lat_se_itr); 1511 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); 1512 ++avg_loop; 1513 } else { 1514 dev_err(ctx->dev, 1515 "Receiver calibration failed at %d loop\n", 1516 avg_loop); 1517 } 1518 xgene_phy_reset_rxd(ctx, lane); 1519 } 1520 1521 /* Update latch manual calibration with average value */ 1522 serdes_rd(ctx, lane, RXTX_REG127, &val); 1523 val = RXTX_REG127_DO_LATCH_MANCAL_SET(val, 1524 xgene_phy_get_avg(lat_do, max_loop)); 1525 val = RXTX_REG127_XO_LATCH_MANCAL_SET(val, 1526 xgene_phy_get_avg(lat_xo, max_loop)); 1527 serdes_wr(ctx, lane, RXTX_REG127, val); 1528 1529 serdes_rd(ctx, lane, RXTX_REG128, &val); 1530 val = RXTX_REG128_EO_LATCH_MANCAL_SET(val, 1531 xgene_phy_get_avg(lat_eo, max_loop)); 1532 val = RXTX_REG128_SO_LATCH_MANCAL_SET(val, 1533 xgene_phy_get_avg(lat_so, max_loop)); 1534 serdes_wr(ctx, lane, RXTX_REG128, val); 1535 1536 serdes_rd(ctx, lane, RXTX_REG129, &val); 1537 val = RXTX_REG129_DE_LATCH_MANCAL_SET(val, 1538 xgene_phy_get_avg(lat_de, max_loop)); 1539 val = RXTX_REG129_XE_LATCH_MANCAL_SET(val, 1540 xgene_phy_get_avg(lat_xe, max_loop)); 1541 serdes_wr(ctx, lane, RXTX_REG129, val); 1542 1543 serdes_rd(ctx, lane, RXTX_REG130, &val); 1544 val = RXTX_REG130_EE_LATCH_MANCAL_SET(val, 1545 xgene_phy_get_avg(lat_ee, max_loop)); 1546 val = RXTX_REG130_SE_LATCH_MANCAL_SET(val, 1547 xgene_phy_get_avg(lat_se, max_loop)); 1548 serdes_wr(ctx, lane, RXTX_REG130, val); 1549 1550 /* Update SUMMER calibration with average value */ 1551 serdes_rd(ctx, lane, RXTX_REG14, &val); 1552 val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val, 1553 xgene_phy_get_avg(sum_cal, max_loop)); 1554 serdes_wr(ctx, lane, RXTX_REG14, val); 1555 1556 dev_dbg(ctx->dev, "Average Value:\n"); 1557 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", 1558 xgene_phy_get_avg(lat_do, max_loop), 1559 xgene_phy_get_avg(lat_xo, max_loop), 1560 xgene_phy_get_avg(lat_eo, max_loop), 1561 xgene_phy_get_avg(lat_so, max_loop)); 1562 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", 1563 xgene_phy_get_avg(lat_de, max_loop), 1564 xgene_phy_get_avg(lat_xe, max_loop), 1565 xgene_phy_get_avg(lat_ee, max_loop), 1566 xgene_phy_get_avg(lat_se, max_loop)); 1567 dev_dbg(ctx->dev, "SUM 0x%x\n", 1568 xgene_phy_get_avg(sum_cal, max_loop)); 1569 1570 serdes_rd(ctx, lane, RXTX_REG14, &val); 1571 val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1); 1572 serdes_wr(ctx, lane, RXTX_REG14, val); 1573 dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); 1574 1575 serdes_rd(ctx, lane, RXTX_REG127, &val); 1576 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1); 1577 dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); 1578 serdes_wr(ctx, lane, RXTX_REG127, val); 1579 1580 /* Disable RX Hi-Z termination */ 1581 serdes_rd(ctx, lane, RXTX_REG12, &val); 1582 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0); 1583 serdes_wr(ctx, lane, RXTX_REG12, val); 1584 /* Turn on DFE */ 1585 serdes_wr(ctx, lane, RXTX_REG28, 0x0007); 1586 /* Set DFE preset */ 1587 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); 1588 } 1589 1590 static int xgene_phy_hw_init(struct phy *phy) 1591 { 1592 struct xgene_phy_ctx *ctx = phy_get_drvdata(phy); 1593 int rc; 1594 int i; 1595 1596 rc = xgene_phy_hw_initialize(ctx, CLK_EXT_DIFF, SSC_DISABLE); 1597 if (rc) { 1598 dev_err(ctx->dev, "PHY initialize failed %d\n", rc); 1599 return rc; 1600 } 1601 1602 /* Setup clock properly after PHY configuration */ 1603 if (!IS_ERR(ctx->clk)) { 1604 /* HW requires an toggle of the clock */ 1605 clk_prepare_enable(ctx->clk); 1606 clk_disable_unprepare(ctx->clk); 1607 clk_prepare_enable(ctx->clk); 1608 } 1609 1610 /* Compute average value */ 1611 for (i = 0; i < MAX_LANE; i++) 1612 xgene_phy_gen_avg_val(ctx, i); 1613 1614 dev_dbg(ctx->dev, "PHY initialized\n"); 1615 return 0; 1616 } 1617 1618 static const struct phy_ops xgene_phy_ops = { 1619 .init = xgene_phy_hw_init, 1620 .owner = THIS_MODULE, 1621 }; 1622 1623 static struct phy *xgene_phy_xlate(struct device *dev, 1624 struct of_phandle_args *args) 1625 { 1626 struct xgene_phy_ctx *ctx = dev_get_drvdata(dev); 1627 1628 if (args->args_count <= 0) 1629 return ERR_PTR(-EINVAL); 1630 if (args->args[0] < MODE_SATA || args->args[0] >= MODE_MAX) 1631 return ERR_PTR(-EINVAL); 1632 1633 ctx->mode = args->args[0]; 1634 return ctx->phy; 1635 } 1636 1637 static void xgene_phy_get_param(struct platform_device *pdev, 1638 const char *name, u32 *buffer, 1639 int count, u32 *default_val, 1640 u32 conv_factor) 1641 { 1642 int i; 1643 1644 if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer, 1645 count)) { 1646 for (i = 0; i < count; i++) 1647 buffer[i] /= conv_factor; 1648 return; 1649 } 1650 /* Does not exist, load default */ 1651 for (i = 0; i < count; i++) 1652 buffer[i] = default_val[i % 3]; 1653 } 1654 1655 static int xgene_phy_probe(struct platform_device *pdev) 1656 { 1657 struct phy_provider *phy_provider; 1658 struct xgene_phy_ctx *ctx; 1659 struct resource *res; 1660 u32 default_spd[] = DEFAULT_SATA_SPD_SEL; 1661 u32 default_txboost_gain[] = DEFAULT_SATA_TXBOOST_GAIN; 1662 u32 default_txeye_direction[] = DEFAULT_SATA_TXEYEDIRECTION; 1663 u32 default_txeye_tuning[] = DEFAULT_SATA_TXEYETUNING; 1664 u32 default_txamp[] = DEFAULT_SATA_TXAMP; 1665 u32 default_txcn1[] = DEFAULT_SATA_TXCN1; 1666 u32 default_txcn2[] = DEFAULT_SATA_TXCN2; 1667 u32 default_txcp1[] = DEFAULT_SATA_TXCP1; 1668 int i; 1669 1670 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 1671 if (!ctx) 1672 return -ENOMEM; 1673 1674 ctx->dev = &pdev->dev; 1675 1676 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1677 ctx->sds_base = devm_ioremap_resource(&pdev->dev, res); 1678 if (IS_ERR(ctx->sds_base)) 1679 return PTR_ERR(ctx->sds_base); 1680 1681 /* Retrieve optional clock */ 1682 ctx->clk = clk_get(&pdev->dev, NULL); 1683 1684 /* Load override paramaters */ 1685 xgene_phy_get_param(pdev, "apm,tx-eye-tuning", 1686 ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); 1687 xgene_phy_get_param(pdev, "apm,tx-eye-direction", 1688 ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); 1689 xgene_phy_get_param(pdev, "apm,tx-boost-gain", 1690 ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); 1691 xgene_phy_get_param(pdev, "apm,tx-amplitude", 1692 ctx->sata_param.txamplitude, 6, default_txamp, 13300); 1693 xgene_phy_get_param(pdev, "apm,tx-pre-cursor1", 1694 ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); 1695 xgene_phy_get_param(pdev, "apm,tx-pre-cursor2", 1696 ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); 1697 xgene_phy_get_param(pdev, "apm,tx-post-cursor", 1698 ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); 1699 xgene_phy_get_param(pdev, "apm,tx-speed", 1700 ctx->sata_param.txspeed, 3, default_spd, 1); 1701 for (i = 0; i < MAX_LANE; i++) 1702 ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ 1703 1704 platform_set_drvdata(pdev, ctx); 1705 1706 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); 1707 if (IS_ERR(ctx->phy)) { 1708 dev_dbg(&pdev->dev, "Failed to create PHY\n"); 1709 return PTR_ERR(ctx->phy); 1710 } 1711 phy_set_drvdata(ctx->phy, ctx); 1712 1713 phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); 1714 return PTR_ERR_OR_ZERO(phy_provider); 1715 } 1716 1717 static const struct of_device_id xgene_phy_of_match[] = { 1718 {.compatible = "apm,xgene-phy",}, 1719 {}, 1720 }; 1721 MODULE_DEVICE_TABLE(of, xgene_phy_of_match); 1722 1723 static struct platform_driver xgene_phy_driver = { 1724 .probe = xgene_phy_probe, 1725 .driver = { 1726 .name = "xgene-phy", 1727 .of_match_table = xgene_phy_of_match, 1728 }, 1729 }; 1730 module_platform_driver(xgene_phy_driver); 1731 1732 MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver"); 1733 MODULE_AUTHOR("Loc Ho <lho@apm.com>"); 1734 MODULE_LICENSE("GPL v2"); 1735 MODULE_VERSION("0.1"); 1736