1dddc97e8SMaxime Ripard /* SPDX-License-Identifier: GPL-2.0 */ 2dddc97e8SMaxime Ripard /* 3dddc97e8SMaxime Ripard * Copyright (C) 2013 NVIDIA Corporation 4dddc97e8SMaxime Ripard * Copyright (C) 2018 Cadence Design Systems Inc. 5dddc97e8SMaxime Ripard */ 6dddc97e8SMaxime Ripard 7dddc97e8SMaxime Ripard #include <linux/errno.h> 8dddc97e8SMaxime Ripard #include <linux/export.h> 9dddc97e8SMaxime Ripard #include <linux/kernel.h> 10dddc97e8SMaxime Ripard #include <linux/time64.h> 11dddc97e8SMaxime Ripard 12dddc97e8SMaxime Ripard #include <linux/phy/phy.h> 13dddc97e8SMaxime Ripard #include <linux/phy/phy-mipi-dphy.h> 14dddc97e8SMaxime Ripard 15dddc97e8SMaxime Ripard /* 16dddc97e8SMaxime Ripard * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 17dddc97e8SMaxime Ripard * from the valid ranges specified in Section 6.9, Table 14, Page 41 18490dbd23SSebastian Fricke * of the D-PHY specification (v1.2). 19dddc97e8SMaxime Ripard */ 20dddc97e8SMaxime Ripard int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, 21dddc97e8SMaxime Ripard unsigned int bpp, 22dddc97e8SMaxime Ripard unsigned int lanes, 23dddc97e8SMaxime Ripard struct phy_configure_opts_mipi_dphy *cfg) 24dddc97e8SMaxime Ripard { 25dddc97e8SMaxime Ripard unsigned long long hs_clk_rate; 26dddc97e8SMaxime Ripard unsigned long long ui; 27dddc97e8SMaxime Ripard 28dddc97e8SMaxime Ripard if (!cfg) 29dddc97e8SMaxime Ripard return -EINVAL; 30dddc97e8SMaxime Ripard 31dddc97e8SMaxime Ripard hs_clk_rate = pixel_clock * bpp; 32dddc97e8SMaxime Ripard do_div(hs_clk_rate, lanes); 33dddc97e8SMaxime Ripard 34dddc97e8SMaxime Ripard ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 35dddc97e8SMaxime Ripard do_div(ui, hs_clk_rate); 36dddc97e8SMaxime Ripard 37dddc97e8SMaxime Ripard cfg->clk_miss = 0; 38dddc97e8SMaxime Ripard cfg->clk_post = 60000 + 52 * ui; 39*9a8406baSLiu Ying cfg->clk_pre = 8; 40dddc97e8SMaxime Ripard cfg->clk_prepare = 38000; 41dddc97e8SMaxime Ripard cfg->clk_settle = 95000; 42dddc97e8SMaxime Ripard cfg->clk_term_en = 0; 43dddc97e8SMaxime Ripard cfg->clk_trail = 60000; 44dddc97e8SMaxime Ripard cfg->clk_zero = 262000; 45dddc97e8SMaxime Ripard cfg->d_term_en = 0; 46dddc97e8SMaxime Ripard cfg->eot = 0; 47dddc97e8SMaxime Ripard cfg->hs_exit = 100000; 48dddc97e8SMaxime Ripard cfg->hs_prepare = 40000 + 4 * ui; 49dddc97e8SMaxime Ripard cfg->hs_zero = 105000 + 6 * ui; 50dddc97e8SMaxime Ripard cfg->hs_settle = 85000 + 6 * ui; 51dddc97e8SMaxime Ripard cfg->hs_skip = 40000; 52dddc97e8SMaxime Ripard 53dddc97e8SMaxime Ripard /* 54dddc97e8SMaxime Ripard * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 55dddc97e8SMaxime Ripard * contains this formula as: 56dddc97e8SMaxime Ripard * 57dddc97e8SMaxime Ripard * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 58dddc97e8SMaxime Ripard * 59dddc97e8SMaxime Ripard * where n = 1 for forward-direction HS mode and n = 4 for reverse- 60dddc97e8SMaxime Ripard * direction HS mode. There's only one setting and this function does 61dddc97e8SMaxime Ripard * not parameterize on anything other that ui, so this code will 62dddc97e8SMaxime Ripard * assumes that reverse-direction HS mode is supported and uses n = 4. 63dddc97e8SMaxime Ripard */ 64dddc97e8SMaxime Ripard cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 65dddc97e8SMaxime Ripard 662204b2c4SMaxime Ripard cfg->init = 100; 67dddc97e8SMaxime Ripard cfg->lpx = 60000; 68dddc97e8SMaxime Ripard cfg->ta_get = 5 * cfg->lpx; 69dddc97e8SMaxime Ripard cfg->ta_go = 4 * cfg->lpx; 70dddc97e8SMaxime Ripard cfg->ta_sure = 2 * cfg->lpx; 712204b2c4SMaxime Ripard cfg->wakeup = 1000; 72dddc97e8SMaxime Ripard 73dddc97e8SMaxime Ripard cfg->hs_clk_rate = hs_clk_rate; 74dddc97e8SMaxime Ripard cfg->lanes = lanes; 75dddc97e8SMaxime Ripard 76dddc97e8SMaxime Ripard return 0; 77dddc97e8SMaxime Ripard } 78dddc97e8SMaxime Ripard EXPORT_SYMBOL(phy_mipi_dphy_get_default_config); 79dddc97e8SMaxime Ripard 80dddc97e8SMaxime Ripard /* 81dddc97e8SMaxime Ripard * Validate D-PHY configuration according to MIPI D-PHY specification 82dddc97e8SMaxime Ripard * (v1.2, Section Section 6.9 "Global Operation Timing Parameters"). 83dddc97e8SMaxime Ripard */ 84dddc97e8SMaxime Ripard int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg) 85dddc97e8SMaxime Ripard { 86dddc97e8SMaxime Ripard unsigned long long ui; 87dddc97e8SMaxime Ripard 88dddc97e8SMaxime Ripard if (!cfg) 89dddc97e8SMaxime Ripard return -EINVAL; 90dddc97e8SMaxime Ripard 91dddc97e8SMaxime Ripard ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); 92dddc97e8SMaxime Ripard do_div(ui, cfg->hs_clk_rate); 93dddc97e8SMaxime Ripard 94dddc97e8SMaxime Ripard if (cfg->clk_miss > 60000) 95dddc97e8SMaxime Ripard return -EINVAL; 96dddc97e8SMaxime Ripard 97dddc97e8SMaxime Ripard if (cfg->clk_post < (60000 + 52 * ui)) 98dddc97e8SMaxime Ripard return -EINVAL; 99dddc97e8SMaxime Ripard 100*9a8406baSLiu Ying if (cfg->clk_pre < 8) 101dddc97e8SMaxime Ripard return -EINVAL; 102dddc97e8SMaxime Ripard 103dddc97e8SMaxime Ripard if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000) 104dddc97e8SMaxime Ripard return -EINVAL; 105dddc97e8SMaxime Ripard 106dddc97e8SMaxime Ripard if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000) 107dddc97e8SMaxime Ripard return -EINVAL; 108dddc97e8SMaxime Ripard 109dddc97e8SMaxime Ripard if (cfg->clk_term_en > 38000) 110dddc97e8SMaxime Ripard return -EINVAL; 111dddc97e8SMaxime Ripard 112dddc97e8SMaxime Ripard if (cfg->clk_trail < 60000) 113dddc97e8SMaxime Ripard return -EINVAL; 114dddc97e8SMaxime Ripard 115dddc97e8SMaxime Ripard if ((cfg->clk_prepare + cfg->clk_zero) < 300000) 116dddc97e8SMaxime Ripard return -EINVAL; 117dddc97e8SMaxime Ripard 118dddc97e8SMaxime Ripard if (cfg->d_term_en > (35000 + 4 * ui)) 119dddc97e8SMaxime Ripard return -EINVAL; 120dddc97e8SMaxime Ripard 121dddc97e8SMaxime Ripard if (cfg->eot > (105000 + 12 * ui)) 122dddc97e8SMaxime Ripard return -EINVAL; 123dddc97e8SMaxime Ripard 124dddc97e8SMaxime Ripard if (cfg->hs_exit < 100000) 125dddc97e8SMaxime Ripard return -EINVAL; 126dddc97e8SMaxime Ripard 127dddc97e8SMaxime Ripard if (cfg->hs_prepare < (40000 + 4 * ui) || 128dddc97e8SMaxime Ripard cfg->hs_prepare > (85000 + 6 * ui)) 129dddc97e8SMaxime Ripard return -EINVAL; 130dddc97e8SMaxime Ripard 131dddc97e8SMaxime Ripard if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui)) 132dddc97e8SMaxime Ripard return -EINVAL; 133dddc97e8SMaxime Ripard 134dddc97e8SMaxime Ripard if ((cfg->hs_settle < (85000 + 6 * ui)) || 135dddc97e8SMaxime Ripard (cfg->hs_settle > (145000 + 10 * ui))) 136dddc97e8SMaxime Ripard return -EINVAL; 137dddc97e8SMaxime Ripard 138dddc97e8SMaxime Ripard if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui)) 139dddc97e8SMaxime Ripard return -EINVAL; 140dddc97e8SMaxime Ripard 141dddc97e8SMaxime Ripard if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui)) 142dddc97e8SMaxime Ripard return -EINVAL; 143dddc97e8SMaxime Ripard 1442204b2c4SMaxime Ripard if (cfg->init < 100) 145dddc97e8SMaxime Ripard return -EINVAL; 146dddc97e8SMaxime Ripard 147dddc97e8SMaxime Ripard if (cfg->lpx < 50000) 148dddc97e8SMaxime Ripard return -EINVAL; 149dddc97e8SMaxime Ripard 150dddc97e8SMaxime Ripard if (cfg->ta_get != (5 * cfg->lpx)) 151dddc97e8SMaxime Ripard return -EINVAL; 152dddc97e8SMaxime Ripard 153dddc97e8SMaxime Ripard if (cfg->ta_go != (4 * cfg->lpx)) 154dddc97e8SMaxime Ripard return -EINVAL; 155dddc97e8SMaxime Ripard 156dddc97e8SMaxime Ripard if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx)) 157dddc97e8SMaxime Ripard return -EINVAL; 158dddc97e8SMaxime Ripard 1592204b2c4SMaxime Ripard if (cfg->wakeup < 1000) 160dddc97e8SMaxime Ripard return -EINVAL; 161dddc97e8SMaxime Ripard 162dddc97e8SMaxime Ripard return 0; 163dddc97e8SMaxime Ripard } 164dddc97e8SMaxime Ripard EXPORT_SYMBOL(phy_mipi_dphy_config_validate); 165