1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/err.h> 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/of_platform.h> 7 #include <linux/phy.h> 8 #include <linux/phy/phy.h> 9 #include <linux/platform_device.h> 10 11 #include <dt-bindings/phy/phy-lan966x-serdes.h> 12 #include "lan966x_serdes_regs.h" 13 14 #define PLL_CONF_MASK GENMASK(4, 3) 15 #define PLL_CONF_25MHZ 0 16 #define PLL_CONF_125MHZ 1 17 #define PLL_CONF_SERDES_125MHZ 2 18 #define PLL_CONF_BYPASS 3 19 20 #define lan_offset_(id, tinst, tcnt, \ 21 gbase, ginst, gcnt, gwidth, \ 22 raddr, rinst, rcnt, rwidth) \ 23 (gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth)) 24 #define lan_offset(...) lan_offset_(__VA_ARGS__) 25 26 #define lan_rmw(val, mask, reg, off) \ 27 lan_rmw_(val, mask, reg, lan_offset(off)) 28 29 #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \ 30 .idx = _idx, \ 31 .port = _port, \ 32 .mode = _mode, \ 33 .submode = _submode, \ 34 .mask = _mask, \ 35 .mux = _mux, \ 36 } 37 38 #define SERDES_MUX_GMII(i, p, m, c) \ 39 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_GMII, m, c) 40 #define SERDES_MUX_SGMII(i, p, m, c) \ 41 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c) 42 #define SERDES_MUX_QSGMII(i, p, m, c) \ 43 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c) 44 #define SERDES_MUX_RGMII(i, p, m, c) \ 45 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII, m, c), \ 46 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_TXID, m, c), \ 47 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_RXID, m, c), \ 48 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII_ID, m, c) 49 50 static void lan_rmw_(u32 val, u32 mask, void __iomem *mem, u32 offset) 51 { 52 u32 v; 53 54 v = readl(mem + offset); 55 v = (v & ~mask) | (val & mask); 56 writel(v, mem + offset); 57 } 58 59 struct serdes_mux { 60 u8 idx; 61 u8 port; 62 enum phy_mode mode; 63 int submode; 64 u32 mask; 65 u32 mux; 66 }; 67 68 static const struct serdes_mux lan966x_serdes_muxes[] = { 69 SERDES_MUX_QSGMII(SERDES6G(1), 0, HSIO_HW_CFG_QSGMII_ENA, 70 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))), 71 SERDES_MUX_QSGMII(SERDES6G(1), 1, HSIO_HW_CFG_QSGMII_ENA, 72 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))), 73 SERDES_MUX_QSGMII(SERDES6G(1), 2, HSIO_HW_CFG_QSGMII_ENA, 74 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))), 75 SERDES_MUX_QSGMII(SERDES6G(1), 3, HSIO_HW_CFG_QSGMII_ENA, 76 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))), 77 78 SERDES_MUX_QSGMII(SERDES6G(2), 4, HSIO_HW_CFG_QSGMII_ENA, 79 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))), 80 SERDES_MUX_QSGMII(SERDES6G(2), 5, HSIO_HW_CFG_QSGMII_ENA, 81 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))), 82 SERDES_MUX_QSGMII(SERDES6G(2), 6, HSIO_HW_CFG_QSGMII_ENA, 83 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))), 84 SERDES_MUX_QSGMII(SERDES6G(2), 7, HSIO_HW_CFG_QSGMII_ENA, 85 HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))), 86 87 SERDES_MUX_GMII(CU(0), 0, HSIO_HW_CFG_GMII_ENA, 88 HSIO_HW_CFG_GMII_ENA_SET(BIT(0))), 89 SERDES_MUX_GMII(CU(1), 1, HSIO_HW_CFG_GMII_ENA, 90 HSIO_HW_CFG_GMII_ENA_SET(BIT(1))), 91 92 SERDES_MUX_SGMII(SERDES6G(0), 0, HSIO_HW_CFG_SD6G_0_CFG, 0), 93 SERDES_MUX_SGMII(SERDES6G(1), 1, HSIO_HW_CFG_SD6G_1_CFG, 0), 94 SERDES_MUX_SGMII(SERDES6G(0), 2, HSIO_HW_CFG_SD6G_0_CFG, 95 HSIO_HW_CFG_SD6G_0_CFG_SET(1)), 96 SERDES_MUX_SGMII(SERDES6G(1), 3, HSIO_HW_CFG_SD6G_1_CFG, 97 HSIO_HW_CFG_SD6G_1_CFG_SET(1)), 98 99 SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG | 100 HSIO_HW_CFG_RGMII_ENA | 101 HSIO_HW_CFG_GMII_ENA, 102 HSIO_HW_CFG_RGMII_0_CFG_SET(0) | 103 HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) | 104 HSIO_HW_CFG_GMII_ENA_SET(BIT(2))), 105 SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG | 106 HSIO_HW_CFG_RGMII_ENA | 107 HSIO_HW_CFG_GMII_ENA, 108 HSIO_HW_CFG_RGMII_1_CFG_SET(0) | 109 HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) | 110 HSIO_HW_CFG_GMII_ENA_SET(BIT(3))), 111 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG | 112 HSIO_HW_CFG_RGMII_ENA | 113 HSIO_HW_CFG_GMII_ENA, 114 HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) | 115 HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) | 116 HSIO_HW_CFG_GMII_ENA_SET(BIT(5))), 117 SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG | 118 HSIO_HW_CFG_RGMII_ENA | 119 HSIO_HW_CFG_GMII_ENA, 120 HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) | 121 HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) | 122 HSIO_HW_CFG_GMII_ENA_SET(BIT(6))), 123 }; 124 125 struct serdes_ctrl { 126 void __iomem *regs; 127 struct device *dev; 128 struct phy *phys[SERDES_MAX]; 129 int ref125; 130 }; 131 132 struct serdes_macro { 133 u8 idx; 134 int port; 135 struct serdes_ctrl *ctrl; 136 int speed; 137 phy_interface_t mode; 138 }; 139 140 enum lan966x_sd6g40_mode { 141 LAN966X_SD6G40_MODE_QSGMII, 142 LAN966X_SD6G40_MODE_SGMII, 143 }; 144 145 enum lan966x_sd6g40_ltx2rx { 146 LAN966X_SD6G40_TX2RX_LOOP_NONE, 147 LAN966X_SD6G40_LTX2RX 148 }; 149 150 struct lan966x_sd6g40_setup_args { 151 enum lan966x_sd6g40_mode mode; 152 enum lan966x_sd6g40_ltx2rx tx2rx_loop; 153 bool txinvert; 154 bool rxinvert; 155 bool refclk125M; 156 bool mute; 157 }; 158 159 struct lan966x_sd6g40_mode_args { 160 enum lan966x_sd6g40_mode mode; 161 u8 lane_10bit_sel; 162 u8 mpll_multiplier; 163 u8 ref_clkdiv2; 164 u8 tx_rate; 165 u8 rx_rate; 166 }; 167 168 struct lan966x_sd6g40_setup { 169 u8 rx_term_en; 170 u8 lane_10bit_sel; 171 u8 tx_invert; 172 u8 rx_invert; 173 u8 mpll_multiplier; 174 u8 lane_loopbk_en; 175 u8 ref_clkdiv2; 176 u8 tx_rate; 177 u8 rx_rate; 178 }; 179 180 static int lan966x_sd6g40_reg_cfg(struct serdes_macro *macro, 181 struct lan966x_sd6g40_setup *res_struct, 182 u32 idx) 183 { 184 u32 value; 185 186 /* Note: SerDes HSIO is configured in 1G_LAN mode */ 187 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | 188 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) | 189 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) | 190 HSIO_SD_CFG_TX_INVERT_SET(res_struct->tx_invert) | 191 HSIO_SD_CFG_RX_INVERT_SET(res_struct->rx_invert) | 192 HSIO_SD_CFG_LANE_LOOPBK_EN_SET(res_struct->lane_loopbk_en) | 193 HSIO_SD_CFG_RX_RESET_SET(0) | 194 HSIO_SD_CFG_TX_RESET_SET(0), 195 HSIO_SD_CFG_LANE_10BIT_SEL | 196 HSIO_SD_CFG_RX_RATE | 197 HSIO_SD_CFG_TX_RATE | 198 HSIO_SD_CFG_TX_INVERT | 199 HSIO_SD_CFG_RX_INVERT | 200 HSIO_SD_CFG_LANE_LOOPBK_EN | 201 HSIO_SD_CFG_RX_RESET | 202 HSIO_SD_CFG_TX_RESET, 203 macro->ctrl->regs, HSIO_SD_CFG(idx)); 204 205 lan_rmw(HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(res_struct->mpll_multiplier) | 206 HSIO_MPLL_CFG_REF_CLKDIV2_SET(res_struct->ref_clkdiv2), 207 HSIO_MPLL_CFG_MPLL_MULTIPLIER | 208 HSIO_MPLL_CFG_REF_CLKDIV2, 209 macro->ctrl->regs, HSIO_MPLL_CFG(idx)); 210 211 lan_rmw(HSIO_SD_CFG_RX_TERM_EN_SET(res_struct->rx_term_en), 212 HSIO_SD_CFG_RX_TERM_EN, 213 macro->ctrl->regs, HSIO_SD_CFG(idx)); 214 215 lan_rmw(HSIO_MPLL_CFG_REF_SSP_EN_SET(1), 216 HSIO_MPLL_CFG_REF_SSP_EN, 217 macro->ctrl->regs, HSIO_MPLL_CFG(idx)); 218 219 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 220 221 lan_rmw(HSIO_SD_CFG_PHY_RESET_SET(0), 222 HSIO_SD_CFG_PHY_RESET, 223 macro->ctrl->regs, HSIO_SD_CFG(idx)); 224 225 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 226 227 lan_rmw(HSIO_MPLL_CFG_MPLL_EN_SET(1), 228 HSIO_MPLL_CFG_MPLL_EN, 229 macro->ctrl->regs, HSIO_MPLL_CFG(idx)); 230 231 usleep_range(7 * USEC_PER_MSEC, 8 * USEC_PER_MSEC); 232 233 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx))); 234 value = HSIO_SD_STAT_MPLL_STATE_GET(value); 235 if (value != 0x1) { 236 dev_err(macro->ctrl->dev, 237 "Unexpected sd_sd_stat[%u] mpll_state was 0x1 but is 0x%x\n", 238 idx, value); 239 return -EIO; 240 } 241 242 lan_rmw(HSIO_SD_CFG_TX_CM_EN_SET(1), 243 HSIO_SD_CFG_TX_CM_EN, 244 macro->ctrl->regs, HSIO_SD_CFG(idx)); 245 246 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 247 248 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx))); 249 value = HSIO_SD_STAT_TX_CM_STATE_GET(value); 250 if (value != 0x1) { 251 dev_err(macro->ctrl->dev, 252 "Unexpected sd_sd_stat[%u] tx_cm_state was 0x1 but is 0x%x\n", 253 idx, value); 254 return -EIO; 255 } 256 257 lan_rmw(HSIO_SD_CFG_RX_PLL_EN_SET(1) | 258 HSIO_SD_CFG_TX_EN_SET(1), 259 HSIO_SD_CFG_RX_PLL_EN | 260 HSIO_SD_CFG_TX_EN, 261 macro->ctrl->regs, HSIO_SD_CFG(idx)); 262 263 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 264 265 /* Waiting for serdes 0 rx DPLL to lock... */ 266 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx))); 267 value = HSIO_SD_STAT_RX_PLL_STATE_GET(value); 268 if (value != 0x1) { 269 dev_err(macro->ctrl->dev, 270 "Unexpected sd_sd_stat[%u] rx_pll_state was 0x1 but is 0x%x\n", 271 idx, value); 272 return -EIO; 273 } 274 275 /* Waiting for serdes 0 tx operational... */ 276 value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx))); 277 value = HSIO_SD_STAT_TX_STATE_GET(value); 278 if (value != 0x1) { 279 dev_err(macro->ctrl->dev, 280 "Unexpected sd_sd_stat[%u] tx_state was 0x1 but is 0x%x\n", 281 idx, value); 282 return -EIO; 283 } 284 285 lan_rmw(HSIO_SD_CFG_TX_DATA_EN_SET(1) | 286 HSIO_SD_CFG_RX_DATA_EN_SET(1), 287 HSIO_SD_CFG_TX_DATA_EN | 288 HSIO_SD_CFG_RX_DATA_EN, 289 macro->ctrl->regs, HSIO_SD_CFG(idx)); 290 291 return 0; 292 } 293 294 static int lan966x_sd6g40_get_conf_from_mode(struct serdes_macro *macro, 295 enum lan966x_sd6g40_mode f_mode, 296 bool ref125M, 297 struct lan966x_sd6g40_mode_args *ret_val) 298 { 299 switch (f_mode) { 300 case LAN966X_SD6G40_MODE_QSGMII: 301 ret_val->lane_10bit_sel = 0; 302 if (ref125M) { 303 ret_val->mpll_multiplier = 40; 304 ret_val->ref_clkdiv2 = 0x1; 305 ret_val->tx_rate = 0x0; 306 ret_val->rx_rate = 0x0; 307 } else { 308 ret_val->mpll_multiplier = 100; 309 ret_val->ref_clkdiv2 = 0x0; 310 ret_val->tx_rate = 0x0; 311 ret_val->rx_rate = 0x0; 312 } 313 break; 314 315 case LAN966X_SD6G40_MODE_SGMII: 316 ret_val->lane_10bit_sel = 1; 317 if (ref125M) { 318 ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 50 : 40; 319 ret_val->ref_clkdiv2 = 0x1; 320 ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2; 321 ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2; 322 } else { 323 ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 125 : 100; 324 ret_val->ref_clkdiv2 = 0x0; 325 ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2; 326 ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2; 327 } 328 break; 329 330 default: 331 return -EOPNOTSUPP; 332 } 333 334 return 0; 335 } 336 337 static int lan966x_calc_sd6g40_setup_lane(struct serdes_macro *macro, 338 struct lan966x_sd6g40_setup_args config, 339 struct lan966x_sd6g40_setup *ret_val) 340 { 341 struct lan966x_sd6g40_mode_args sd6g40_mode; 342 struct lan966x_sd6g40_mode_args *mode_args = &sd6g40_mode; 343 int ret; 344 345 ret = lan966x_sd6g40_get_conf_from_mode(macro, config.mode, 346 config.refclk125M, mode_args); 347 if (ret) 348 return ret; 349 350 ret_val->lane_10bit_sel = mode_args->lane_10bit_sel; 351 ret_val->rx_rate = mode_args->rx_rate; 352 ret_val->tx_rate = mode_args->tx_rate; 353 ret_val->mpll_multiplier = mode_args->mpll_multiplier; 354 ret_val->ref_clkdiv2 = mode_args->ref_clkdiv2; 355 ret_val->rx_term_en = 0; 356 357 if (config.tx2rx_loop == LAN966X_SD6G40_LTX2RX) 358 ret_val->lane_loopbk_en = 1; 359 else 360 ret_val->lane_loopbk_en = 0; 361 362 ret_val->tx_invert = !!config.txinvert; 363 ret_val->rx_invert = !!config.rxinvert; 364 365 return 0; 366 } 367 368 static int lan966x_sd6g40_setup_lane(struct serdes_macro *macro, 369 struct lan966x_sd6g40_setup_args config, 370 u32 idx) 371 { 372 struct lan966x_sd6g40_setup calc_results = {}; 373 int ret; 374 375 ret = lan966x_calc_sd6g40_setup_lane(macro, config, &calc_results); 376 if (ret) 377 return ret; 378 379 return lan966x_sd6g40_reg_cfg(macro, &calc_results, idx); 380 } 381 382 static int lan966x_sd6g40_setup(struct serdes_macro *macro, u32 idx, int mode) 383 { 384 struct lan966x_sd6g40_setup_args conf = {}; 385 386 conf.refclk125M = macro->ctrl->ref125; 387 388 if (mode == PHY_INTERFACE_MODE_QSGMII) 389 conf.mode = LAN966X_SD6G40_MODE_QSGMII; 390 else 391 conf.mode = LAN966X_SD6G40_MODE_SGMII; 392 393 return lan966x_sd6g40_setup_lane(macro, conf, idx); 394 } 395 396 static int lan966x_rgmii_setup(struct serdes_macro *macro, u32 idx, int mode) 397 { 398 bool tx_delay = false; 399 bool rx_delay = false; 400 401 /* Configure RGMII */ 402 lan_rmw(HSIO_RGMII_CFG_RGMII_RX_RST_SET(0) | 403 HSIO_RGMII_CFG_RGMII_TX_RST_SET(0) | 404 HSIO_RGMII_CFG_TX_CLK_CFG_SET(macro->speed == SPEED_1000 ? 1 : 405 macro->speed == SPEED_100 ? 2 : 406 macro->speed == SPEED_10 ? 3 : 0), 407 HSIO_RGMII_CFG_RGMII_RX_RST | 408 HSIO_RGMII_CFG_RGMII_TX_RST | 409 HSIO_RGMII_CFG_TX_CLK_CFG, 410 macro->ctrl->regs, HSIO_RGMII_CFG(idx)); 411 412 if (mode == PHY_INTERFACE_MODE_RGMII || 413 mode == PHY_INTERFACE_MODE_RGMII_TXID) 414 rx_delay = true; 415 416 if (mode == PHY_INTERFACE_MODE_RGMII || 417 mode == PHY_INTERFACE_MODE_RGMII_RXID) 418 tx_delay = true; 419 420 /* Setup DLL configuration */ 421 lan_rmw(HSIO_DLL_CFG_DLL_RST_SET(0) | 422 HSIO_DLL_CFG_DLL_ENA_SET(rx_delay), 423 HSIO_DLL_CFG_DLL_RST | 424 HSIO_DLL_CFG_DLL_ENA, 425 macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x0 : 0x2)); 426 427 lan_rmw(HSIO_DLL_CFG_DELAY_ENA_SET(rx_delay), 428 HSIO_DLL_CFG_DELAY_ENA, 429 macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x0 : 0x2)); 430 431 lan_rmw(HSIO_DLL_CFG_DLL_RST_SET(0) | 432 HSIO_DLL_CFG_DLL_ENA_SET(tx_delay), 433 HSIO_DLL_CFG_DLL_RST | 434 HSIO_DLL_CFG_DLL_ENA, 435 macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x1 : 0x3)); 436 437 lan_rmw(HSIO_DLL_CFG_DELAY_ENA_SET(tx_delay), 438 HSIO_DLL_CFG_DELAY_ENA, 439 macro->ctrl->regs, HSIO_DLL_CFG(idx == 0 ? 0x1 : 0x3)); 440 441 return 0; 442 } 443 444 static int serdes_set_speed(struct phy *phy, int speed) 445 { 446 struct serdes_macro *macro = phy_get_drvdata(phy); 447 448 if (!phy_interface_mode_is_rgmii(macro->mode)) 449 return 0; 450 451 macro->speed = speed; 452 lan966x_rgmii_setup(macro, macro->idx - (SERDES6G_MAX + 1), macro->mode); 453 454 return 0; 455 } 456 457 static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) 458 { 459 struct serdes_macro *macro = phy_get_drvdata(phy); 460 unsigned int i; 461 int val; 462 463 /* As of now only PHY_MODE_ETHERNET is supported */ 464 if (mode != PHY_MODE_ETHERNET) 465 return -EOPNOTSUPP; 466 467 if (submode == PHY_INTERFACE_MODE_2500BASEX) 468 macro->speed = SPEED_2500; 469 else 470 macro->speed = SPEED_1000; 471 472 if (submode == PHY_INTERFACE_MODE_1000BASEX || 473 submode == PHY_INTERFACE_MODE_2500BASEX) 474 submode = PHY_INTERFACE_MODE_SGMII; 475 476 if (submode == PHY_INTERFACE_MODE_QUSGMII) 477 submode = PHY_INTERFACE_MODE_QSGMII; 478 479 for (i = 0; i < ARRAY_SIZE(lan966x_serdes_muxes); i++) { 480 if (macro->idx != lan966x_serdes_muxes[i].idx || 481 mode != lan966x_serdes_muxes[i].mode || 482 submode != lan966x_serdes_muxes[i].submode || 483 macro->port != lan966x_serdes_muxes[i].port) 484 continue; 485 486 val = readl(macro->ctrl->regs + lan_offset(HSIO_HW_CFG)); 487 val |= lan966x_serdes_muxes[i].mux; 488 lan_rmw(val, lan966x_serdes_muxes[i].mask, 489 macro->ctrl->regs, HSIO_HW_CFG); 490 491 macro->mode = lan966x_serdes_muxes[i].submode; 492 493 if (macro->idx < CU_MAX) 494 return 0; 495 496 if (macro->idx < SERDES6G_MAX) 497 return lan966x_sd6g40_setup(macro, 498 macro->idx - (CU_MAX + 1), 499 macro->mode); 500 501 if (macro->idx < RGMII_MAX) 502 return lan966x_rgmii_setup(macro, 503 macro->idx - (SERDES6G_MAX + 1), 504 macro->mode); 505 506 return -EOPNOTSUPP; 507 } 508 509 return -EINVAL; 510 } 511 512 static const struct phy_ops serdes_ops = { 513 .set_mode = serdes_set_mode, 514 .set_speed = serdes_set_speed, 515 .owner = THIS_MODULE, 516 }; 517 518 static struct phy *serdes_simple_xlate(struct device *dev, 519 struct of_phandle_args *args) 520 { 521 struct serdes_ctrl *ctrl = dev_get_drvdata(dev); 522 unsigned int port, idx, i; 523 524 if (args->args_count != 2) 525 return ERR_PTR(-EINVAL); 526 527 port = args->args[0]; 528 idx = args->args[1]; 529 530 for (i = 0; i < SERDES_MAX; i++) { 531 struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]); 532 533 if (idx != macro->idx) 534 continue; 535 536 macro->port = port; 537 return ctrl->phys[i]; 538 } 539 540 return ERR_PTR(-ENODEV); 541 } 542 543 static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy) 544 { 545 struct serdes_macro *macro; 546 547 *phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops); 548 if (IS_ERR(*phy)) 549 return PTR_ERR(*phy); 550 551 macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL); 552 if (!macro) 553 return -ENOMEM; 554 555 macro->idx = idx; 556 macro->ctrl = ctrl; 557 macro->port = -1; 558 559 phy_set_drvdata(*phy, macro); 560 561 return 0; 562 } 563 564 static int serdes_probe(struct platform_device *pdev) 565 { 566 struct phy_provider *provider; 567 struct serdes_ctrl *ctrl; 568 void __iomem *hw_stat; 569 unsigned int i; 570 u32 val; 571 int ret; 572 573 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); 574 if (!ctrl) 575 return -ENOMEM; 576 577 ctrl->dev = &pdev->dev; 578 ctrl->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 579 if (IS_ERR(ctrl->regs)) 580 return PTR_ERR(ctrl->regs); 581 582 hw_stat = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 583 if (IS_ERR(hw_stat)) 584 return PTR_ERR(hw_stat); 585 586 for (i = 0; i < SERDES_MAX; i++) { 587 ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]); 588 if (ret) 589 return ret; 590 } 591 592 val = readl(hw_stat); 593 val = FIELD_GET(PLL_CONF_MASK, val); 594 ctrl->ref125 = (val == PLL_CONF_125MHZ || 595 val == PLL_CONF_SERDES_125MHZ); 596 597 dev_set_drvdata(&pdev->dev, ctrl); 598 599 provider = devm_of_phy_provider_register(ctrl->dev, 600 serdes_simple_xlate); 601 602 return PTR_ERR_OR_ZERO(provider); 603 } 604 605 static const struct of_device_id serdes_ids[] = { 606 { .compatible = "microchip,lan966x-serdes", }, 607 {}, 608 }; 609 MODULE_DEVICE_TABLE(of, serdes_ids); 610 611 static struct platform_driver mscc_lan966x_serdes = { 612 .probe = serdes_probe, 613 .driver = { 614 .name = "microchip,lan966x-serdes", 615 .of_match_table = of_match_ptr(serdes_ids), 616 }, 617 }; 618 619 module_platform_driver(mscc_lan966x_serdes); 620 621 MODULE_DESCRIPTION("Microchip lan966x switch serdes driver"); 622 MODULE_AUTHOR("Horatiu Vultur <horatiu.vultur@microchip.com>"); 623 MODULE_LICENSE("GPL v2"); 624