1c1eb8f83SChunfeng Yun // SPDX-License-Identifier: GPL-2.0
2c1eb8f83SChunfeng Yun /*
3c1eb8f83SChunfeng Yun * MediaTek USB3.1 gen2 xsphy Driver
4c1eb8f83SChunfeng Yun *
5c1eb8f83SChunfeng Yun * Copyright (c) 2018 MediaTek Inc.
6c1eb8f83SChunfeng Yun * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
7c1eb8f83SChunfeng Yun *
8c1eb8f83SChunfeng Yun */
9c1eb8f83SChunfeng Yun
10c1eb8f83SChunfeng Yun #include <dt-bindings/phy/phy.h>
11c1eb8f83SChunfeng Yun #include <linux/clk.h>
12c1eb8f83SChunfeng Yun #include <linux/delay.h>
13c1eb8f83SChunfeng Yun #include <linux/iopoll.h>
14c1eb8f83SChunfeng Yun #include <linux/module.h>
15c1eb8f83SChunfeng Yun #include <linux/of_address.h>
16c1eb8f83SChunfeng Yun #include <linux/phy/phy.h>
17c1eb8f83SChunfeng Yun #include <linux/platform_device.h>
18c1eb8f83SChunfeng Yun
199520bbf3SChunfeng Yun #include "phy-mtk-io.h"
209520bbf3SChunfeng Yun
21c1eb8f83SChunfeng Yun /* u2 phy banks */
22c1eb8f83SChunfeng Yun #define SSUSB_SIFSLV_MISC 0x000
23c1eb8f83SChunfeng Yun #define SSUSB_SIFSLV_U2FREQ 0x100
24c1eb8f83SChunfeng Yun #define SSUSB_SIFSLV_U2PHY_COM 0x300
25c1eb8f83SChunfeng Yun
26c1eb8f83SChunfeng Yun /* u3 phy shared banks */
27c1eb8f83SChunfeng Yun #define SSPXTP_SIFSLV_DIG_GLB 0x000
28c1eb8f83SChunfeng Yun #define SSPXTP_SIFSLV_PHYA_GLB 0x100
29c1eb8f83SChunfeng Yun
30c1eb8f83SChunfeng Yun /* u3 phy banks */
31c1eb8f83SChunfeng Yun #define SSPXTP_SIFSLV_DIG_LN_TOP 0x000
32c1eb8f83SChunfeng Yun #define SSPXTP_SIFSLV_DIG_LN_TX0 0x100
33c1eb8f83SChunfeng Yun #define SSPXTP_SIFSLV_DIG_LN_RX0 0x200
34c1eb8f83SChunfeng Yun #define SSPXTP_SIFSLV_DIG_LN_DAIF 0x300
35c1eb8f83SChunfeng Yun #define SSPXTP_SIFSLV_PHYA_LN 0x400
36c1eb8f83SChunfeng Yun
37c1eb8f83SChunfeng Yun #define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00)
38c1eb8f83SChunfeng Yun #define P2F_RG_FREQDET_EN BIT(24)
39c1eb8f83SChunfeng Yun #define P2F_RG_CYCLECNT GENMASK(23, 0)
40c1eb8f83SChunfeng Yun
41c1eb8f83SChunfeng Yun #define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
42c1eb8f83SChunfeng Yun
43c1eb8f83SChunfeng Yun #define XSP_U2FREQ_FMMONR1 ((SSUSB_SIFSLV_U2FREQ) + 0x10)
44c1eb8f83SChunfeng Yun #define P2F_RG_FRCK_EN BIT(8)
45c1eb8f83SChunfeng Yun #define P2F_USB_FM_VALID BIT(0)
46c1eb8f83SChunfeng Yun
47c1eb8f83SChunfeng Yun #define XSP_USBPHYACR0 ((SSUSB_SIFSLV_U2PHY_COM) + 0x00)
48c1eb8f83SChunfeng Yun #define P2A0_RG_INTR_EN BIT(5)
49c1eb8f83SChunfeng Yun
50c1eb8f83SChunfeng Yun #define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
51c1eb8f83SChunfeng Yun #define P2A1_RG_INTR_CAL GENMASK(23, 19)
52c1eb8f83SChunfeng Yun #define P2A1_RG_VRT_SEL GENMASK(14, 12)
53c1eb8f83SChunfeng Yun #define P2A1_RG_TERM_SEL GENMASK(10, 8)
54c1eb8f83SChunfeng Yun
55c1eb8f83SChunfeng Yun #define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
56c1eb8f83SChunfeng Yun #define P2A5_RG_HSTX_SRCAL_EN BIT(15)
57c1eb8f83SChunfeng Yun #define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
58c1eb8f83SChunfeng Yun
59c1eb8f83SChunfeng Yun #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
60c1eb8f83SChunfeng Yun #define P2A6_RG_BC11_SW_EN BIT(23)
61c1eb8f83SChunfeng Yun #define P2A6_RG_OTG_VBUSCMP_EN BIT(20)
62c1eb8f83SChunfeng Yun
63c1eb8f83SChunfeng Yun #define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
64c1eb8f83SChunfeng Yun #define P2D_FORCE_IDDIG BIT(9)
65c1eb8f83SChunfeng Yun #define P2D_RG_VBUSVALID BIT(5)
66c1eb8f83SChunfeng Yun #define P2D_RG_SESSEND BIT(4)
67c1eb8f83SChunfeng Yun #define P2D_RG_AVALID BIT(2)
68c1eb8f83SChunfeng Yun #define P2D_RG_IDDIG BIT(1)
69c1eb8f83SChunfeng Yun
70c1eb8f83SChunfeng Yun #define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
71c1eb8f83SChunfeng Yun #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)
72c1eb8f83SChunfeng Yun
73c1eb8f83SChunfeng Yun #define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
74c1eb8f83SChunfeng Yun #define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)
75c1eb8f83SChunfeng Yun
76c1eb8f83SChunfeng Yun #define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
77c1eb8f83SChunfeng Yun #define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)
78c1eb8f83SChunfeng Yun
79c1eb8f83SChunfeng Yun #define XSP_REF_CLK 26 /* MHZ */
80c1eb8f83SChunfeng Yun #define XSP_SLEW_RATE_COEF 17
81c1eb8f83SChunfeng Yun #define XSP_SR_COEF_DIVISOR 1000
82c1eb8f83SChunfeng Yun #define XSP_FM_DET_CYCLE_CNT 1024
83c1eb8f83SChunfeng Yun
84c1eb8f83SChunfeng Yun struct xsphy_instance {
85c1eb8f83SChunfeng Yun struct phy *phy;
86c1eb8f83SChunfeng Yun void __iomem *port_base;
87c1eb8f83SChunfeng Yun struct clk *ref_clk; /* reference clock of anolog phy */
88c1eb8f83SChunfeng Yun u32 index;
89c1eb8f83SChunfeng Yun u32 type;
90c1eb8f83SChunfeng Yun /* only for HQA test */
91c1eb8f83SChunfeng Yun int efuse_intr;
92c1eb8f83SChunfeng Yun int efuse_tx_imp;
93c1eb8f83SChunfeng Yun int efuse_rx_imp;
94c1eb8f83SChunfeng Yun /* u2 eye diagram */
95c1eb8f83SChunfeng Yun int eye_src;
96c1eb8f83SChunfeng Yun int eye_vrt;
97c1eb8f83SChunfeng Yun int eye_term;
98c1eb8f83SChunfeng Yun };
99c1eb8f83SChunfeng Yun
100c1eb8f83SChunfeng Yun struct mtk_xsphy {
101c1eb8f83SChunfeng Yun struct device *dev;
102c1eb8f83SChunfeng Yun void __iomem *glb_base; /* only shared u3 sif */
103c1eb8f83SChunfeng Yun struct xsphy_instance **phys;
104c1eb8f83SChunfeng Yun int nphys;
105c1eb8f83SChunfeng Yun int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
106c1eb8f83SChunfeng Yun int src_coef; /* coefficient for slew rate calibrate */
107c1eb8f83SChunfeng Yun };
108c1eb8f83SChunfeng Yun
u2_phy_slew_rate_calibrate(struct mtk_xsphy * xsphy,struct xsphy_instance * inst)109c1eb8f83SChunfeng Yun static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
110c1eb8f83SChunfeng Yun struct xsphy_instance *inst)
111c1eb8f83SChunfeng Yun {
112c1eb8f83SChunfeng Yun void __iomem *pbase = inst->port_base;
113c1eb8f83SChunfeng Yun int calib_val;
114c1eb8f83SChunfeng Yun int fm_out;
115c1eb8f83SChunfeng Yun u32 tmp;
116c1eb8f83SChunfeng Yun
117c1eb8f83SChunfeng Yun /* use force value */
118c1eb8f83SChunfeng Yun if (inst->eye_src)
119c1eb8f83SChunfeng Yun return;
120c1eb8f83SChunfeng Yun
121c1eb8f83SChunfeng Yun /* enable USB ring oscillator */
1229520bbf3SChunfeng Yun mtk_phy_set_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
123c1eb8f83SChunfeng Yun udelay(1); /* wait clock stable */
124c1eb8f83SChunfeng Yun
125c1eb8f83SChunfeng Yun /* enable free run clock */
1269520bbf3SChunfeng Yun mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
127c1eb8f83SChunfeng Yun
128c1eb8f83SChunfeng Yun /* set cycle count as 1024 */
129*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,
130*c221baa3SChunfeng Yun XSP_FM_DET_CYCLE_CNT);
131c1eb8f83SChunfeng Yun
132c1eb8f83SChunfeng Yun /* enable frequency meter */
1339520bbf3SChunfeng Yun mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
134c1eb8f83SChunfeng Yun
135c1eb8f83SChunfeng Yun /* ignore return value */
136c1eb8f83SChunfeng Yun readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp,
137c1eb8f83SChunfeng Yun (tmp & P2F_USB_FM_VALID), 10, 200);
138c1eb8f83SChunfeng Yun
139c1eb8f83SChunfeng Yun fm_out = readl(pbase + XSP_U2FREQ_MMONR0);
140c1eb8f83SChunfeng Yun
141c1eb8f83SChunfeng Yun /* disable frequency meter */
1429520bbf3SChunfeng Yun mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
143c1eb8f83SChunfeng Yun
144c1eb8f83SChunfeng Yun /* disable free run clock */
1459520bbf3SChunfeng Yun mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
146c1eb8f83SChunfeng Yun
147c1eb8f83SChunfeng Yun if (fm_out) {
148c1eb8f83SChunfeng Yun /* (1024 / FM_OUT) x reference clock frequency x coefficient */
149c1eb8f83SChunfeng Yun tmp = xsphy->src_ref_clk * xsphy->src_coef;
150c1eb8f83SChunfeng Yun tmp = (tmp * XSP_FM_DET_CYCLE_CNT) / fm_out;
151c1eb8f83SChunfeng Yun calib_val = DIV_ROUND_CLOSEST(tmp, XSP_SR_COEF_DIVISOR);
152c1eb8f83SChunfeng Yun } else {
153c1eb8f83SChunfeng Yun /* if FM detection fail, set default value */
154c1eb8f83SChunfeng Yun calib_val = 3;
155c1eb8f83SChunfeng Yun }
156c1eb8f83SChunfeng Yun dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
157c1eb8f83SChunfeng Yun inst->index, fm_out, calib_val,
158c1eb8f83SChunfeng Yun xsphy->src_ref_clk, xsphy->src_coef);
159c1eb8f83SChunfeng Yun
160c1eb8f83SChunfeng Yun /* set HS slew rate */
161*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val);
162c1eb8f83SChunfeng Yun
163c1eb8f83SChunfeng Yun /* disable USB ring oscillator */
1649520bbf3SChunfeng Yun mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
165c1eb8f83SChunfeng Yun }
166c1eb8f83SChunfeng Yun
u2_phy_instance_init(struct mtk_xsphy * xsphy,struct xsphy_instance * inst)167c1eb8f83SChunfeng Yun static void u2_phy_instance_init(struct mtk_xsphy *xsphy,
168c1eb8f83SChunfeng Yun struct xsphy_instance *inst)
169c1eb8f83SChunfeng Yun {
170c1eb8f83SChunfeng Yun void __iomem *pbase = inst->port_base;
171c1eb8f83SChunfeng Yun
172c1eb8f83SChunfeng Yun /* DP/DM BC1.1 path Disable */
1739520bbf3SChunfeng Yun mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN);
174c1eb8f83SChunfeng Yun
1759520bbf3SChunfeng Yun mtk_phy_set_bits(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN);
176c1eb8f83SChunfeng Yun }
177c1eb8f83SChunfeng Yun
u2_phy_instance_power_on(struct mtk_xsphy * xsphy,struct xsphy_instance * inst)178c1eb8f83SChunfeng Yun static void u2_phy_instance_power_on(struct mtk_xsphy *xsphy,
179c1eb8f83SChunfeng Yun struct xsphy_instance *inst)
180c1eb8f83SChunfeng Yun {
181c1eb8f83SChunfeng Yun void __iomem *pbase = inst->port_base;
182c1eb8f83SChunfeng Yun u32 index = inst->index;
183c1eb8f83SChunfeng Yun
1849520bbf3SChunfeng Yun mtk_phy_set_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);
185c1eb8f83SChunfeng Yun
1869520bbf3SChunfeng Yun mtk_phy_update_bits(pbase + XSP_U2PHYDTM1,
1879520bbf3SChunfeng Yun P2D_RG_VBUSVALID | P2D_RG_AVALID | P2D_RG_SESSEND,
1889520bbf3SChunfeng Yun P2D_RG_VBUSVALID | P2D_RG_AVALID);
189c1eb8f83SChunfeng Yun
190c1eb8f83SChunfeng Yun dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
191c1eb8f83SChunfeng Yun }
192c1eb8f83SChunfeng Yun
u2_phy_instance_power_off(struct mtk_xsphy * xsphy,struct xsphy_instance * inst)193c1eb8f83SChunfeng Yun static void u2_phy_instance_power_off(struct mtk_xsphy *xsphy,
194c1eb8f83SChunfeng Yun struct xsphy_instance *inst)
195c1eb8f83SChunfeng Yun {
196c1eb8f83SChunfeng Yun void __iomem *pbase = inst->port_base;
197c1eb8f83SChunfeng Yun u32 index = inst->index;
198c1eb8f83SChunfeng Yun
1999520bbf3SChunfeng Yun mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);
200c1eb8f83SChunfeng Yun
2019520bbf3SChunfeng Yun mtk_phy_update_bits(pbase + XSP_U2PHYDTM1,
2029520bbf3SChunfeng Yun P2D_RG_VBUSVALID | P2D_RG_AVALID | P2D_RG_SESSEND,
2039520bbf3SChunfeng Yun P2D_RG_SESSEND);
204c1eb8f83SChunfeng Yun
205c1eb8f83SChunfeng Yun dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
206c1eb8f83SChunfeng Yun }
207c1eb8f83SChunfeng Yun
u2_phy_instance_set_mode(struct mtk_xsphy * xsphy,struct xsphy_instance * inst,enum phy_mode mode)208c1eb8f83SChunfeng Yun static void u2_phy_instance_set_mode(struct mtk_xsphy *xsphy,
209c1eb8f83SChunfeng Yun struct xsphy_instance *inst,
210c1eb8f83SChunfeng Yun enum phy_mode mode)
211c1eb8f83SChunfeng Yun {
212c1eb8f83SChunfeng Yun u32 tmp;
213c1eb8f83SChunfeng Yun
214c1eb8f83SChunfeng Yun tmp = readl(inst->port_base + XSP_U2PHYDTM1);
215c1eb8f83SChunfeng Yun switch (mode) {
216c1eb8f83SChunfeng Yun case PHY_MODE_USB_DEVICE:
217c1eb8f83SChunfeng Yun tmp |= P2D_FORCE_IDDIG | P2D_RG_IDDIG;
218c1eb8f83SChunfeng Yun break;
219c1eb8f83SChunfeng Yun case PHY_MODE_USB_HOST:
220c1eb8f83SChunfeng Yun tmp |= P2D_FORCE_IDDIG;
221c1eb8f83SChunfeng Yun tmp &= ~P2D_RG_IDDIG;
222c1eb8f83SChunfeng Yun break;
223c1eb8f83SChunfeng Yun case PHY_MODE_USB_OTG:
224c1eb8f83SChunfeng Yun tmp &= ~(P2D_FORCE_IDDIG | P2D_RG_IDDIG);
225c1eb8f83SChunfeng Yun break;
226c1eb8f83SChunfeng Yun default:
227c1eb8f83SChunfeng Yun return;
228c1eb8f83SChunfeng Yun }
229c1eb8f83SChunfeng Yun writel(tmp, inst->port_base + XSP_U2PHYDTM1);
230c1eb8f83SChunfeng Yun }
231c1eb8f83SChunfeng Yun
phy_parse_property(struct mtk_xsphy * xsphy,struct xsphy_instance * inst)232c1eb8f83SChunfeng Yun static void phy_parse_property(struct mtk_xsphy *xsphy,
233c1eb8f83SChunfeng Yun struct xsphy_instance *inst)
234c1eb8f83SChunfeng Yun {
235c1eb8f83SChunfeng Yun struct device *dev = &inst->phy->dev;
236c1eb8f83SChunfeng Yun
237c1eb8f83SChunfeng Yun switch (inst->type) {
238c1eb8f83SChunfeng Yun case PHY_TYPE_USB2:
239c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,efuse-intr",
240c1eb8f83SChunfeng Yun &inst->efuse_intr);
241c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,eye-src",
242c1eb8f83SChunfeng Yun &inst->eye_src);
243c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,eye-vrt",
244c1eb8f83SChunfeng Yun &inst->eye_vrt);
245c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,eye-term",
246c1eb8f83SChunfeng Yun &inst->eye_term);
247c1eb8f83SChunfeng Yun dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
248c1eb8f83SChunfeng Yun inst->efuse_intr, inst->eye_src,
249c1eb8f83SChunfeng Yun inst->eye_vrt, inst->eye_term);
250c1eb8f83SChunfeng Yun break;
251c1eb8f83SChunfeng Yun case PHY_TYPE_USB3:
252c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,efuse-intr",
253c1eb8f83SChunfeng Yun &inst->efuse_intr);
254c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,efuse-tx-imp",
255c1eb8f83SChunfeng Yun &inst->efuse_tx_imp);
256c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,efuse-rx-imp",
257c1eb8f83SChunfeng Yun &inst->efuse_rx_imp);
258c1eb8f83SChunfeng Yun dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",
259c1eb8f83SChunfeng Yun inst->efuse_intr, inst->efuse_tx_imp,
260c1eb8f83SChunfeng Yun inst->efuse_rx_imp);
261c1eb8f83SChunfeng Yun break;
262c1eb8f83SChunfeng Yun default:
263c1eb8f83SChunfeng Yun dev_err(xsphy->dev, "incompatible phy type\n");
264c1eb8f83SChunfeng Yun return;
265c1eb8f83SChunfeng Yun }
266c1eb8f83SChunfeng Yun }
267c1eb8f83SChunfeng Yun
u2_phy_props_set(struct mtk_xsphy * xsphy,struct xsphy_instance * inst)268c1eb8f83SChunfeng Yun static void u2_phy_props_set(struct mtk_xsphy *xsphy,
269c1eb8f83SChunfeng Yun struct xsphy_instance *inst)
270c1eb8f83SChunfeng Yun {
271c1eb8f83SChunfeng Yun void __iomem *pbase = inst->port_base;
272c1eb8f83SChunfeng Yun
2739520bbf3SChunfeng Yun if (inst->efuse_intr)
274*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,
275*c221baa3SChunfeng Yun inst->efuse_intr);
276c1eb8f83SChunfeng Yun
2779520bbf3SChunfeng Yun if (inst->eye_src)
278*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
279*c221baa3SChunfeng Yun inst->eye_src);
280c1eb8f83SChunfeng Yun
2819520bbf3SChunfeng Yun if (inst->eye_vrt)
282*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,
283*c221baa3SChunfeng Yun inst->eye_vrt);
284c1eb8f83SChunfeng Yun
2859520bbf3SChunfeng Yun if (inst->eye_term)
286*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
287*c221baa3SChunfeng Yun inst->eye_term);
288c1eb8f83SChunfeng Yun }
289c1eb8f83SChunfeng Yun
u3_phy_props_set(struct mtk_xsphy * xsphy,struct xsphy_instance * inst)290c1eb8f83SChunfeng Yun static void u3_phy_props_set(struct mtk_xsphy *xsphy,
291c1eb8f83SChunfeng Yun struct xsphy_instance *inst)
292c1eb8f83SChunfeng Yun {
293c1eb8f83SChunfeng Yun void __iomem *pbase = inst->port_base;
294c1eb8f83SChunfeng Yun
2959520bbf3SChunfeng Yun if (inst->efuse_intr)
296*c221baa3SChunfeng Yun mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00,
297*c221baa3SChunfeng Yun RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr);
298c1eb8f83SChunfeng Yun
2999520bbf3SChunfeng Yun if (inst->efuse_tx_imp)
300*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04,
301*c221baa3SChunfeng Yun RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp);
302c1eb8f83SChunfeng Yun
3039520bbf3SChunfeng Yun if (inst->efuse_rx_imp)
304*c221baa3SChunfeng Yun mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14,
305*c221baa3SChunfeng Yun RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
306c1eb8f83SChunfeng Yun }
307c1eb8f83SChunfeng Yun
mtk_phy_init(struct phy * phy)308c1eb8f83SChunfeng Yun static int mtk_phy_init(struct phy *phy)
309c1eb8f83SChunfeng Yun {
310c1eb8f83SChunfeng Yun struct xsphy_instance *inst = phy_get_drvdata(phy);
311c1eb8f83SChunfeng Yun struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
312c1eb8f83SChunfeng Yun int ret;
313c1eb8f83SChunfeng Yun
314c1eb8f83SChunfeng Yun ret = clk_prepare_enable(inst->ref_clk);
315c1eb8f83SChunfeng Yun if (ret) {
316c1eb8f83SChunfeng Yun dev_err(xsphy->dev, "failed to enable ref_clk\n");
317c1eb8f83SChunfeng Yun return ret;
318c1eb8f83SChunfeng Yun }
319c1eb8f83SChunfeng Yun
320c1eb8f83SChunfeng Yun switch (inst->type) {
321c1eb8f83SChunfeng Yun case PHY_TYPE_USB2:
322c1eb8f83SChunfeng Yun u2_phy_instance_init(xsphy, inst);
323c1eb8f83SChunfeng Yun u2_phy_props_set(xsphy, inst);
324c1eb8f83SChunfeng Yun break;
325c1eb8f83SChunfeng Yun case PHY_TYPE_USB3:
326c1eb8f83SChunfeng Yun u3_phy_props_set(xsphy, inst);
327c1eb8f83SChunfeng Yun break;
328c1eb8f83SChunfeng Yun default:
329c1eb8f83SChunfeng Yun dev_err(xsphy->dev, "incompatible phy type\n");
330c1eb8f83SChunfeng Yun clk_disable_unprepare(inst->ref_clk);
331c1eb8f83SChunfeng Yun return -EINVAL;
332c1eb8f83SChunfeng Yun }
333c1eb8f83SChunfeng Yun
334c1eb8f83SChunfeng Yun return 0;
335c1eb8f83SChunfeng Yun }
336c1eb8f83SChunfeng Yun
mtk_phy_power_on(struct phy * phy)337c1eb8f83SChunfeng Yun static int mtk_phy_power_on(struct phy *phy)
338c1eb8f83SChunfeng Yun {
339c1eb8f83SChunfeng Yun struct xsphy_instance *inst = phy_get_drvdata(phy);
340c1eb8f83SChunfeng Yun struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
341c1eb8f83SChunfeng Yun
342c1eb8f83SChunfeng Yun if (inst->type == PHY_TYPE_USB2) {
343c1eb8f83SChunfeng Yun u2_phy_instance_power_on(xsphy, inst);
344c1eb8f83SChunfeng Yun u2_phy_slew_rate_calibrate(xsphy, inst);
345c1eb8f83SChunfeng Yun }
346c1eb8f83SChunfeng Yun
347c1eb8f83SChunfeng Yun return 0;
348c1eb8f83SChunfeng Yun }
349c1eb8f83SChunfeng Yun
mtk_phy_power_off(struct phy * phy)350c1eb8f83SChunfeng Yun static int mtk_phy_power_off(struct phy *phy)
351c1eb8f83SChunfeng Yun {
352c1eb8f83SChunfeng Yun struct xsphy_instance *inst = phy_get_drvdata(phy);
353c1eb8f83SChunfeng Yun struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
354c1eb8f83SChunfeng Yun
355c1eb8f83SChunfeng Yun if (inst->type == PHY_TYPE_USB2)
356c1eb8f83SChunfeng Yun u2_phy_instance_power_off(xsphy, inst);
357c1eb8f83SChunfeng Yun
358c1eb8f83SChunfeng Yun return 0;
359c1eb8f83SChunfeng Yun }
360c1eb8f83SChunfeng Yun
mtk_phy_exit(struct phy * phy)361c1eb8f83SChunfeng Yun static int mtk_phy_exit(struct phy *phy)
362c1eb8f83SChunfeng Yun {
363c1eb8f83SChunfeng Yun struct xsphy_instance *inst = phy_get_drvdata(phy);
364c1eb8f83SChunfeng Yun
365c1eb8f83SChunfeng Yun clk_disable_unprepare(inst->ref_clk);
366c1eb8f83SChunfeng Yun return 0;
367c1eb8f83SChunfeng Yun }
368c1eb8f83SChunfeng Yun
mtk_phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)36979a5a18aSGrygorii Strashko static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
370c1eb8f83SChunfeng Yun {
371c1eb8f83SChunfeng Yun struct xsphy_instance *inst = phy_get_drvdata(phy);
372c1eb8f83SChunfeng Yun struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
373c1eb8f83SChunfeng Yun
374c1eb8f83SChunfeng Yun if (inst->type == PHY_TYPE_USB2)
375c1eb8f83SChunfeng Yun u2_phy_instance_set_mode(xsphy, inst, mode);
376c1eb8f83SChunfeng Yun
377c1eb8f83SChunfeng Yun return 0;
378c1eb8f83SChunfeng Yun }
379c1eb8f83SChunfeng Yun
mtk_phy_xlate(struct device * dev,struct of_phandle_args * args)380c1eb8f83SChunfeng Yun static struct phy *mtk_phy_xlate(struct device *dev,
381c1eb8f83SChunfeng Yun struct of_phandle_args *args)
382c1eb8f83SChunfeng Yun {
383c1eb8f83SChunfeng Yun struct mtk_xsphy *xsphy = dev_get_drvdata(dev);
384c1eb8f83SChunfeng Yun struct xsphy_instance *inst = NULL;
385c1eb8f83SChunfeng Yun struct device_node *phy_np = args->np;
386c1eb8f83SChunfeng Yun int index;
387c1eb8f83SChunfeng Yun
388c1eb8f83SChunfeng Yun if (args->args_count != 1) {
389c1eb8f83SChunfeng Yun dev_err(dev, "invalid number of cells in 'phy' property\n");
390c1eb8f83SChunfeng Yun return ERR_PTR(-EINVAL);
391c1eb8f83SChunfeng Yun }
392c1eb8f83SChunfeng Yun
393c1eb8f83SChunfeng Yun for (index = 0; index < xsphy->nphys; index++)
394c1eb8f83SChunfeng Yun if (phy_np == xsphy->phys[index]->phy->dev.of_node) {
395c1eb8f83SChunfeng Yun inst = xsphy->phys[index];
396c1eb8f83SChunfeng Yun break;
397c1eb8f83SChunfeng Yun }
398c1eb8f83SChunfeng Yun
399c1eb8f83SChunfeng Yun if (!inst) {
400c1eb8f83SChunfeng Yun dev_err(dev, "failed to find appropriate phy\n");
401c1eb8f83SChunfeng Yun return ERR_PTR(-EINVAL);
402c1eb8f83SChunfeng Yun }
403c1eb8f83SChunfeng Yun
404c1eb8f83SChunfeng Yun inst->type = args->args[0];
405c1eb8f83SChunfeng Yun if (!(inst->type == PHY_TYPE_USB2 ||
406c1eb8f83SChunfeng Yun inst->type == PHY_TYPE_USB3)) {
407c1eb8f83SChunfeng Yun dev_err(dev, "unsupported phy type: %d\n", inst->type);
408c1eb8f83SChunfeng Yun return ERR_PTR(-EINVAL);
409c1eb8f83SChunfeng Yun }
410c1eb8f83SChunfeng Yun
411c1eb8f83SChunfeng Yun phy_parse_property(xsphy, inst);
412c1eb8f83SChunfeng Yun
413c1eb8f83SChunfeng Yun return inst->phy;
414c1eb8f83SChunfeng Yun }
415c1eb8f83SChunfeng Yun
416c1eb8f83SChunfeng Yun static const struct phy_ops mtk_xsphy_ops = {
417c1eb8f83SChunfeng Yun .init = mtk_phy_init,
418c1eb8f83SChunfeng Yun .exit = mtk_phy_exit,
419c1eb8f83SChunfeng Yun .power_on = mtk_phy_power_on,
420c1eb8f83SChunfeng Yun .power_off = mtk_phy_power_off,
421c1eb8f83SChunfeng Yun .set_mode = mtk_phy_set_mode,
422c1eb8f83SChunfeng Yun .owner = THIS_MODULE,
423c1eb8f83SChunfeng Yun };
424c1eb8f83SChunfeng Yun
425c1eb8f83SChunfeng Yun static const struct of_device_id mtk_xsphy_id_table[] = {
426c1eb8f83SChunfeng Yun { .compatible = "mediatek,xsphy", },
427c1eb8f83SChunfeng Yun { },
428c1eb8f83SChunfeng Yun };
429c1eb8f83SChunfeng Yun MODULE_DEVICE_TABLE(of, mtk_xsphy_id_table);
430c1eb8f83SChunfeng Yun
mtk_xsphy_probe(struct platform_device * pdev)431c1eb8f83SChunfeng Yun static int mtk_xsphy_probe(struct platform_device *pdev)
432c1eb8f83SChunfeng Yun {
433c1eb8f83SChunfeng Yun struct device *dev = &pdev->dev;
434c1eb8f83SChunfeng Yun struct device_node *np = dev->of_node;
435c1eb8f83SChunfeng Yun struct device_node *child_np;
436c1eb8f83SChunfeng Yun struct phy_provider *provider;
437c1eb8f83SChunfeng Yun struct resource *glb_res;
438c1eb8f83SChunfeng Yun struct mtk_xsphy *xsphy;
439c1eb8f83SChunfeng Yun struct resource res;
440c1eb8f83SChunfeng Yun int port, retval;
441c1eb8f83SChunfeng Yun
442c1eb8f83SChunfeng Yun xsphy = devm_kzalloc(dev, sizeof(*xsphy), GFP_KERNEL);
443c1eb8f83SChunfeng Yun if (!xsphy)
444c1eb8f83SChunfeng Yun return -ENOMEM;
445c1eb8f83SChunfeng Yun
446c1eb8f83SChunfeng Yun xsphy->nphys = of_get_child_count(np);
447c1eb8f83SChunfeng Yun xsphy->phys = devm_kcalloc(dev, xsphy->nphys,
448c1eb8f83SChunfeng Yun sizeof(*xsphy->phys), GFP_KERNEL);
449c1eb8f83SChunfeng Yun if (!xsphy->phys)
450c1eb8f83SChunfeng Yun return -ENOMEM;
451c1eb8f83SChunfeng Yun
452c1eb8f83SChunfeng Yun xsphy->dev = dev;
453c1eb8f83SChunfeng Yun platform_set_drvdata(pdev, xsphy);
454c1eb8f83SChunfeng Yun
455c1eb8f83SChunfeng Yun glb_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
456c1eb8f83SChunfeng Yun /* optional, may not exist if no u3 phys */
457c1eb8f83SChunfeng Yun if (glb_res) {
458c1eb8f83SChunfeng Yun /* get banks shared by multiple u3 phys */
459c1eb8f83SChunfeng Yun xsphy->glb_base = devm_ioremap_resource(dev, glb_res);
460c1eb8f83SChunfeng Yun if (IS_ERR(xsphy->glb_base)) {
461c1eb8f83SChunfeng Yun dev_err(dev, "failed to remap glb regs\n");
462c1eb8f83SChunfeng Yun return PTR_ERR(xsphy->glb_base);
463c1eb8f83SChunfeng Yun }
464c1eb8f83SChunfeng Yun }
465c1eb8f83SChunfeng Yun
466c1eb8f83SChunfeng Yun xsphy->src_ref_clk = XSP_REF_CLK;
467c1eb8f83SChunfeng Yun xsphy->src_coef = XSP_SLEW_RATE_COEF;
468c1eb8f83SChunfeng Yun /* update parameters of slew rate calibrate if exist */
469c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
470c1eb8f83SChunfeng Yun &xsphy->src_ref_clk);
471c1eb8f83SChunfeng Yun device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);
472c1eb8f83SChunfeng Yun
473c1eb8f83SChunfeng Yun port = 0;
474c1eb8f83SChunfeng Yun for_each_child_of_node(np, child_np) {
475c1eb8f83SChunfeng Yun struct xsphy_instance *inst;
476c1eb8f83SChunfeng Yun struct phy *phy;
477c1eb8f83SChunfeng Yun
478c1eb8f83SChunfeng Yun inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
479c1eb8f83SChunfeng Yun if (!inst) {
480c1eb8f83SChunfeng Yun retval = -ENOMEM;
481c1eb8f83SChunfeng Yun goto put_child;
482c1eb8f83SChunfeng Yun }
483c1eb8f83SChunfeng Yun
484c1eb8f83SChunfeng Yun xsphy->phys[port] = inst;
485c1eb8f83SChunfeng Yun
486c1eb8f83SChunfeng Yun phy = devm_phy_create(dev, child_np, &mtk_xsphy_ops);
487c1eb8f83SChunfeng Yun if (IS_ERR(phy)) {
488c1eb8f83SChunfeng Yun dev_err(dev, "failed to create phy\n");
489c1eb8f83SChunfeng Yun retval = PTR_ERR(phy);
490c1eb8f83SChunfeng Yun goto put_child;
491c1eb8f83SChunfeng Yun }
492c1eb8f83SChunfeng Yun
493c1eb8f83SChunfeng Yun retval = of_address_to_resource(child_np, 0, &res);
494c1eb8f83SChunfeng Yun if (retval) {
495c1eb8f83SChunfeng Yun dev_err(dev, "failed to get address resource(id-%d)\n",
496c1eb8f83SChunfeng Yun port);
497c1eb8f83SChunfeng Yun goto put_child;
498c1eb8f83SChunfeng Yun }
499c1eb8f83SChunfeng Yun
500c1eb8f83SChunfeng Yun inst->port_base = devm_ioremap_resource(&phy->dev, &res);
501c1eb8f83SChunfeng Yun if (IS_ERR(inst->port_base)) {
502c1eb8f83SChunfeng Yun dev_err(dev, "failed to remap phy regs\n");
503c1eb8f83SChunfeng Yun retval = PTR_ERR(inst->port_base);
504c1eb8f83SChunfeng Yun goto put_child;
505c1eb8f83SChunfeng Yun }
506c1eb8f83SChunfeng Yun
507c1eb8f83SChunfeng Yun inst->phy = phy;
508c1eb8f83SChunfeng Yun inst->index = port;
509c1eb8f83SChunfeng Yun phy_set_drvdata(phy, inst);
510c1eb8f83SChunfeng Yun port++;
511c1eb8f83SChunfeng Yun
512c1eb8f83SChunfeng Yun inst->ref_clk = devm_clk_get(&phy->dev, "ref");
513c1eb8f83SChunfeng Yun if (IS_ERR(inst->ref_clk)) {
514c1eb8f83SChunfeng Yun dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
515c1eb8f83SChunfeng Yun retval = PTR_ERR(inst->ref_clk);
516c1eb8f83SChunfeng Yun goto put_child;
517c1eb8f83SChunfeng Yun }
518c1eb8f83SChunfeng Yun }
519c1eb8f83SChunfeng Yun
520c1eb8f83SChunfeng Yun provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
521c1eb8f83SChunfeng Yun return PTR_ERR_OR_ZERO(provider);
522c1eb8f83SChunfeng Yun
523c1eb8f83SChunfeng Yun put_child:
524c1eb8f83SChunfeng Yun of_node_put(child_np);
525c1eb8f83SChunfeng Yun return retval;
526c1eb8f83SChunfeng Yun }
527c1eb8f83SChunfeng Yun
528c1eb8f83SChunfeng Yun static struct platform_driver mtk_xsphy_driver = {
529c1eb8f83SChunfeng Yun .probe = mtk_xsphy_probe,
530c1eb8f83SChunfeng Yun .driver = {
531c1eb8f83SChunfeng Yun .name = "mtk-xsphy",
532c1eb8f83SChunfeng Yun .of_match_table = mtk_xsphy_id_table,
533c1eb8f83SChunfeng Yun },
534c1eb8f83SChunfeng Yun };
535c1eb8f83SChunfeng Yun
536c1eb8f83SChunfeng Yun module_platform_driver(mtk_xsphy_driver);
537c1eb8f83SChunfeng Yun
538c1eb8f83SChunfeng Yun MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
539c1eb8f83SChunfeng Yun MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");
540c1eb8f83SChunfeng Yun MODULE_LICENSE("GPL v2");
541