1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 5 * 6 */ 7 8 #include <dt-bindings/phy/phy.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 21 /* version V1 sub-banks offset base address */ 22 /* banks shared by multiple phys */ 23 #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ 24 #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ 25 #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ 26 /* u2 phy bank */ 27 #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 28 /* u3/pcie/sata phy banks */ 29 #define SSUSB_SIFSLV_V1_U3PHYD 0x000 30 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 31 32 /* version V2/V3 sub-banks offset base address */ 33 /* V3: U2FREQ is not used anymore, but reserved */ 34 /* u2 phy banks */ 35 #define SSUSB_SIFSLV_V2_MISC 0x000 36 #define SSUSB_SIFSLV_V2_U2FREQ 0x100 37 #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 38 /* u3/pcie/sata phy banks */ 39 #define SSUSB_SIFSLV_V2_SPLLC 0x000 40 #define SSUSB_SIFSLV_V2_CHIP 0x100 41 #define SSUSB_SIFSLV_V2_U3PHYD 0x200 42 #define SSUSB_SIFSLV_V2_U3PHYA 0x400 43 44 #define U3P_USBPHYACR0 0x000 45 #define PA0_RG_U2PLL_FORCE_ON BIT(15) 46 #define PA0_USB20_PLL_PREDIV GENMASK(7, 6) 47 #define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) 48 #define PA0_RG_USB20_INTR_EN BIT(5) 49 50 #define U3P_USBPHYACR1 0x004 51 #define PA1_RG_INTR_CAL GENMASK(23, 19) 52 #define PA1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19) 53 #define PA1_RG_VRT_SEL GENMASK(14, 12) 54 #define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12) 55 #define PA1_RG_TERM_SEL GENMASK(10, 8) 56 #define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8) 57 58 #define U3P_USBPHYACR2 0x008 59 #define PA2_RG_U2PLL_BW GENMASK(21, 19) 60 #define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19) 61 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) 62 63 #define U3P_USBPHYACR5 0x014 64 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) 65 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) 66 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) 67 #define PA5_RG_U2_HS_100U_U3_EN BIT(11) 68 69 #define U3P_USBPHYACR6 0x018 70 #define PA6_RG_U2_BC11_SW_EN BIT(23) 71 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) 72 #define PA6_RG_U2_DISCTH GENMASK(7, 4) 73 #define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) 74 #define PA6_RG_U2_SQTH GENMASK(3, 0) 75 #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) 76 77 #define U3P_U2PHYACR4 0x020 78 #define P2C_RG_USB20_GPIO_CTL BIT(9) 79 #define P2C_USB20_GPIO_MODE BIT(8) 80 #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) 81 82 #define U3P_U2PHYA_RESV 0x030 83 #define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b 84 #define P2R_RG_U2PLL_FBDIV_48M 0x3c0000 85 86 #define U3P_U2PHYA_RESV1 0x044 87 #define P2R_RG_U2PLL_REFCLK_SEL BIT(5) 88 #define P2R_RG_U2PLL_FRA_EN BIT(3) 89 90 #define U3D_U2PHYDCR0 0x060 91 #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) 92 93 #define U3P_U2PHYDTM0 0x068 94 #define P2C_FORCE_UART_EN BIT(26) 95 #define P2C_FORCE_DATAIN BIT(23) 96 #define P2C_FORCE_DM_PULLDOWN BIT(21) 97 #define P2C_FORCE_DP_PULLDOWN BIT(20) 98 #define P2C_FORCE_XCVRSEL BIT(19) 99 #define P2C_FORCE_SUSPENDM BIT(18) 100 #define P2C_FORCE_TERMSEL BIT(17) 101 #define P2C_RG_DATAIN GENMASK(13, 10) 102 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) 103 #define P2C_RG_DMPULLDOWN BIT(7) 104 #define P2C_RG_DPPULLDOWN BIT(6) 105 #define P2C_RG_XCVRSEL GENMASK(5, 4) 106 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) 107 #define P2C_RG_SUSPENDM BIT(3) 108 #define P2C_RG_TERMSEL BIT(2) 109 #define P2C_DTM0_PART_MASK \ 110 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ 111 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ 112 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ 113 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) 114 115 #define U3P_U2PHYDTM1 0x06C 116 #define P2C_RG_UART_EN BIT(16) 117 #define P2C_FORCE_IDDIG BIT(9) 118 #define P2C_RG_VBUSVALID BIT(5) 119 #define P2C_RG_SESSEND BIT(4) 120 #define P2C_RG_AVALID BIT(2) 121 #define P2C_RG_IDDIG BIT(1) 122 123 #define U3P_U2PHYBC12C 0x080 124 #define P2C_RG_CHGDT_EN BIT(0) 125 126 #define U3P_U3_CHIP_GPIO_CTLD 0x0c 127 #define P3C_REG_IP_SW_RST BIT(31) 128 #define P3C_MCU_BUS_CK_GATE_EN BIT(30) 129 #define P3C_FORCE_IP_SW_RST BIT(29) 130 131 #define U3P_U3_CHIP_GPIO_CTLE 0x10 132 #define P3C_RG_SWRST_U3_PHYD BIT(25) 133 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) 134 135 #define U3P_U3_PHYA_REG0 0x000 136 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) 137 #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) 138 139 #define U3P_U3_PHYA_REG1 0x004 140 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) 141 #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) 142 143 #define U3P_U3_PHYA_REG6 0x018 144 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) 145 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) 146 147 #define U3P_U3_PHYA_REG9 0x024 148 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) 149 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) 150 151 #define U3P_U3_PHYA_DA_REG0 0x100 152 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) 153 #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) 154 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) 155 #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) 156 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) 157 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) 158 159 #define U3P_U3_PHYA_DA_REG4 0x108 160 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) 161 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) 162 #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) 163 164 #define U3P_U3_PHYA_DA_REG5 0x10c 165 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) 166 #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) 167 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) 168 #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) 169 170 #define U3P_U3_PHYA_DA_REG6 0x110 171 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) 172 #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) 173 174 #define U3P_U3_PHYA_DA_REG7 0x114 175 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) 176 #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) 177 178 #define U3P_U3_PHYA_DA_REG20 0x13c 179 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) 180 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) 181 182 #define U3P_U3_PHYA_DA_REG25 0x148 183 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) 184 #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) 185 186 #define U3P_U3_PHYD_LFPS1 0x00c 187 #define P3D_RG_FWAKE_TH GENMASK(21, 16) 188 #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) 189 190 #define U3P_U3_PHYD_CDR1 0x05c 191 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 192 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) 193 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 194 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) 195 196 #define U3P_U3_PHYD_RXDET1 0x128 197 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 198 #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) 199 200 #define U3P_U3_PHYD_RXDET2 0x12c 201 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) 202 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) 203 204 #define U3P_SPLLC_XTALCTL3 0x018 205 #define XC3_RG_U3_XTAL_RX_PWD BIT(9) 206 #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) 207 208 #define U3P_U2FREQ_FMCR0 0x00 209 #define P2F_RG_MONCLK_SEL GENMASK(27, 26) 210 #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) 211 #define P2F_RG_FREQDET_EN BIT(24) 212 #define P2F_RG_CYCLECNT GENMASK(23, 0) 213 #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) 214 215 #define U3P_U2FREQ_VALUE 0x0c 216 217 #define U3P_U2FREQ_FMMONR1 0x10 218 #define P2F_USB_FM_VALID BIT(0) 219 #define P2F_RG_FRCK_EN BIT(8) 220 221 #define U3P_REF_CLK 26 /* MHZ */ 222 #define U3P_SLEW_RATE_COEF 28 223 #define U3P_SR_COEF_DIVISOR 1000 224 #define U3P_FM_DET_CYCLE_CNT 1024 225 226 /* SATA register setting */ 227 #define PHYD_CTRL_SIGNAL_MODE4 0x1c 228 /* CDR Charge Pump P-path current adjustment */ 229 #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) 230 #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) 231 #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) 232 #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) 233 234 #define PHYD_DESIGN_OPTION2 0x24 235 /* Symbol lock count selection */ 236 #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) 237 #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) 238 239 #define PHYD_DESIGN_OPTION9 0x40 240 /* COMWAK GAP width window */ 241 #define RG_TG_MAX_MSK GENMASK(20, 16) 242 #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) 243 /* COMINIT GAP width window */ 244 #define RG_T2_MAX_MSK GENMASK(13, 8) 245 #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) 246 /* COMWAK GAP width window */ 247 #define RG_TG_MIN_MSK GENMASK(7, 5) 248 #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) 249 /* COMINIT GAP width window */ 250 #define RG_T2_MIN_MSK GENMASK(4, 0) 251 #define RG_T2_MIN_VAL(x) (0x1f & (x)) 252 253 #define ANA_RG_CTRL_SIGNAL1 0x4c 254 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ 255 #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) 256 #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) 257 258 #define ANA_RG_CTRL_SIGNAL4 0x58 259 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) 260 #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) 261 /* Loop filter R1 resistance adjustment for Gen1 speed */ 262 #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) 263 #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) 264 265 #define ANA_RG_CTRL_SIGNAL6 0x60 266 /* I-path capacitance adjustment for Gen1 */ 267 #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) 268 #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) 269 #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) 270 #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) 271 272 #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c 273 /* RX Gen1 LEQ tuning step */ 274 #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) 275 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) 276 277 #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 278 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) 279 #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) 280 281 #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc 282 #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) 283 #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) 284 285 /* PHY switch between pcie/usb3/sgmii/sata */ 286 #define USB_PHY_SWITCH_CTRL 0x0 287 #define RG_PHY_SW_TYPE GENMASK(3, 0) 288 #define RG_PHY_SW_PCIE 0x0 289 #define RG_PHY_SW_USB3 0x1 290 #define RG_PHY_SW_SGMII 0x2 291 #define RG_PHY_SW_SATA 0x3 292 293 #define TPHY_CLKS_CNT 2 294 295 enum mtk_phy_version { 296 MTK_PHY_V1 = 1, 297 MTK_PHY_V2, 298 MTK_PHY_V3, 299 }; 300 301 struct mtk_phy_pdata { 302 /* avoid RX sensitivity level degradation only for mt8173 */ 303 bool avoid_rx_sen_degradation; 304 /* 305 * workaround only for mt8195, HW fix it for others of V3, 306 * u2phy should use integer mode instead of fractional mode of 307 * 48M PLL, fix it by switching PLL to 26M from default 48M 308 */ 309 bool sw_pll_48m_to_26m; 310 enum mtk_phy_version version; 311 }; 312 313 struct u2phy_banks { 314 void __iomem *misc; 315 void __iomem *fmreg; 316 void __iomem *com; 317 }; 318 319 struct u3phy_banks { 320 void __iomem *spllc; 321 void __iomem *chip; 322 void __iomem *phyd; /* include u3phyd_bank2 */ 323 void __iomem *phya; /* include u3phya_da */ 324 }; 325 326 struct mtk_phy_instance { 327 struct phy *phy; 328 void __iomem *port_base; 329 union { 330 struct u2phy_banks u2_banks; 331 struct u3phy_banks u3_banks; 332 }; 333 struct clk_bulk_data clks[TPHY_CLKS_CNT]; 334 u32 index; 335 u32 type; 336 struct regmap *type_sw; 337 u32 type_sw_reg; 338 u32 type_sw_index; 339 int eye_src; 340 int eye_vrt; 341 int eye_term; 342 int intr; 343 int discth; 344 bool bc12_en; 345 }; 346 347 struct mtk_tphy { 348 struct device *dev; 349 void __iomem *sif_base; /* only shared sif */ 350 const struct mtk_phy_pdata *pdata; 351 struct mtk_phy_instance **phys; 352 int nphys; 353 int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ 354 int src_coef; /* coefficient for slew rate calibrate */ 355 }; 356 357 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, 358 struct mtk_phy_instance *instance) 359 { 360 struct u2phy_banks *u2_banks = &instance->u2_banks; 361 void __iomem *fmreg = u2_banks->fmreg; 362 void __iomem *com = u2_banks->com; 363 int calibration_val; 364 int fm_out; 365 u32 tmp; 366 367 /* HW V3 doesn't support slew rate cal anymore */ 368 if (tphy->pdata->version == MTK_PHY_V3) 369 return; 370 371 /* use force value */ 372 if (instance->eye_src) 373 return; 374 375 /* enable USB ring oscillator */ 376 tmp = readl(com + U3P_USBPHYACR5); 377 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; 378 writel(tmp, com + U3P_USBPHYACR5); 379 udelay(1); 380 381 /*enable free run clock */ 382 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 383 tmp |= P2F_RG_FRCK_EN; 384 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 385 386 /* set cycle count as 1024, and select u2 channel */ 387 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 388 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); 389 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); 390 if (tphy->pdata->version == MTK_PHY_V1) 391 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); 392 393 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 394 395 /* enable frequency meter */ 396 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 397 tmp |= P2F_RG_FREQDET_EN; 398 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 399 400 /* ignore return value */ 401 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, 402 (tmp & P2F_USB_FM_VALID), 10, 200); 403 404 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); 405 406 /* disable frequency meter */ 407 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 408 tmp &= ~P2F_RG_FREQDET_EN; 409 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 410 411 /*disable free run clock */ 412 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 413 tmp &= ~P2F_RG_FRCK_EN; 414 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 415 416 if (fm_out) { 417 /* ( 1024 / FM_OUT ) x reference clock frequency x coef */ 418 tmp = tphy->src_ref_clk * tphy->src_coef; 419 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out; 420 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); 421 } else { 422 /* if FM detection fail, set default value */ 423 calibration_val = 4; 424 } 425 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", 426 instance->index, fm_out, calibration_val, 427 tphy->src_ref_clk, tphy->src_coef); 428 429 /* set HS slew rate */ 430 tmp = readl(com + U3P_USBPHYACR5); 431 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; 432 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); 433 writel(tmp, com + U3P_USBPHYACR5); 434 435 /* disable USB ring oscillator */ 436 tmp = readl(com + U3P_USBPHYACR5); 437 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; 438 writel(tmp, com + U3P_USBPHYACR5); 439 } 440 441 static void u3_phy_instance_init(struct mtk_tphy *tphy, 442 struct mtk_phy_instance *instance) 443 { 444 struct u3phy_banks *u3_banks = &instance->u3_banks; 445 u32 tmp; 446 447 /* gating PCIe Analog XTAL clock */ 448 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); 449 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; 450 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); 451 452 /* gating XSQ */ 453 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 454 tmp &= ~P3A_RG_XTAL_EXT_EN_U3; 455 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); 456 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 457 458 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); 459 tmp &= ~P3A_RG_RX_DAC_MUX; 460 tmp |= P3A_RG_RX_DAC_MUX_VAL(4); 461 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); 462 463 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); 464 tmp &= ~P3A_RG_TX_EIDLE_CM; 465 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); 466 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); 467 468 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); 469 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); 470 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); 471 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); 472 473 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); 474 tmp &= ~P3D_RG_FWAKE_TH; 475 tmp |= P3D_RG_FWAKE_TH_VAL(0x34); 476 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); 477 478 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 479 tmp &= ~P3D_RG_RXDET_STB2_SET; 480 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 481 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 482 483 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 484 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 485 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 486 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 487 488 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 489 } 490 491 static void u2_phy_pll_26m_set(struct mtk_tphy *tphy, 492 struct mtk_phy_instance *instance) 493 { 494 struct u2phy_banks *u2_banks = &instance->u2_banks; 495 void __iomem *com = u2_banks->com; 496 u32 tmp; 497 498 if (!tphy->pdata->sw_pll_48m_to_26m) 499 return; 500 501 tmp = readl(com + U3P_USBPHYACR0); 502 tmp &= ~PA0_USB20_PLL_PREDIV; 503 tmp |= PA0_USB20_PLL_PREDIV_VAL(0); 504 writel(tmp, com + U3P_USBPHYACR0); 505 506 tmp = readl(com + U3P_USBPHYACR2); 507 tmp &= ~PA2_RG_U2PLL_BW; 508 tmp |= PA2_RG_U2PLL_BW_VAL(3); 509 writel(tmp, com + U3P_USBPHYACR2); 510 511 writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV); 512 513 tmp = readl(com + U3P_U2PHYA_RESV1); 514 tmp |= P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL; 515 writel(tmp, com + U3P_U2PHYA_RESV1); 516 } 517 518 static void u2_phy_instance_init(struct mtk_tphy *tphy, 519 struct mtk_phy_instance *instance) 520 { 521 struct u2phy_banks *u2_banks = &instance->u2_banks; 522 void __iomem *com = u2_banks->com; 523 u32 index = instance->index; 524 u32 tmp; 525 526 /* switch to USB function, and enable usb pll */ 527 tmp = readl(com + U3P_U2PHYDTM0); 528 tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); 529 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); 530 writel(tmp, com + U3P_U2PHYDTM0); 531 532 tmp = readl(com + U3P_U2PHYDTM1); 533 tmp &= ~P2C_RG_UART_EN; 534 writel(tmp, com + U3P_U2PHYDTM1); 535 536 tmp = readl(com + U3P_USBPHYACR0); 537 tmp |= PA0_RG_USB20_INTR_EN; 538 writel(tmp, com + U3P_USBPHYACR0); 539 540 /* disable switch 100uA current to SSUSB */ 541 tmp = readl(com + U3P_USBPHYACR5); 542 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; 543 writel(tmp, com + U3P_USBPHYACR5); 544 545 if (!index) { 546 tmp = readl(com + U3P_U2PHYACR4); 547 tmp &= ~P2C_U2_GPIO_CTR_MSK; 548 writel(tmp, com + U3P_U2PHYACR4); 549 } 550 551 if (tphy->pdata->avoid_rx_sen_degradation) { 552 if (!index) { 553 tmp = readl(com + U3P_USBPHYACR2); 554 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; 555 writel(tmp, com + U3P_USBPHYACR2); 556 557 tmp = readl(com + U3D_U2PHYDCR0); 558 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 559 writel(tmp, com + U3D_U2PHYDCR0); 560 } else { 561 tmp = readl(com + U3D_U2PHYDCR0); 562 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 563 writel(tmp, com + U3D_U2PHYDCR0); 564 565 tmp = readl(com + U3P_U2PHYDTM0); 566 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 567 writel(tmp, com + U3P_U2PHYDTM0); 568 } 569 } 570 571 tmp = readl(com + U3P_USBPHYACR6); 572 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ 573 tmp &= ~PA6_RG_U2_SQTH; 574 tmp |= PA6_RG_U2_SQTH_VAL(2); 575 writel(tmp, com + U3P_USBPHYACR6); 576 577 /* Workaround only for mt8195, HW fix it for others (V3) */ 578 u2_phy_pll_26m_set(tphy, instance); 579 580 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 581 } 582 583 static void u2_phy_instance_power_on(struct mtk_tphy *tphy, 584 struct mtk_phy_instance *instance) 585 { 586 struct u2phy_banks *u2_banks = &instance->u2_banks; 587 void __iomem *com = u2_banks->com; 588 u32 index = instance->index; 589 u32 tmp; 590 591 tmp = readl(com + U3P_U2PHYDTM0); 592 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); 593 writel(tmp, com + U3P_U2PHYDTM0); 594 595 /* OTG Enable */ 596 tmp = readl(com + U3P_USBPHYACR6); 597 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; 598 writel(tmp, com + U3P_USBPHYACR6); 599 600 tmp = readl(com + U3P_U2PHYDTM1); 601 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; 602 tmp &= ~P2C_RG_SESSEND; 603 writel(tmp, com + U3P_U2PHYDTM1); 604 605 if (tphy->pdata->avoid_rx_sen_degradation && index) { 606 tmp = readl(com + U3D_U2PHYDCR0); 607 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 608 writel(tmp, com + U3D_U2PHYDCR0); 609 610 tmp = readl(com + U3P_U2PHYDTM0); 611 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 612 writel(tmp, com + U3P_U2PHYDTM0); 613 } 614 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 615 } 616 617 static void u2_phy_instance_power_off(struct mtk_tphy *tphy, 618 struct mtk_phy_instance *instance) 619 { 620 struct u2phy_banks *u2_banks = &instance->u2_banks; 621 void __iomem *com = u2_banks->com; 622 u32 index = instance->index; 623 u32 tmp; 624 625 tmp = readl(com + U3P_U2PHYDTM0); 626 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); 627 writel(tmp, com + U3P_U2PHYDTM0); 628 629 /* OTG Disable */ 630 tmp = readl(com + U3P_USBPHYACR6); 631 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; 632 writel(tmp, com + U3P_USBPHYACR6); 633 634 tmp = readl(com + U3P_U2PHYDTM1); 635 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); 636 tmp |= P2C_RG_SESSEND; 637 writel(tmp, com + U3P_U2PHYDTM1); 638 639 if (tphy->pdata->avoid_rx_sen_degradation && index) { 640 tmp = readl(com + U3P_U2PHYDTM0); 641 tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 642 writel(tmp, com + U3P_U2PHYDTM0); 643 644 tmp = readl(com + U3D_U2PHYDCR0); 645 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 646 writel(tmp, com + U3D_U2PHYDCR0); 647 } 648 649 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 650 } 651 652 static void u2_phy_instance_exit(struct mtk_tphy *tphy, 653 struct mtk_phy_instance *instance) 654 { 655 struct u2phy_banks *u2_banks = &instance->u2_banks; 656 void __iomem *com = u2_banks->com; 657 u32 index = instance->index; 658 u32 tmp; 659 660 if (tphy->pdata->avoid_rx_sen_degradation && index) { 661 tmp = readl(com + U3D_U2PHYDCR0); 662 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 663 writel(tmp, com + U3D_U2PHYDCR0); 664 665 tmp = readl(com + U3P_U2PHYDTM0); 666 tmp &= ~P2C_FORCE_SUSPENDM; 667 writel(tmp, com + U3P_U2PHYDTM0); 668 } 669 } 670 671 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, 672 struct mtk_phy_instance *instance, 673 enum phy_mode mode) 674 { 675 struct u2phy_banks *u2_banks = &instance->u2_banks; 676 u32 tmp; 677 678 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); 679 switch (mode) { 680 case PHY_MODE_USB_DEVICE: 681 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; 682 break; 683 case PHY_MODE_USB_HOST: 684 tmp |= P2C_FORCE_IDDIG; 685 tmp &= ~P2C_RG_IDDIG; 686 break; 687 case PHY_MODE_USB_OTG: 688 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); 689 break; 690 default: 691 return; 692 } 693 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); 694 } 695 696 static void pcie_phy_instance_init(struct mtk_tphy *tphy, 697 struct mtk_phy_instance *instance) 698 { 699 struct u3phy_banks *u3_banks = &instance->u3_banks; 700 u32 tmp; 701 702 if (tphy->pdata->version != MTK_PHY_V1) 703 return; 704 705 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 706 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); 707 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); 708 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 709 710 /* ref clk drive */ 711 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); 712 tmp &= ~P3A_RG_CLKDRV_AMP; 713 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); 714 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); 715 716 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); 717 tmp &= ~P3A_RG_CLKDRV_OFF; 718 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); 719 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); 720 721 /* SSC delta -5000ppm */ 722 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); 723 tmp &= ~P3A_RG_PLL_DELTA1_PE2H; 724 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); 725 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); 726 727 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); 728 tmp &= ~P3A_RG_PLL_DELTA_PE2H; 729 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); 730 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); 731 732 /* change pll BW 0.6M */ 733 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); 734 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); 735 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); 736 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); 737 738 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); 739 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); 740 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); 741 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); 742 743 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); 744 tmp &= ~P3A_RG_PLL_IR_PE2H; 745 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); 746 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); 747 748 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); 749 tmp &= ~P3A_RG_PLL_BP_PE2H; 750 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); 751 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); 752 753 /* Tx Detect Rx Timing: 10us -> 5us */ 754 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 755 tmp &= ~P3D_RG_RXDET_STB2_SET; 756 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 757 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 758 759 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 760 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 761 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 762 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 763 764 /* wait for PCIe subsys register to active */ 765 usleep_range(2500, 3000); 766 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 767 } 768 769 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, 770 struct mtk_phy_instance *instance) 771 { 772 struct u3phy_banks *bank = &instance->u3_banks; 773 u32 tmp; 774 775 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 776 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); 777 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 778 779 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 780 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 781 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 782 } 783 784 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, 785 struct mtk_phy_instance *instance) 786 787 { 788 struct u3phy_banks *bank = &instance->u3_banks; 789 u32 tmp; 790 791 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 792 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; 793 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 794 795 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 796 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; 797 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 798 } 799 800 static void sata_phy_instance_init(struct mtk_tphy *tphy, 801 struct mtk_phy_instance *instance) 802 { 803 struct u3phy_banks *u3_banks = &instance->u3_banks; 804 void __iomem *phyd = u3_banks->phyd; 805 u32 tmp; 806 807 /* charge current adjustment */ 808 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); 809 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); 810 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); 811 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); 812 813 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 814 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; 815 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); 816 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 817 818 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 819 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; 820 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); 821 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 822 823 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); 824 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); 825 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); 826 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); 827 828 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); 829 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); 830 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); 831 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); 832 833 tmp = readl(phyd + PHYD_DESIGN_OPTION2); 834 tmp &= ~RG_LOCK_CNT_SEL_MSK; 835 tmp |= RG_LOCK_CNT_SEL_VAL(0x02); 836 writel(tmp, phyd + PHYD_DESIGN_OPTION2); 837 838 tmp = readl(phyd + PHYD_DESIGN_OPTION9); 839 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | 840 RG_T2_MAX_MSK | RG_TG_MAX_MSK); 841 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | 842 RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e); 843 writel(tmp, phyd + PHYD_DESIGN_OPTION9); 844 845 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); 846 tmp &= ~RG_IDRV_0DB_GEN1_MSK; 847 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); 848 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); 849 850 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 851 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; 852 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); 853 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 854 855 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 856 } 857 858 static void phy_v1_banks_init(struct mtk_tphy *tphy, 859 struct mtk_phy_instance *instance) 860 { 861 struct u2phy_banks *u2_banks = &instance->u2_banks; 862 struct u3phy_banks *u3_banks = &instance->u3_banks; 863 864 switch (instance->type) { 865 case PHY_TYPE_USB2: 866 u2_banks->misc = NULL; 867 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; 868 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; 869 break; 870 case PHY_TYPE_USB3: 871 case PHY_TYPE_PCIE: 872 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; 873 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; 874 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 875 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; 876 break; 877 case PHY_TYPE_SATA: 878 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 879 break; 880 default: 881 dev_err(tphy->dev, "incompatible PHY type\n"); 882 return; 883 } 884 } 885 886 static void phy_v2_banks_init(struct mtk_tphy *tphy, 887 struct mtk_phy_instance *instance) 888 { 889 struct u2phy_banks *u2_banks = &instance->u2_banks; 890 struct u3phy_banks *u3_banks = &instance->u3_banks; 891 892 switch (instance->type) { 893 case PHY_TYPE_USB2: 894 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; 895 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; 896 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; 897 break; 898 case PHY_TYPE_USB3: 899 case PHY_TYPE_PCIE: 900 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; 901 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; 902 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; 903 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; 904 break; 905 default: 906 dev_err(tphy->dev, "incompatible PHY type\n"); 907 return; 908 } 909 } 910 911 static void phy_parse_property(struct mtk_tphy *tphy, 912 struct mtk_phy_instance *instance) 913 { 914 struct device *dev = &instance->phy->dev; 915 916 if (instance->type != PHY_TYPE_USB2) 917 return; 918 919 instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12"); 920 device_property_read_u32(dev, "mediatek,eye-src", 921 &instance->eye_src); 922 device_property_read_u32(dev, "mediatek,eye-vrt", 923 &instance->eye_vrt); 924 device_property_read_u32(dev, "mediatek,eye-term", 925 &instance->eye_term); 926 device_property_read_u32(dev, "mediatek,intr", 927 &instance->intr); 928 device_property_read_u32(dev, "mediatek,discth", 929 &instance->discth); 930 dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n", 931 instance->bc12_en, instance->eye_src, 932 instance->eye_vrt, instance->eye_term, 933 instance->intr, instance->discth); 934 } 935 936 static void u2_phy_props_set(struct mtk_tphy *tphy, 937 struct mtk_phy_instance *instance) 938 { 939 struct u2phy_banks *u2_banks = &instance->u2_banks; 940 void __iomem *com = u2_banks->com; 941 u32 tmp; 942 943 if (instance->bc12_en) { 944 tmp = readl(com + U3P_U2PHYBC12C); 945 tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */ 946 writel(tmp, com + U3P_U2PHYBC12C); 947 } 948 949 if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) { 950 tmp = readl(com + U3P_USBPHYACR5); 951 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; 952 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src); 953 writel(tmp, com + U3P_USBPHYACR5); 954 } 955 956 if (instance->eye_vrt) { 957 tmp = readl(com + U3P_USBPHYACR1); 958 tmp &= ~PA1_RG_VRT_SEL; 959 tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt); 960 writel(tmp, com + U3P_USBPHYACR1); 961 } 962 963 if (instance->eye_term) { 964 tmp = readl(com + U3P_USBPHYACR1); 965 tmp &= ~PA1_RG_TERM_SEL; 966 tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term); 967 writel(tmp, com + U3P_USBPHYACR1); 968 } 969 970 if (instance->intr) { 971 tmp = readl(com + U3P_USBPHYACR1); 972 tmp &= ~PA1_RG_INTR_CAL; 973 tmp |= PA1_RG_INTR_CAL_VAL(instance->intr); 974 writel(tmp, com + U3P_USBPHYACR1); 975 } 976 977 if (instance->discth) { 978 tmp = readl(com + U3P_USBPHYACR6); 979 tmp &= ~PA6_RG_U2_DISCTH; 980 tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth); 981 writel(tmp, com + U3P_USBPHYACR6); 982 } 983 } 984 985 /* type switch for usb3/pcie/sgmii/sata */ 986 static int phy_type_syscon_get(struct mtk_phy_instance *instance, 987 struct device_node *dn) 988 { 989 struct of_phandle_args args; 990 int ret; 991 992 /* type switch function is optional */ 993 if (!of_property_read_bool(dn, "mediatek,syscon-type")) 994 return 0; 995 996 ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", 997 2, 0, &args); 998 if (ret) 999 return ret; 1000 1001 instance->type_sw_reg = args.args[0]; 1002 instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ 1003 instance->type_sw = syscon_node_to_regmap(args.np); 1004 of_node_put(args.np); 1005 dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", 1006 instance->type_sw_reg, instance->type_sw_index); 1007 1008 return PTR_ERR_OR_ZERO(instance->type_sw); 1009 } 1010 1011 static int phy_type_set(struct mtk_phy_instance *instance) 1012 { 1013 int type; 1014 u32 mask; 1015 1016 if (!instance->type_sw) 1017 return 0; 1018 1019 switch (instance->type) { 1020 case PHY_TYPE_USB3: 1021 type = RG_PHY_SW_USB3; 1022 break; 1023 case PHY_TYPE_PCIE: 1024 type = RG_PHY_SW_PCIE; 1025 break; 1026 case PHY_TYPE_SGMII: 1027 type = RG_PHY_SW_SGMII; 1028 break; 1029 case PHY_TYPE_SATA: 1030 type = RG_PHY_SW_SATA; 1031 break; 1032 case PHY_TYPE_USB2: 1033 default: 1034 return 0; 1035 } 1036 1037 mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE); 1038 regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type); 1039 1040 return 0; 1041 } 1042 1043 static int mtk_phy_init(struct phy *phy) 1044 { 1045 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1046 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1047 int ret; 1048 1049 ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks); 1050 if (ret) 1051 return ret; 1052 1053 switch (instance->type) { 1054 case PHY_TYPE_USB2: 1055 u2_phy_instance_init(tphy, instance); 1056 u2_phy_props_set(tphy, instance); 1057 break; 1058 case PHY_TYPE_USB3: 1059 u3_phy_instance_init(tphy, instance); 1060 break; 1061 case PHY_TYPE_PCIE: 1062 pcie_phy_instance_init(tphy, instance); 1063 break; 1064 case PHY_TYPE_SATA: 1065 sata_phy_instance_init(tphy, instance); 1066 break; 1067 case PHY_TYPE_SGMII: 1068 /* nothing to do, only used to set type */ 1069 break; 1070 default: 1071 dev_err(tphy->dev, "incompatible PHY type\n"); 1072 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); 1073 return -EINVAL; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static int mtk_phy_power_on(struct phy *phy) 1080 { 1081 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1082 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1083 1084 if (instance->type == PHY_TYPE_USB2) { 1085 u2_phy_instance_power_on(tphy, instance); 1086 hs_slew_rate_calibrate(tphy, instance); 1087 } else if (instance->type == PHY_TYPE_PCIE) { 1088 pcie_phy_instance_power_on(tphy, instance); 1089 } 1090 1091 return 0; 1092 } 1093 1094 static int mtk_phy_power_off(struct phy *phy) 1095 { 1096 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1097 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1098 1099 if (instance->type == PHY_TYPE_USB2) 1100 u2_phy_instance_power_off(tphy, instance); 1101 else if (instance->type == PHY_TYPE_PCIE) 1102 pcie_phy_instance_power_off(tphy, instance); 1103 1104 return 0; 1105 } 1106 1107 static int mtk_phy_exit(struct phy *phy) 1108 { 1109 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1110 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1111 1112 if (instance->type == PHY_TYPE_USB2) 1113 u2_phy_instance_exit(tphy, instance); 1114 1115 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); 1116 return 0; 1117 } 1118 1119 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1120 { 1121 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1122 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1123 1124 if (instance->type == PHY_TYPE_USB2) 1125 u2_phy_instance_set_mode(tphy, instance, mode); 1126 1127 return 0; 1128 } 1129 1130 static struct phy *mtk_phy_xlate(struct device *dev, 1131 struct of_phandle_args *args) 1132 { 1133 struct mtk_tphy *tphy = dev_get_drvdata(dev); 1134 struct mtk_phy_instance *instance = NULL; 1135 struct device_node *phy_np = args->np; 1136 int index; 1137 1138 if (args->args_count != 1) { 1139 dev_err(dev, "invalid number of cells in 'phy' property\n"); 1140 return ERR_PTR(-EINVAL); 1141 } 1142 1143 for (index = 0; index < tphy->nphys; index++) 1144 if (phy_np == tphy->phys[index]->phy->dev.of_node) { 1145 instance = tphy->phys[index]; 1146 break; 1147 } 1148 1149 if (!instance) { 1150 dev_err(dev, "failed to find appropriate phy\n"); 1151 return ERR_PTR(-EINVAL); 1152 } 1153 1154 instance->type = args->args[0]; 1155 if (!(instance->type == PHY_TYPE_USB2 || 1156 instance->type == PHY_TYPE_USB3 || 1157 instance->type == PHY_TYPE_PCIE || 1158 instance->type == PHY_TYPE_SATA || 1159 instance->type == PHY_TYPE_SGMII)) { 1160 dev_err(dev, "unsupported device type: %d\n", instance->type); 1161 return ERR_PTR(-EINVAL); 1162 } 1163 1164 switch (tphy->pdata->version) { 1165 case MTK_PHY_V1: 1166 phy_v1_banks_init(tphy, instance); 1167 break; 1168 case MTK_PHY_V2: 1169 case MTK_PHY_V3: 1170 phy_v2_banks_init(tphy, instance); 1171 break; 1172 default: 1173 dev_err(dev, "phy version is not supported\n"); 1174 return ERR_PTR(-EINVAL); 1175 } 1176 1177 phy_parse_property(tphy, instance); 1178 phy_type_set(instance); 1179 1180 return instance->phy; 1181 } 1182 1183 static const struct phy_ops mtk_tphy_ops = { 1184 .init = mtk_phy_init, 1185 .exit = mtk_phy_exit, 1186 .power_on = mtk_phy_power_on, 1187 .power_off = mtk_phy_power_off, 1188 .set_mode = mtk_phy_set_mode, 1189 .owner = THIS_MODULE, 1190 }; 1191 1192 static const struct mtk_phy_pdata tphy_v1_pdata = { 1193 .avoid_rx_sen_degradation = false, 1194 .version = MTK_PHY_V1, 1195 }; 1196 1197 static const struct mtk_phy_pdata tphy_v2_pdata = { 1198 .avoid_rx_sen_degradation = false, 1199 .version = MTK_PHY_V2, 1200 }; 1201 1202 static const struct mtk_phy_pdata tphy_v3_pdata = { 1203 .version = MTK_PHY_V3, 1204 }; 1205 1206 static const struct mtk_phy_pdata mt8173_pdata = { 1207 .avoid_rx_sen_degradation = true, 1208 .version = MTK_PHY_V1, 1209 }; 1210 1211 static const struct mtk_phy_pdata mt8195_pdata = { 1212 .sw_pll_48m_to_26m = true, 1213 .version = MTK_PHY_V3, 1214 }; 1215 1216 static const struct of_device_id mtk_tphy_id_table[] = { 1217 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, 1218 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, 1219 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, 1220 { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata }, 1221 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, 1222 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, 1223 { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, 1224 { }, 1225 }; 1226 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); 1227 1228 static int mtk_tphy_probe(struct platform_device *pdev) 1229 { 1230 struct device *dev = &pdev->dev; 1231 struct device_node *np = dev->of_node; 1232 struct device_node *child_np; 1233 struct phy_provider *provider; 1234 struct resource *sif_res; 1235 struct mtk_tphy *tphy; 1236 struct resource res; 1237 int port, retval; 1238 1239 tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); 1240 if (!tphy) 1241 return -ENOMEM; 1242 1243 tphy->pdata = of_device_get_match_data(dev); 1244 if (!tphy->pdata) 1245 return -EINVAL; 1246 1247 tphy->nphys = of_get_child_count(np); 1248 tphy->phys = devm_kcalloc(dev, tphy->nphys, 1249 sizeof(*tphy->phys), GFP_KERNEL); 1250 if (!tphy->phys) 1251 return -ENOMEM; 1252 1253 tphy->dev = dev; 1254 platform_set_drvdata(pdev, tphy); 1255 1256 sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1257 /* SATA phy of V1 needn't it if not shared with PCIe or USB */ 1258 if (sif_res && tphy->pdata->version == MTK_PHY_V1) { 1259 /* get banks shared by multiple phys */ 1260 tphy->sif_base = devm_ioremap_resource(dev, sif_res); 1261 if (IS_ERR(tphy->sif_base)) { 1262 dev_err(dev, "failed to remap sif regs\n"); 1263 return PTR_ERR(tphy->sif_base); 1264 } 1265 } 1266 1267 if (tphy->pdata->version < MTK_PHY_V3) { 1268 tphy->src_ref_clk = U3P_REF_CLK; 1269 tphy->src_coef = U3P_SLEW_RATE_COEF; 1270 /* update parameters of slew rate calibrate if exist */ 1271 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", 1272 &tphy->src_ref_clk); 1273 device_property_read_u32(dev, "mediatek,src-coef", 1274 &tphy->src_coef); 1275 } 1276 1277 port = 0; 1278 for_each_child_of_node(np, child_np) { 1279 struct mtk_phy_instance *instance; 1280 struct clk_bulk_data *clks; 1281 struct device *subdev; 1282 struct phy *phy; 1283 1284 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); 1285 if (!instance) { 1286 retval = -ENOMEM; 1287 goto put_child; 1288 } 1289 1290 tphy->phys[port] = instance; 1291 1292 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops); 1293 if (IS_ERR(phy)) { 1294 dev_err(dev, "failed to create phy\n"); 1295 retval = PTR_ERR(phy); 1296 goto put_child; 1297 } 1298 1299 subdev = &phy->dev; 1300 retval = of_address_to_resource(child_np, 0, &res); 1301 if (retval) { 1302 dev_err(subdev, "failed to get address resource(id-%d)\n", 1303 port); 1304 goto put_child; 1305 } 1306 1307 instance->port_base = devm_ioremap_resource(subdev, &res); 1308 if (IS_ERR(instance->port_base)) { 1309 retval = PTR_ERR(instance->port_base); 1310 goto put_child; 1311 } 1312 1313 instance->phy = phy; 1314 instance->index = port; 1315 phy_set_drvdata(phy, instance); 1316 port++; 1317 1318 clks = instance->clks; 1319 clks[0].id = "ref"; /* digital (& analog) clock */ 1320 clks[1].id = "da_ref"; /* analog clock */ 1321 retval = devm_clk_bulk_get_optional(subdev, TPHY_CLKS_CNT, clks); 1322 if (retval) 1323 goto put_child; 1324 1325 retval = phy_type_syscon_get(instance, child_np); 1326 if (retval) 1327 goto put_child; 1328 } 1329 1330 provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); 1331 1332 return PTR_ERR_OR_ZERO(provider); 1333 put_child: 1334 of_node_put(child_np); 1335 return retval; 1336 } 1337 1338 static struct platform_driver mtk_tphy_driver = { 1339 .probe = mtk_tphy_probe, 1340 .driver = { 1341 .name = "mtk-tphy", 1342 .of_match_table = mtk_tphy_id_table, 1343 }, 1344 }; 1345 1346 module_platform_driver(mtk_tphy_driver); 1347 1348 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 1349 MODULE_DESCRIPTION("MediaTek T-PHY driver"); 1350 MODULE_LICENSE("GPL v2"); 1351