1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #include <dt-bindings/phy/phy.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 26 /* version V1 sub-banks offset base address */ 27 /* banks shared by multiple phys */ 28 #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ 29 #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ 30 #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ 31 /* u2 phy bank */ 32 #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 33 /* u3/pcie/sata phy banks */ 34 #define SSUSB_SIFSLV_V1_U3PHYD 0x000 35 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 36 37 /* version V2 sub-banks offset base address */ 38 /* u2 phy banks */ 39 #define SSUSB_SIFSLV_V2_MISC 0x000 40 #define SSUSB_SIFSLV_V2_U2FREQ 0x100 41 #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 42 /* u3/pcie/sata phy banks */ 43 #define SSUSB_SIFSLV_V2_SPLLC 0x000 44 #define SSUSB_SIFSLV_V2_CHIP 0x100 45 #define SSUSB_SIFSLV_V2_U3PHYD 0x200 46 #define SSUSB_SIFSLV_V2_U3PHYA 0x400 47 48 #define U3P_USBPHYACR0 0x000 49 #define PA0_RG_U2PLL_FORCE_ON BIT(15) 50 #define PA0_RG_USB20_INTR_EN BIT(5) 51 52 #define U3P_USBPHYACR2 0x008 53 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) 54 55 #define U3P_USBPHYACR5 0x014 56 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) 57 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) 58 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) 59 #define PA5_RG_U2_HS_100U_U3_EN BIT(11) 60 61 #define U3P_USBPHYACR6 0x018 62 #define PA6_RG_U2_BC11_SW_EN BIT(23) 63 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) 64 #define PA6_RG_U2_SQTH GENMASK(3, 0) 65 #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) 66 67 #define U3P_U2PHYACR4 0x020 68 #define P2C_RG_USB20_GPIO_CTL BIT(9) 69 #define P2C_USB20_GPIO_MODE BIT(8) 70 #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) 71 72 #define U3D_U2PHYDCR0 0x060 73 #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) 74 75 #define U3P_U2PHYDTM0 0x068 76 #define P2C_FORCE_UART_EN BIT(26) 77 #define P2C_FORCE_DATAIN BIT(23) 78 #define P2C_FORCE_DM_PULLDOWN BIT(21) 79 #define P2C_FORCE_DP_PULLDOWN BIT(20) 80 #define P2C_FORCE_XCVRSEL BIT(19) 81 #define P2C_FORCE_SUSPENDM BIT(18) 82 #define P2C_FORCE_TERMSEL BIT(17) 83 #define P2C_RG_DATAIN GENMASK(13, 10) 84 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) 85 #define P2C_RG_DMPULLDOWN BIT(7) 86 #define P2C_RG_DPPULLDOWN BIT(6) 87 #define P2C_RG_XCVRSEL GENMASK(5, 4) 88 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) 89 #define P2C_RG_SUSPENDM BIT(3) 90 #define P2C_RG_TERMSEL BIT(2) 91 #define P2C_DTM0_PART_MASK \ 92 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ 93 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ 94 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ 95 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) 96 97 #define U3P_U2PHYDTM1 0x06C 98 #define P2C_RG_UART_EN BIT(16) 99 #define P2C_RG_VBUSVALID BIT(5) 100 #define P2C_RG_SESSEND BIT(4) 101 #define P2C_RG_AVALID BIT(2) 102 103 #define U3P_U3_CHIP_GPIO_CTLD 0x0c 104 #define P3C_REG_IP_SW_RST BIT(31) 105 #define P3C_MCU_BUS_CK_GATE_EN BIT(30) 106 #define P3C_FORCE_IP_SW_RST BIT(29) 107 108 #define U3P_U3_CHIP_GPIO_CTLE 0x10 109 #define P3C_RG_SWRST_U3_PHYD BIT(25) 110 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) 111 112 #define U3P_U3_PHYA_REG0 0x000 113 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) 114 #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) 115 116 #define U3P_U3_PHYA_REG1 0x004 117 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) 118 #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) 119 120 #define U3P_U3_PHYA_REG6 0x018 121 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) 122 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) 123 124 #define U3P_U3_PHYA_REG9 0x024 125 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) 126 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) 127 128 #define U3P_U3_PHYA_DA_REG0 0x100 129 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) 130 #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) 131 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) 132 #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) 133 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) 134 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) 135 136 #define U3P_U3_PHYA_DA_REG4 0x108 137 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) 138 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) 139 #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) 140 141 #define U3P_U3_PHYA_DA_REG5 0x10c 142 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) 143 #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) 144 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) 145 #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) 146 147 #define U3P_U3_PHYA_DA_REG6 0x110 148 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) 149 #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) 150 151 #define U3P_U3_PHYA_DA_REG7 0x114 152 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) 153 #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) 154 155 #define U3P_U3_PHYA_DA_REG20 0x13c 156 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) 157 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) 158 159 #define U3P_U3_PHYA_DA_REG25 0x148 160 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) 161 #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) 162 163 #define U3P_U3_PHYD_LFPS1 0x00c 164 #define P3D_RG_FWAKE_TH GENMASK(21, 16) 165 #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) 166 167 #define U3P_U3_PHYD_CDR1 0x05c 168 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 169 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) 170 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 171 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) 172 173 #define U3P_U3_PHYD_RXDET1 0x128 174 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 175 #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) 176 177 #define U3P_U3_PHYD_RXDET2 0x12c 178 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) 179 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) 180 181 #define U3P_SPLLC_XTALCTL3 0x018 182 #define XC3_RG_U3_XTAL_RX_PWD BIT(9) 183 #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) 184 185 #define U3P_U2FREQ_FMCR0 0x00 186 #define P2F_RG_MONCLK_SEL GENMASK(27, 26) 187 #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) 188 #define P2F_RG_FREQDET_EN BIT(24) 189 #define P2F_RG_CYCLECNT GENMASK(23, 0) 190 #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) 191 192 #define U3P_U2FREQ_VALUE 0x0c 193 194 #define U3P_U2FREQ_FMMONR1 0x10 195 #define P2F_USB_FM_VALID BIT(0) 196 #define P2F_RG_FRCK_EN BIT(8) 197 198 #define U3P_REF_CLK 26 /* MHZ */ 199 #define U3P_SLEW_RATE_COEF 28 200 #define U3P_SR_COEF_DIVISOR 1000 201 #define U3P_FM_DET_CYCLE_CNT 1024 202 203 /* SATA register setting */ 204 #define PHYD_CTRL_SIGNAL_MODE4 0x1c 205 /* CDR Charge Pump P-path current adjustment */ 206 #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) 207 #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) 208 #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) 209 #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) 210 211 #define PHYD_DESIGN_OPTION2 0x24 212 /* Symbol lock count selection */ 213 #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) 214 #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) 215 216 #define PHYD_DESIGN_OPTION9 0x40 217 /* COMWAK GAP width window */ 218 #define RG_TG_MAX_MSK GENMASK(20, 16) 219 #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) 220 /* COMINIT GAP width window */ 221 #define RG_T2_MAX_MSK GENMASK(13, 8) 222 #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) 223 /* COMWAK GAP width window */ 224 #define RG_TG_MIN_MSK GENMASK(7, 5) 225 #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) 226 /* COMINIT GAP width window */ 227 #define RG_T2_MIN_MSK GENMASK(4, 0) 228 #define RG_T2_MIN_VAL(x) (0x1f & (x)) 229 230 #define ANA_RG_CTRL_SIGNAL1 0x4c 231 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ 232 #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) 233 #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) 234 235 #define ANA_RG_CTRL_SIGNAL4 0x58 236 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) 237 #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) 238 /* Loop filter R1 resistance adjustment for Gen1 speed */ 239 #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) 240 #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) 241 242 #define ANA_RG_CTRL_SIGNAL6 0x60 243 /* I-path capacitance adjustment for Gen1 */ 244 #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) 245 #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) 246 #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) 247 #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) 248 249 #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c 250 /* RX Gen1 LEQ tuning step */ 251 #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) 252 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) 253 254 #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 255 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) 256 #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) 257 258 #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc 259 #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) 260 #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) 261 262 enum mtk_phy_version { 263 MTK_PHY_V1 = 1, 264 MTK_PHY_V2, 265 }; 266 267 struct mtk_phy_pdata { 268 /* avoid RX sensitivity level degradation only for mt8173 */ 269 bool avoid_rx_sen_degradation; 270 enum mtk_phy_version version; 271 }; 272 273 struct u2phy_banks { 274 void __iomem *misc; 275 void __iomem *fmreg; 276 void __iomem *com; 277 }; 278 279 struct u3phy_banks { 280 void __iomem *spllc; 281 void __iomem *chip; 282 void __iomem *phyd; /* include u3phyd_bank2 */ 283 void __iomem *phya; /* include u3phya_da */ 284 }; 285 286 struct mtk_phy_instance { 287 struct phy *phy; 288 void __iomem *port_base; 289 union { 290 struct u2phy_banks u2_banks; 291 struct u3phy_banks u3_banks; 292 }; 293 struct clk *ref_clk; /* reference clock of anolog phy */ 294 u32 index; 295 u8 type; 296 }; 297 298 struct mtk_tphy { 299 struct device *dev; 300 void __iomem *sif_base; /* only shared sif */ 301 /* deprecated, use @ref_clk instead in phy instance */ 302 struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ 303 const struct mtk_phy_pdata *pdata; 304 struct mtk_phy_instance **phys; 305 int nphys; 306 }; 307 308 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, 309 struct mtk_phy_instance *instance) 310 { 311 struct u2phy_banks *u2_banks = &instance->u2_banks; 312 void __iomem *fmreg = u2_banks->fmreg; 313 void __iomem *com = u2_banks->com; 314 int calibration_val; 315 int fm_out; 316 u32 tmp; 317 318 /* enable USB ring oscillator */ 319 tmp = readl(com + U3P_USBPHYACR5); 320 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; 321 writel(tmp, com + U3P_USBPHYACR5); 322 udelay(1); 323 324 /*enable free run clock */ 325 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 326 tmp |= P2F_RG_FRCK_EN; 327 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 328 329 /* set cycle count as 1024, and select u2 channel */ 330 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 331 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); 332 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); 333 if (tphy->pdata->version == MTK_PHY_V1) 334 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); 335 336 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 337 338 /* enable frequency meter */ 339 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 340 tmp |= P2F_RG_FREQDET_EN; 341 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 342 343 /* ignore return value */ 344 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, 345 (tmp & P2F_USB_FM_VALID), 10, 200); 346 347 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); 348 349 /* disable frequency meter */ 350 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 351 tmp &= ~P2F_RG_FREQDET_EN; 352 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 353 354 /*disable free run clock */ 355 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 356 tmp &= ~P2F_RG_FRCK_EN; 357 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 358 359 if (fm_out) { 360 /* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */ 361 tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF; 362 tmp /= fm_out; 363 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); 364 } else { 365 /* if FM detection fail, set default value */ 366 calibration_val = 4; 367 } 368 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n", 369 instance->index, fm_out, calibration_val); 370 371 /* set HS slew rate */ 372 tmp = readl(com + U3P_USBPHYACR5); 373 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; 374 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); 375 writel(tmp, com + U3P_USBPHYACR5); 376 377 /* disable USB ring oscillator */ 378 tmp = readl(com + U3P_USBPHYACR5); 379 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; 380 writel(tmp, com + U3P_USBPHYACR5); 381 } 382 383 static void u3_phy_instance_init(struct mtk_tphy *tphy, 384 struct mtk_phy_instance *instance) 385 { 386 struct u3phy_banks *u3_banks = &instance->u3_banks; 387 u32 tmp; 388 389 /* gating PCIe Analog XTAL clock */ 390 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); 391 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; 392 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); 393 394 /* gating XSQ */ 395 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 396 tmp &= ~P3A_RG_XTAL_EXT_EN_U3; 397 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); 398 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 399 400 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); 401 tmp &= ~P3A_RG_RX_DAC_MUX; 402 tmp |= P3A_RG_RX_DAC_MUX_VAL(4); 403 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); 404 405 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); 406 tmp &= ~P3A_RG_TX_EIDLE_CM; 407 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); 408 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); 409 410 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); 411 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); 412 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); 413 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); 414 415 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); 416 tmp &= ~P3D_RG_FWAKE_TH; 417 tmp |= P3D_RG_FWAKE_TH_VAL(0x34); 418 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); 419 420 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 421 tmp &= ~P3D_RG_RXDET_STB2_SET; 422 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 423 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 424 425 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 426 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 427 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 428 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 429 430 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 431 } 432 433 static void u2_phy_instance_init(struct mtk_tphy *tphy, 434 struct mtk_phy_instance *instance) 435 { 436 struct u2phy_banks *u2_banks = &instance->u2_banks; 437 void __iomem *com = u2_banks->com; 438 u32 index = instance->index; 439 u32 tmp; 440 441 /* switch to USB function. (system register, force ip into usb mode) */ 442 tmp = readl(com + U3P_U2PHYDTM0); 443 tmp &= ~P2C_FORCE_UART_EN; 444 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); 445 writel(tmp, com + U3P_U2PHYDTM0); 446 447 tmp = readl(com + U3P_U2PHYDTM1); 448 tmp &= ~P2C_RG_UART_EN; 449 writel(tmp, com + U3P_U2PHYDTM1); 450 451 tmp = readl(com + U3P_USBPHYACR0); 452 tmp |= PA0_RG_USB20_INTR_EN; 453 writel(tmp, com + U3P_USBPHYACR0); 454 455 /* disable switch 100uA current to SSUSB */ 456 tmp = readl(com + U3P_USBPHYACR5); 457 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; 458 writel(tmp, com + U3P_USBPHYACR5); 459 460 if (!index) { 461 tmp = readl(com + U3P_U2PHYACR4); 462 tmp &= ~P2C_U2_GPIO_CTR_MSK; 463 writel(tmp, com + U3P_U2PHYACR4); 464 } 465 466 if (tphy->pdata->avoid_rx_sen_degradation) { 467 if (!index) { 468 tmp = readl(com + U3P_USBPHYACR2); 469 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; 470 writel(tmp, com + U3P_USBPHYACR2); 471 472 tmp = readl(com + U3D_U2PHYDCR0); 473 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 474 writel(tmp, com + U3D_U2PHYDCR0); 475 } else { 476 tmp = readl(com + U3D_U2PHYDCR0); 477 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 478 writel(tmp, com + U3D_U2PHYDCR0); 479 480 tmp = readl(com + U3P_U2PHYDTM0); 481 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 482 writel(tmp, com + U3P_U2PHYDTM0); 483 } 484 } 485 486 tmp = readl(com + U3P_USBPHYACR6); 487 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ 488 tmp &= ~PA6_RG_U2_SQTH; 489 tmp |= PA6_RG_U2_SQTH_VAL(2); 490 writel(tmp, com + U3P_USBPHYACR6); 491 492 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 493 } 494 495 static void u2_phy_instance_power_on(struct mtk_tphy *tphy, 496 struct mtk_phy_instance *instance) 497 { 498 struct u2phy_banks *u2_banks = &instance->u2_banks; 499 void __iomem *com = u2_banks->com; 500 u32 index = instance->index; 501 u32 tmp; 502 503 /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ 504 tmp = readl(com + U3P_U2PHYDTM0); 505 tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL); 506 tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK); 507 writel(tmp, com + U3P_U2PHYDTM0); 508 509 /* OTG Enable */ 510 tmp = readl(com + U3P_USBPHYACR6); 511 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; 512 writel(tmp, com + U3P_USBPHYACR6); 513 514 tmp = readl(com + U3P_U2PHYDTM1); 515 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; 516 tmp &= ~P2C_RG_SESSEND; 517 writel(tmp, com + U3P_U2PHYDTM1); 518 519 if (tphy->pdata->avoid_rx_sen_degradation && index) { 520 tmp = readl(com + U3D_U2PHYDCR0); 521 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 522 writel(tmp, com + U3D_U2PHYDCR0); 523 524 tmp = readl(com + U3P_U2PHYDTM0); 525 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 526 writel(tmp, com + U3P_U2PHYDTM0); 527 } 528 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 529 } 530 531 static void u2_phy_instance_power_off(struct mtk_tphy *tphy, 532 struct mtk_phy_instance *instance) 533 { 534 struct u2phy_banks *u2_banks = &instance->u2_banks; 535 void __iomem *com = u2_banks->com; 536 u32 index = instance->index; 537 u32 tmp; 538 539 tmp = readl(com + U3P_U2PHYDTM0); 540 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); 541 tmp |= P2C_FORCE_SUSPENDM; 542 writel(tmp, com + U3P_U2PHYDTM0); 543 544 /* OTG Disable */ 545 tmp = readl(com + U3P_USBPHYACR6); 546 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; 547 writel(tmp, com + U3P_USBPHYACR6); 548 549 /* let suspendm=0, set utmi into analog power down */ 550 tmp = readl(com + U3P_U2PHYDTM0); 551 tmp &= ~P2C_RG_SUSPENDM; 552 writel(tmp, com + U3P_U2PHYDTM0); 553 udelay(1); 554 555 tmp = readl(com + U3P_U2PHYDTM1); 556 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); 557 tmp |= P2C_RG_SESSEND; 558 writel(tmp, com + U3P_U2PHYDTM1); 559 560 if (tphy->pdata->avoid_rx_sen_degradation && index) { 561 tmp = readl(com + U3D_U2PHYDCR0); 562 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 563 writel(tmp, com + U3D_U2PHYDCR0); 564 } 565 566 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 567 } 568 569 static void u2_phy_instance_exit(struct mtk_tphy *tphy, 570 struct mtk_phy_instance *instance) 571 { 572 struct u2phy_banks *u2_banks = &instance->u2_banks; 573 void __iomem *com = u2_banks->com; 574 u32 index = instance->index; 575 u32 tmp; 576 577 if (tphy->pdata->avoid_rx_sen_degradation && index) { 578 tmp = readl(com + U3D_U2PHYDCR0); 579 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 580 writel(tmp, com + U3D_U2PHYDCR0); 581 582 tmp = readl(com + U3P_U2PHYDTM0); 583 tmp &= ~P2C_FORCE_SUSPENDM; 584 writel(tmp, com + U3P_U2PHYDTM0); 585 } 586 } 587 588 static void pcie_phy_instance_init(struct mtk_tphy *tphy, 589 struct mtk_phy_instance *instance) 590 { 591 struct u3phy_banks *u3_banks = &instance->u3_banks; 592 u32 tmp; 593 594 if (tphy->pdata->version != MTK_PHY_V1) 595 return; 596 597 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 598 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); 599 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); 600 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 601 602 /* ref clk drive */ 603 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); 604 tmp &= ~P3A_RG_CLKDRV_AMP; 605 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); 606 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); 607 608 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); 609 tmp &= ~P3A_RG_CLKDRV_OFF; 610 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); 611 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); 612 613 /* SSC delta -5000ppm */ 614 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); 615 tmp &= ~P3A_RG_PLL_DELTA1_PE2H; 616 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); 617 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); 618 619 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); 620 tmp &= ~P3A_RG_PLL_DELTA_PE2H; 621 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); 622 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); 623 624 /* change pll BW 0.6M */ 625 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); 626 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); 627 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); 628 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); 629 630 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); 631 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); 632 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); 633 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); 634 635 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); 636 tmp &= ~P3A_RG_PLL_IR_PE2H; 637 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); 638 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); 639 640 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); 641 tmp &= ~P3A_RG_PLL_BP_PE2H; 642 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); 643 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); 644 645 /* Tx Detect Rx Timing: 10us -> 5us */ 646 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 647 tmp &= ~P3D_RG_RXDET_STB2_SET; 648 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 649 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 650 651 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 652 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 653 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 654 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 655 656 /* wait for PCIe subsys register to active */ 657 usleep_range(2500, 3000); 658 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 659 } 660 661 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, 662 struct mtk_phy_instance *instance) 663 { 664 struct u3phy_banks *bank = &instance->u3_banks; 665 u32 tmp; 666 667 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 668 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN | 669 P3C_REG_IP_SW_RST); 670 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 671 672 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 673 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 674 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 675 } 676 677 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, 678 struct mtk_phy_instance *instance) 679 680 { 681 struct u3phy_banks *bank = &instance->u3_banks; 682 u32 tmp; 683 684 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 685 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; 686 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 687 688 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 689 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; 690 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 691 } 692 693 static void sata_phy_instance_init(struct mtk_tphy *tphy, 694 struct mtk_phy_instance *instance) 695 { 696 struct u3phy_banks *u3_banks = &instance->u3_banks; 697 void __iomem *phyd = u3_banks->phyd; 698 u32 tmp; 699 700 /* charge current adjustment */ 701 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); 702 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); 703 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); 704 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); 705 706 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 707 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; 708 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); 709 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 710 711 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 712 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; 713 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); 714 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 715 716 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); 717 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); 718 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); 719 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); 720 721 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); 722 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); 723 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); 724 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); 725 726 tmp = readl(phyd + PHYD_DESIGN_OPTION2); 727 tmp &= ~RG_LOCK_CNT_SEL_MSK; 728 tmp |= RG_LOCK_CNT_SEL_VAL(0x02); 729 writel(tmp, phyd + PHYD_DESIGN_OPTION2); 730 731 tmp = readl(phyd + PHYD_DESIGN_OPTION9); 732 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | 733 RG_T2_MAX_MSK | RG_TG_MAX_MSK); 734 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | 735 RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e); 736 writel(tmp, phyd + PHYD_DESIGN_OPTION9); 737 738 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); 739 tmp &= ~RG_IDRV_0DB_GEN1_MSK; 740 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); 741 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); 742 743 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 744 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; 745 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); 746 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 747 748 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 749 } 750 751 static void phy_v1_banks_init(struct mtk_tphy *tphy, 752 struct mtk_phy_instance *instance) 753 { 754 struct u2phy_banks *u2_banks = &instance->u2_banks; 755 struct u3phy_banks *u3_banks = &instance->u3_banks; 756 757 switch (instance->type) { 758 case PHY_TYPE_USB2: 759 u2_banks->misc = NULL; 760 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; 761 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; 762 break; 763 case PHY_TYPE_USB3: 764 case PHY_TYPE_PCIE: 765 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; 766 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; 767 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 768 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; 769 break; 770 case PHY_TYPE_SATA: 771 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 772 break; 773 default: 774 dev_err(tphy->dev, "incompatible PHY type\n"); 775 return; 776 } 777 } 778 779 static void phy_v2_banks_init(struct mtk_tphy *tphy, 780 struct mtk_phy_instance *instance) 781 { 782 struct u2phy_banks *u2_banks = &instance->u2_banks; 783 struct u3phy_banks *u3_banks = &instance->u3_banks; 784 785 switch (instance->type) { 786 case PHY_TYPE_USB2: 787 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; 788 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; 789 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; 790 break; 791 case PHY_TYPE_USB3: 792 case PHY_TYPE_PCIE: 793 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; 794 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; 795 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; 796 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; 797 break; 798 default: 799 dev_err(tphy->dev, "incompatible PHY type\n"); 800 return; 801 } 802 } 803 804 static int mtk_phy_init(struct phy *phy) 805 { 806 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 807 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 808 int ret; 809 810 ret = clk_prepare_enable(tphy->u3phya_ref); 811 if (ret) { 812 dev_err(tphy->dev, "failed to enable u3phya_ref\n"); 813 return ret; 814 } 815 816 ret = clk_prepare_enable(instance->ref_clk); 817 if (ret) { 818 dev_err(tphy->dev, "failed to enable ref_clk\n"); 819 return ret; 820 } 821 822 switch (instance->type) { 823 case PHY_TYPE_USB2: 824 u2_phy_instance_init(tphy, instance); 825 break; 826 case PHY_TYPE_USB3: 827 u3_phy_instance_init(tphy, instance); 828 break; 829 case PHY_TYPE_PCIE: 830 pcie_phy_instance_init(tphy, instance); 831 break; 832 case PHY_TYPE_SATA: 833 sata_phy_instance_init(tphy, instance); 834 break; 835 default: 836 dev_err(tphy->dev, "incompatible PHY type\n"); 837 return -EINVAL; 838 } 839 840 return 0; 841 } 842 843 static int mtk_phy_power_on(struct phy *phy) 844 { 845 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 846 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 847 848 if (instance->type == PHY_TYPE_USB2) { 849 u2_phy_instance_power_on(tphy, instance); 850 hs_slew_rate_calibrate(tphy, instance); 851 } else if (instance->type == PHY_TYPE_PCIE) { 852 pcie_phy_instance_power_on(tphy, instance); 853 } 854 855 return 0; 856 } 857 858 static int mtk_phy_power_off(struct phy *phy) 859 { 860 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 861 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 862 863 if (instance->type == PHY_TYPE_USB2) 864 u2_phy_instance_power_off(tphy, instance); 865 else if (instance->type == PHY_TYPE_PCIE) 866 pcie_phy_instance_power_off(tphy, instance); 867 868 return 0; 869 } 870 871 static int mtk_phy_exit(struct phy *phy) 872 { 873 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 874 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 875 876 if (instance->type == PHY_TYPE_USB2) 877 u2_phy_instance_exit(tphy, instance); 878 879 clk_disable_unprepare(instance->ref_clk); 880 clk_disable_unprepare(tphy->u3phya_ref); 881 return 0; 882 } 883 884 static struct phy *mtk_phy_xlate(struct device *dev, 885 struct of_phandle_args *args) 886 { 887 struct mtk_tphy *tphy = dev_get_drvdata(dev); 888 struct mtk_phy_instance *instance = NULL; 889 struct device_node *phy_np = args->np; 890 int index; 891 892 if (args->args_count != 1) { 893 dev_err(dev, "invalid number of cells in 'phy' property\n"); 894 return ERR_PTR(-EINVAL); 895 } 896 897 for (index = 0; index < tphy->nphys; index++) 898 if (phy_np == tphy->phys[index]->phy->dev.of_node) { 899 instance = tphy->phys[index]; 900 break; 901 } 902 903 if (!instance) { 904 dev_err(dev, "failed to find appropriate phy\n"); 905 return ERR_PTR(-EINVAL); 906 } 907 908 instance->type = args->args[0]; 909 if (!(instance->type == PHY_TYPE_USB2 || 910 instance->type == PHY_TYPE_USB3 || 911 instance->type == PHY_TYPE_PCIE || 912 instance->type == PHY_TYPE_SATA)) { 913 dev_err(dev, "unsupported device type: %d\n", instance->type); 914 return ERR_PTR(-EINVAL); 915 } 916 917 if (tphy->pdata->version == MTK_PHY_V1) { 918 phy_v1_banks_init(tphy, instance); 919 } else if (tphy->pdata->version == MTK_PHY_V2) { 920 phy_v2_banks_init(tphy, instance); 921 } else { 922 dev_err(dev, "phy version is not supported\n"); 923 return ERR_PTR(-EINVAL); 924 } 925 926 return instance->phy; 927 } 928 929 static const struct phy_ops mtk_tphy_ops = { 930 .init = mtk_phy_init, 931 .exit = mtk_phy_exit, 932 .power_on = mtk_phy_power_on, 933 .power_off = mtk_phy_power_off, 934 .owner = THIS_MODULE, 935 }; 936 937 static const struct mtk_phy_pdata tphy_v1_pdata = { 938 .avoid_rx_sen_degradation = false, 939 .version = MTK_PHY_V1, 940 }; 941 942 static const struct mtk_phy_pdata tphy_v2_pdata = { 943 .avoid_rx_sen_degradation = false, 944 .version = MTK_PHY_V2, 945 }; 946 947 static const struct mtk_phy_pdata mt8173_pdata = { 948 .avoid_rx_sen_degradation = true, 949 .version = MTK_PHY_V1, 950 }; 951 952 static const struct of_device_id mtk_tphy_id_table[] = { 953 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, 954 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, 955 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, 956 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, 957 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, 958 { }, 959 }; 960 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); 961 962 static int mtk_tphy_probe(struct platform_device *pdev) 963 { 964 const struct of_device_id *match; 965 struct device *dev = &pdev->dev; 966 struct device_node *np = dev->of_node; 967 struct device_node *child_np; 968 struct phy_provider *provider; 969 struct resource *sif_res; 970 struct mtk_tphy *tphy; 971 struct resource res; 972 int port, retval; 973 974 match = of_match_node(mtk_tphy_id_table, pdev->dev.of_node); 975 if (!match) 976 return -EINVAL; 977 978 tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); 979 if (!tphy) 980 return -ENOMEM; 981 982 tphy->pdata = match->data; 983 tphy->nphys = of_get_child_count(np); 984 tphy->phys = devm_kcalloc(dev, tphy->nphys, 985 sizeof(*tphy->phys), GFP_KERNEL); 986 if (!tphy->phys) 987 return -ENOMEM; 988 989 tphy->dev = dev; 990 platform_set_drvdata(pdev, tphy); 991 992 if (tphy->pdata->version == MTK_PHY_V1) { 993 /* get banks shared by multiple phys */ 994 sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 995 tphy->sif_base = devm_ioremap_resource(dev, sif_res); 996 if (IS_ERR(tphy->sif_base)) { 997 dev_err(dev, "failed to remap sif regs\n"); 998 return PTR_ERR(tphy->sif_base); 999 } 1000 } 1001 1002 /* it's deprecated, make it optional for backward compatibility */ 1003 tphy->u3phya_ref = devm_clk_get(dev, "u3phya_ref"); 1004 if (IS_ERR(tphy->u3phya_ref)) { 1005 if (PTR_ERR(tphy->u3phya_ref) == -EPROBE_DEFER) 1006 return -EPROBE_DEFER; 1007 1008 tphy->u3phya_ref = NULL; 1009 } 1010 1011 port = 0; 1012 for_each_child_of_node(np, child_np) { 1013 struct mtk_phy_instance *instance; 1014 struct phy *phy; 1015 1016 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); 1017 if (!instance) { 1018 retval = -ENOMEM; 1019 goto put_child; 1020 } 1021 1022 tphy->phys[port] = instance; 1023 1024 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops); 1025 if (IS_ERR(phy)) { 1026 dev_err(dev, "failed to create phy\n"); 1027 retval = PTR_ERR(phy); 1028 goto put_child; 1029 } 1030 1031 retval = of_address_to_resource(child_np, 0, &res); 1032 if (retval) { 1033 dev_err(dev, "failed to get address resource(id-%d)\n", 1034 port); 1035 goto put_child; 1036 } 1037 1038 instance->port_base = devm_ioremap_resource(&phy->dev, &res); 1039 if (IS_ERR(instance->port_base)) { 1040 dev_err(dev, "failed to remap phy regs\n"); 1041 retval = PTR_ERR(instance->port_base); 1042 goto put_child; 1043 } 1044 1045 instance->phy = phy; 1046 instance->index = port; 1047 phy_set_drvdata(phy, instance); 1048 port++; 1049 1050 /* if deprecated clock is provided, ignore instance's one */ 1051 if (tphy->u3phya_ref) 1052 continue; 1053 1054 instance->ref_clk = devm_clk_get(&phy->dev, "ref"); 1055 if (IS_ERR(instance->ref_clk)) { 1056 dev_err(dev, "failed to get ref_clk(id-%d)\n", port); 1057 retval = PTR_ERR(instance->ref_clk); 1058 goto put_child; 1059 } 1060 } 1061 1062 provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); 1063 1064 return PTR_ERR_OR_ZERO(provider); 1065 put_child: 1066 of_node_put(child_np); 1067 return retval; 1068 } 1069 1070 static struct platform_driver mtk_tphy_driver = { 1071 .probe = mtk_tphy_probe, 1072 .driver = { 1073 .name = "mtk-tphy", 1074 .of_match_table = mtk_tphy_id_table, 1075 }, 1076 }; 1077 1078 module_platform_driver(mtk_tphy_driver); 1079 1080 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 1081 MODULE_DESCRIPTION("MediaTek T-PHY driver"); 1082 MODULE_LICENSE("GPL v2"); 1083