1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #include <dt-bindings/phy/phy.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 26 /* version V1 sub-banks offset base address */ 27 /* banks shared by multiple phys */ 28 #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ 29 #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ 30 #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ 31 /* u2 phy bank */ 32 #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 33 /* u3/pcie/sata phy banks */ 34 #define SSUSB_SIFSLV_V1_U3PHYD 0x000 35 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 36 37 /* version V2 sub-banks offset base address */ 38 /* u2 phy banks */ 39 #define SSUSB_SIFSLV_V2_MISC 0x000 40 #define SSUSB_SIFSLV_V2_U2FREQ 0x100 41 #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 42 /* u3/pcie/sata phy banks */ 43 #define SSUSB_SIFSLV_V2_SPLLC 0x000 44 #define SSUSB_SIFSLV_V2_CHIP 0x100 45 #define SSUSB_SIFSLV_V2_U3PHYD 0x200 46 #define SSUSB_SIFSLV_V2_U3PHYA 0x400 47 48 #define U3P_USBPHYACR0 0x000 49 #define PA0_RG_U2PLL_FORCE_ON BIT(15) 50 #define PA0_RG_USB20_INTR_EN BIT(5) 51 52 #define U3P_USBPHYACR2 0x008 53 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) 54 55 #define U3P_USBPHYACR5 0x014 56 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) 57 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) 58 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) 59 #define PA5_RG_U2_HS_100U_U3_EN BIT(11) 60 61 #define U3P_USBPHYACR6 0x018 62 #define PA6_RG_U2_BC11_SW_EN BIT(23) 63 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) 64 #define PA6_RG_U2_SQTH GENMASK(3, 0) 65 #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) 66 67 #define U3P_U2PHYACR4 0x020 68 #define P2C_RG_USB20_GPIO_CTL BIT(9) 69 #define P2C_USB20_GPIO_MODE BIT(8) 70 #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) 71 72 #define U3D_U2PHYDCR0 0x060 73 #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) 74 75 #define U3P_U2PHYDTM0 0x068 76 #define P2C_FORCE_UART_EN BIT(26) 77 #define P2C_FORCE_DATAIN BIT(23) 78 #define P2C_FORCE_DM_PULLDOWN BIT(21) 79 #define P2C_FORCE_DP_PULLDOWN BIT(20) 80 #define P2C_FORCE_XCVRSEL BIT(19) 81 #define P2C_FORCE_SUSPENDM BIT(18) 82 #define P2C_FORCE_TERMSEL BIT(17) 83 #define P2C_RG_DATAIN GENMASK(13, 10) 84 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) 85 #define P2C_RG_DMPULLDOWN BIT(7) 86 #define P2C_RG_DPPULLDOWN BIT(6) 87 #define P2C_RG_XCVRSEL GENMASK(5, 4) 88 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) 89 #define P2C_RG_SUSPENDM BIT(3) 90 #define P2C_RG_TERMSEL BIT(2) 91 #define P2C_DTM0_PART_MASK \ 92 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ 93 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ 94 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ 95 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) 96 97 #define U3P_U2PHYDTM1 0x06C 98 #define P2C_RG_UART_EN BIT(16) 99 #define P2C_FORCE_IDDIG BIT(9) 100 #define P2C_RG_VBUSVALID BIT(5) 101 #define P2C_RG_SESSEND BIT(4) 102 #define P2C_RG_AVALID BIT(2) 103 #define P2C_RG_IDDIG BIT(1) 104 105 #define U3P_U3_CHIP_GPIO_CTLD 0x0c 106 #define P3C_REG_IP_SW_RST BIT(31) 107 #define P3C_MCU_BUS_CK_GATE_EN BIT(30) 108 #define P3C_FORCE_IP_SW_RST BIT(29) 109 110 #define U3P_U3_CHIP_GPIO_CTLE 0x10 111 #define P3C_RG_SWRST_U3_PHYD BIT(25) 112 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) 113 114 #define U3P_U3_PHYA_REG0 0x000 115 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) 116 #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) 117 118 #define U3P_U3_PHYA_REG1 0x004 119 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) 120 #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) 121 122 #define U3P_U3_PHYA_REG6 0x018 123 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) 124 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) 125 126 #define U3P_U3_PHYA_REG9 0x024 127 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) 128 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) 129 130 #define U3P_U3_PHYA_DA_REG0 0x100 131 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) 132 #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) 133 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) 134 #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) 135 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) 136 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) 137 138 #define U3P_U3_PHYA_DA_REG4 0x108 139 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) 140 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) 141 #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) 142 143 #define U3P_U3_PHYA_DA_REG5 0x10c 144 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) 145 #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) 146 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) 147 #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) 148 149 #define U3P_U3_PHYA_DA_REG6 0x110 150 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) 151 #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) 152 153 #define U3P_U3_PHYA_DA_REG7 0x114 154 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) 155 #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) 156 157 #define U3P_U3_PHYA_DA_REG20 0x13c 158 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) 159 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) 160 161 #define U3P_U3_PHYA_DA_REG25 0x148 162 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) 163 #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) 164 165 #define U3P_U3_PHYD_LFPS1 0x00c 166 #define P3D_RG_FWAKE_TH GENMASK(21, 16) 167 #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) 168 169 #define U3P_U3_PHYD_CDR1 0x05c 170 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 171 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) 172 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 173 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) 174 175 #define U3P_U3_PHYD_RXDET1 0x128 176 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 177 #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) 178 179 #define U3P_U3_PHYD_RXDET2 0x12c 180 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) 181 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) 182 183 #define U3P_SPLLC_XTALCTL3 0x018 184 #define XC3_RG_U3_XTAL_RX_PWD BIT(9) 185 #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) 186 187 #define U3P_U2FREQ_FMCR0 0x00 188 #define P2F_RG_MONCLK_SEL GENMASK(27, 26) 189 #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) 190 #define P2F_RG_FREQDET_EN BIT(24) 191 #define P2F_RG_CYCLECNT GENMASK(23, 0) 192 #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) 193 194 #define U3P_U2FREQ_VALUE 0x0c 195 196 #define U3P_U2FREQ_FMMONR1 0x10 197 #define P2F_USB_FM_VALID BIT(0) 198 #define P2F_RG_FRCK_EN BIT(8) 199 200 #define U3P_REF_CLK 26 /* MHZ */ 201 #define U3P_SLEW_RATE_COEF 28 202 #define U3P_SR_COEF_DIVISOR 1000 203 #define U3P_FM_DET_CYCLE_CNT 1024 204 205 /* SATA register setting */ 206 #define PHYD_CTRL_SIGNAL_MODE4 0x1c 207 /* CDR Charge Pump P-path current adjustment */ 208 #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) 209 #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) 210 #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) 211 #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) 212 213 #define PHYD_DESIGN_OPTION2 0x24 214 /* Symbol lock count selection */ 215 #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) 216 #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) 217 218 #define PHYD_DESIGN_OPTION9 0x40 219 /* COMWAK GAP width window */ 220 #define RG_TG_MAX_MSK GENMASK(20, 16) 221 #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) 222 /* COMINIT GAP width window */ 223 #define RG_T2_MAX_MSK GENMASK(13, 8) 224 #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) 225 /* COMWAK GAP width window */ 226 #define RG_TG_MIN_MSK GENMASK(7, 5) 227 #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) 228 /* COMINIT GAP width window */ 229 #define RG_T2_MIN_MSK GENMASK(4, 0) 230 #define RG_T2_MIN_VAL(x) (0x1f & (x)) 231 232 #define ANA_RG_CTRL_SIGNAL1 0x4c 233 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ 234 #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) 235 #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) 236 237 #define ANA_RG_CTRL_SIGNAL4 0x58 238 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) 239 #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) 240 /* Loop filter R1 resistance adjustment for Gen1 speed */ 241 #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) 242 #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) 243 244 #define ANA_RG_CTRL_SIGNAL6 0x60 245 /* I-path capacitance adjustment for Gen1 */ 246 #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) 247 #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) 248 #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) 249 #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) 250 251 #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c 252 /* RX Gen1 LEQ tuning step */ 253 #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) 254 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) 255 256 #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 257 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) 258 #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) 259 260 #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc 261 #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) 262 #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) 263 264 enum mtk_phy_version { 265 MTK_PHY_V1 = 1, 266 MTK_PHY_V2, 267 }; 268 269 struct mtk_phy_pdata { 270 /* avoid RX sensitivity level degradation only for mt8173 */ 271 bool avoid_rx_sen_degradation; 272 enum mtk_phy_version version; 273 }; 274 275 struct u2phy_banks { 276 void __iomem *misc; 277 void __iomem *fmreg; 278 void __iomem *com; 279 }; 280 281 struct u3phy_banks { 282 void __iomem *spllc; 283 void __iomem *chip; 284 void __iomem *phyd; /* include u3phyd_bank2 */ 285 void __iomem *phya; /* include u3phya_da */ 286 }; 287 288 struct mtk_phy_instance { 289 struct phy *phy; 290 void __iomem *port_base; 291 union { 292 struct u2phy_banks u2_banks; 293 struct u3phy_banks u3_banks; 294 }; 295 struct clk *ref_clk; /* reference clock of anolog phy */ 296 u32 index; 297 u8 type; 298 }; 299 300 struct mtk_tphy { 301 struct device *dev; 302 void __iomem *sif_base; /* only shared sif */ 303 /* deprecated, use @ref_clk instead in phy instance */ 304 struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ 305 const struct mtk_phy_pdata *pdata; 306 struct mtk_phy_instance **phys; 307 int nphys; 308 }; 309 310 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, 311 struct mtk_phy_instance *instance) 312 { 313 struct u2phy_banks *u2_banks = &instance->u2_banks; 314 void __iomem *fmreg = u2_banks->fmreg; 315 void __iomem *com = u2_banks->com; 316 int calibration_val; 317 int fm_out; 318 u32 tmp; 319 320 /* enable USB ring oscillator */ 321 tmp = readl(com + U3P_USBPHYACR5); 322 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; 323 writel(tmp, com + U3P_USBPHYACR5); 324 udelay(1); 325 326 /*enable free run clock */ 327 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 328 tmp |= P2F_RG_FRCK_EN; 329 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 330 331 /* set cycle count as 1024, and select u2 channel */ 332 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 333 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); 334 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); 335 if (tphy->pdata->version == MTK_PHY_V1) 336 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); 337 338 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 339 340 /* enable frequency meter */ 341 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 342 tmp |= P2F_RG_FREQDET_EN; 343 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 344 345 /* ignore return value */ 346 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, 347 (tmp & P2F_USB_FM_VALID), 10, 200); 348 349 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); 350 351 /* disable frequency meter */ 352 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 353 tmp &= ~P2F_RG_FREQDET_EN; 354 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 355 356 /*disable free run clock */ 357 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 358 tmp &= ~P2F_RG_FRCK_EN; 359 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 360 361 if (fm_out) { 362 /* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */ 363 tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF; 364 tmp /= fm_out; 365 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); 366 } else { 367 /* if FM detection fail, set default value */ 368 calibration_val = 4; 369 } 370 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n", 371 instance->index, fm_out, calibration_val); 372 373 /* set HS slew rate */ 374 tmp = readl(com + U3P_USBPHYACR5); 375 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; 376 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); 377 writel(tmp, com + U3P_USBPHYACR5); 378 379 /* disable USB ring oscillator */ 380 tmp = readl(com + U3P_USBPHYACR5); 381 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; 382 writel(tmp, com + U3P_USBPHYACR5); 383 } 384 385 static void u3_phy_instance_init(struct mtk_tphy *tphy, 386 struct mtk_phy_instance *instance) 387 { 388 struct u3phy_banks *u3_banks = &instance->u3_banks; 389 u32 tmp; 390 391 /* gating PCIe Analog XTAL clock */ 392 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); 393 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; 394 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); 395 396 /* gating XSQ */ 397 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 398 tmp &= ~P3A_RG_XTAL_EXT_EN_U3; 399 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); 400 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 401 402 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); 403 tmp &= ~P3A_RG_RX_DAC_MUX; 404 tmp |= P3A_RG_RX_DAC_MUX_VAL(4); 405 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); 406 407 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); 408 tmp &= ~P3A_RG_TX_EIDLE_CM; 409 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); 410 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); 411 412 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); 413 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); 414 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); 415 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); 416 417 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); 418 tmp &= ~P3D_RG_FWAKE_TH; 419 tmp |= P3D_RG_FWAKE_TH_VAL(0x34); 420 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); 421 422 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 423 tmp &= ~P3D_RG_RXDET_STB2_SET; 424 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 425 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 426 427 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 428 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 429 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 430 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 431 432 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 433 } 434 435 static void u2_phy_instance_init(struct mtk_tphy *tphy, 436 struct mtk_phy_instance *instance) 437 { 438 struct u2phy_banks *u2_banks = &instance->u2_banks; 439 void __iomem *com = u2_banks->com; 440 u32 index = instance->index; 441 u32 tmp; 442 443 /* switch to USB function. (system register, force ip into usb mode) */ 444 tmp = readl(com + U3P_U2PHYDTM0); 445 tmp &= ~P2C_FORCE_UART_EN; 446 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); 447 writel(tmp, com + U3P_U2PHYDTM0); 448 449 tmp = readl(com + U3P_U2PHYDTM1); 450 tmp &= ~P2C_RG_UART_EN; 451 writel(tmp, com + U3P_U2PHYDTM1); 452 453 tmp = readl(com + U3P_USBPHYACR0); 454 tmp |= PA0_RG_USB20_INTR_EN; 455 writel(tmp, com + U3P_USBPHYACR0); 456 457 /* disable switch 100uA current to SSUSB */ 458 tmp = readl(com + U3P_USBPHYACR5); 459 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; 460 writel(tmp, com + U3P_USBPHYACR5); 461 462 if (!index) { 463 tmp = readl(com + U3P_U2PHYACR4); 464 tmp &= ~P2C_U2_GPIO_CTR_MSK; 465 writel(tmp, com + U3P_U2PHYACR4); 466 } 467 468 if (tphy->pdata->avoid_rx_sen_degradation) { 469 if (!index) { 470 tmp = readl(com + U3P_USBPHYACR2); 471 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; 472 writel(tmp, com + U3P_USBPHYACR2); 473 474 tmp = readl(com + U3D_U2PHYDCR0); 475 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 476 writel(tmp, com + U3D_U2PHYDCR0); 477 } else { 478 tmp = readl(com + U3D_U2PHYDCR0); 479 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 480 writel(tmp, com + U3D_U2PHYDCR0); 481 482 tmp = readl(com + U3P_U2PHYDTM0); 483 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 484 writel(tmp, com + U3P_U2PHYDTM0); 485 } 486 } 487 488 tmp = readl(com + U3P_USBPHYACR6); 489 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ 490 tmp &= ~PA6_RG_U2_SQTH; 491 tmp |= PA6_RG_U2_SQTH_VAL(2); 492 writel(tmp, com + U3P_USBPHYACR6); 493 494 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 495 } 496 497 static void u2_phy_instance_power_on(struct mtk_tphy *tphy, 498 struct mtk_phy_instance *instance) 499 { 500 struct u2phy_banks *u2_banks = &instance->u2_banks; 501 void __iomem *com = u2_banks->com; 502 u32 index = instance->index; 503 u32 tmp; 504 505 /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ 506 tmp = readl(com + U3P_U2PHYDTM0); 507 tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL); 508 tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK); 509 writel(tmp, com + U3P_U2PHYDTM0); 510 511 /* OTG Enable */ 512 tmp = readl(com + U3P_USBPHYACR6); 513 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; 514 writel(tmp, com + U3P_USBPHYACR6); 515 516 tmp = readl(com + U3P_U2PHYDTM1); 517 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; 518 tmp &= ~P2C_RG_SESSEND; 519 writel(tmp, com + U3P_U2PHYDTM1); 520 521 if (tphy->pdata->avoid_rx_sen_degradation && index) { 522 tmp = readl(com + U3D_U2PHYDCR0); 523 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 524 writel(tmp, com + U3D_U2PHYDCR0); 525 526 tmp = readl(com + U3P_U2PHYDTM0); 527 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 528 writel(tmp, com + U3P_U2PHYDTM0); 529 } 530 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 531 } 532 533 static void u2_phy_instance_power_off(struct mtk_tphy *tphy, 534 struct mtk_phy_instance *instance) 535 { 536 struct u2phy_banks *u2_banks = &instance->u2_banks; 537 void __iomem *com = u2_banks->com; 538 u32 index = instance->index; 539 u32 tmp; 540 541 tmp = readl(com + U3P_U2PHYDTM0); 542 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); 543 tmp |= P2C_FORCE_SUSPENDM; 544 writel(tmp, com + U3P_U2PHYDTM0); 545 546 /* OTG Disable */ 547 tmp = readl(com + U3P_USBPHYACR6); 548 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; 549 writel(tmp, com + U3P_USBPHYACR6); 550 551 /* let suspendm=0, set utmi into analog power down */ 552 tmp = readl(com + U3P_U2PHYDTM0); 553 tmp &= ~P2C_RG_SUSPENDM; 554 writel(tmp, com + U3P_U2PHYDTM0); 555 udelay(1); 556 557 tmp = readl(com + U3P_U2PHYDTM1); 558 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); 559 tmp |= P2C_RG_SESSEND; 560 writel(tmp, com + U3P_U2PHYDTM1); 561 562 if (tphy->pdata->avoid_rx_sen_degradation && index) { 563 tmp = readl(com + U3D_U2PHYDCR0); 564 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 565 writel(tmp, com + U3D_U2PHYDCR0); 566 } 567 568 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 569 } 570 571 static void u2_phy_instance_exit(struct mtk_tphy *tphy, 572 struct mtk_phy_instance *instance) 573 { 574 struct u2phy_banks *u2_banks = &instance->u2_banks; 575 void __iomem *com = u2_banks->com; 576 u32 index = instance->index; 577 u32 tmp; 578 579 if (tphy->pdata->avoid_rx_sen_degradation && index) { 580 tmp = readl(com + U3D_U2PHYDCR0); 581 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 582 writel(tmp, com + U3D_U2PHYDCR0); 583 584 tmp = readl(com + U3P_U2PHYDTM0); 585 tmp &= ~P2C_FORCE_SUSPENDM; 586 writel(tmp, com + U3P_U2PHYDTM0); 587 } 588 } 589 590 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, 591 struct mtk_phy_instance *instance, 592 enum phy_mode mode) 593 { 594 struct u2phy_banks *u2_banks = &instance->u2_banks; 595 u32 tmp; 596 597 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); 598 switch (mode) { 599 case PHY_MODE_USB_DEVICE: 600 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; 601 break; 602 case PHY_MODE_USB_HOST: 603 tmp |= P2C_FORCE_IDDIG; 604 tmp &= ~P2C_RG_IDDIG; 605 break; 606 case PHY_MODE_USB_OTG: 607 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); 608 break; 609 default: 610 return; 611 } 612 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); 613 } 614 615 static void pcie_phy_instance_init(struct mtk_tphy *tphy, 616 struct mtk_phy_instance *instance) 617 { 618 struct u3phy_banks *u3_banks = &instance->u3_banks; 619 u32 tmp; 620 621 if (tphy->pdata->version != MTK_PHY_V1) 622 return; 623 624 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 625 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); 626 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); 627 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 628 629 /* ref clk drive */ 630 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); 631 tmp &= ~P3A_RG_CLKDRV_AMP; 632 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); 633 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); 634 635 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); 636 tmp &= ~P3A_RG_CLKDRV_OFF; 637 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); 638 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); 639 640 /* SSC delta -5000ppm */ 641 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); 642 tmp &= ~P3A_RG_PLL_DELTA1_PE2H; 643 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); 644 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); 645 646 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); 647 tmp &= ~P3A_RG_PLL_DELTA_PE2H; 648 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); 649 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); 650 651 /* change pll BW 0.6M */ 652 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); 653 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); 654 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); 655 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); 656 657 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); 658 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); 659 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); 660 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); 661 662 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); 663 tmp &= ~P3A_RG_PLL_IR_PE2H; 664 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); 665 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); 666 667 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); 668 tmp &= ~P3A_RG_PLL_BP_PE2H; 669 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); 670 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); 671 672 /* Tx Detect Rx Timing: 10us -> 5us */ 673 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 674 tmp &= ~P3D_RG_RXDET_STB2_SET; 675 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 676 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 677 678 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 679 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 680 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 681 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 682 683 /* wait for PCIe subsys register to active */ 684 usleep_range(2500, 3000); 685 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 686 } 687 688 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, 689 struct mtk_phy_instance *instance) 690 { 691 struct u3phy_banks *bank = &instance->u3_banks; 692 u32 tmp; 693 694 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 695 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN | 696 P3C_REG_IP_SW_RST); 697 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 698 699 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 700 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 701 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 702 } 703 704 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, 705 struct mtk_phy_instance *instance) 706 707 { 708 struct u3phy_banks *bank = &instance->u3_banks; 709 u32 tmp; 710 711 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 712 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; 713 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 714 715 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 716 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; 717 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 718 } 719 720 static void sata_phy_instance_init(struct mtk_tphy *tphy, 721 struct mtk_phy_instance *instance) 722 { 723 struct u3phy_banks *u3_banks = &instance->u3_banks; 724 void __iomem *phyd = u3_banks->phyd; 725 u32 tmp; 726 727 /* charge current adjustment */ 728 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); 729 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); 730 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); 731 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); 732 733 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 734 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; 735 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); 736 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 737 738 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 739 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; 740 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); 741 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 742 743 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); 744 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); 745 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); 746 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); 747 748 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); 749 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); 750 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); 751 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); 752 753 tmp = readl(phyd + PHYD_DESIGN_OPTION2); 754 tmp &= ~RG_LOCK_CNT_SEL_MSK; 755 tmp |= RG_LOCK_CNT_SEL_VAL(0x02); 756 writel(tmp, phyd + PHYD_DESIGN_OPTION2); 757 758 tmp = readl(phyd + PHYD_DESIGN_OPTION9); 759 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | 760 RG_T2_MAX_MSK | RG_TG_MAX_MSK); 761 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | 762 RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e); 763 writel(tmp, phyd + PHYD_DESIGN_OPTION9); 764 765 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); 766 tmp &= ~RG_IDRV_0DB_GEN1_MSK; 767 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); 768 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); 769 770 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 771 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; 772 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); 773 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 774 775 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 776 } 777 778 static void phy_v1_banks_init(struct mtk_tphy *tphy, 779 struct mtk_phy_instance *instance) 780 { 781 struct u2phy_banks *u2_banks = &instance->u2_banks; 782 struct u3phy_banks *u3_banks = &instance->u3_banks; 783 784 switch (instance->type) { 785 case PHY_TYPE_USB2: 786 u2_banks->misc = NULL; 787 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; 788 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; 789 break; 790 case PHY_TYPE_USB3: 791 case PHY_TYPE_PCIE: 792 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; 793 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; 794 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 795 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; 796 break; 797 case PHY_TYPE_SATA: 798 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 799 break; 800 default: 801 dev_err(tphy->dev, "incompatible PHY type\n"); 802 return; 803 } 804 } 805 806 static void phy_v2_banks_init(struct mtk_tphy *tphy, 807 struct mtk_phy_instance *instance) 808 { 809 struct u2phy_banks *u2_banks = &instance->u2_banks; 810 struct u3phy_banks *u3_banks = &instance->u3_banks; 811 812 switch (instance->type) { 813 case PHY_TYPE_USB2: 814 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; 815 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; 816 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; 817 break; 818 case PHY_TYPE_USB3: 819 case PHY_TYPE_PCIE: 820 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; 821 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; 822 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; 823 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; 824 break; 825 default: 826 dev_err(tphy->dev, "incompatible PHY type\n"); 827 return; 828 } 829 } 830 831 static int mtk_phy_init(struct phy *phy) 832 { 833 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 834 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 835 int ret; 836 837 ret = clk_prepare_enable(tphy->u3phya_ref); 838 if (ret) { 839 dev_err(tphy->dev, "failed to enable u3phya_ref\n"); 840 return ret; 841 } 842 843 ret = clk_prepare_enable(instance->ref_clk); 844 if (ret) { 845 dev_err(tphy->dev, "failed to enable ref_clk\n"); 846 return ret; 847 } 848 849 switch (instance->type) { 850 case PHY_TYPE_USB2: 851 u2_phy_instance_init(tphy, instance); 852 break; 853 case PHY_TYPE_USB3: 854 u3_phy_instance_init(tphy, instance); 855 break; 856 case PHY_TYPE_PCIE: 857 pcie_phy_instance_init(tphy, instance); 858 break; 859 case PHY_TYPE_SATA: 860 sata_phy_instance_init(tphy, instance); 861 break; 862 default: 863 dev_err(tphy->dev, "incompatible PHY type\n"); 864 return -EINVAL; 865 } 866 867 return 0; 868 } 869 870 static int mtk_phy_power_on(struct phy *phy) 871 { 872 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 873 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 874 875 if (instance->type == PHY_TYPE_USB2) { 876 u2_phy_instance_power_on(tphy, instance); 877 hs_slew_rate_calibrate(tphy, instance); 878 } else if (instance->type == PHY_TYPE_PCIE) { 879 pcie_phy_instance_power_on(tphy, instance); 880 } 881 882 return 0; 883 } 884 885 static int mtk_phy_power_off(struct phy *phy) 886 { 887 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 888 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 889 890 if (instance->type == PHY_TYPE_USB2) 891 u2_phy_instance_power_off(tphy, instance); 892 else if (instance->type == PHY_TYPE_PCIE) 893 pcie_phy_instance_power_off(tphy, instance); 894 895 return 0; 896 } 897 898 static int mtk_phy_exit(struct phy *phy) 899 { 900 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 901 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 902 903 if (instance->type == PHY_TYPE_USB2) 904 u2_phy_instance_exit(tphy, instance); 905 906 clk_disable_unprepare(instance->ref_clk); 907 clk_disable_unprepare(tphy->u3phya_ref); 908 return 0; 909 } 910 911 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode) 912 { 913 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 914 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 915 916 if (instance->type == PHY_TYPE_USB2) 917 u2_phy_instance_set_mode(tphy, instance, mode); 918 919 return 0; 920 } 921 922 static struct phy *mtk_phy_xlate(struct device *dev, 923 struct of_phandle_args *args) 924 { 925 struct mtk_tphy *tphy = dev_get_drvdata(dev); 926 struct mtk_phy_instance *instance = NULL; 927 struct device_node *phy_np = args->np; 928 int index; 929 930 if (args->args_count != 1) { 931 dev_err(dev, "invalid number of cells in 'phy' property\n"); 932 return ERR_PTR(-EINVAL); 933 } 934 935 for (index = 0; index < tphy->nphys; index++) 936 if (phy_np == tphy->phys[index]->phy->dev.of_node) { 937 instance = tphy->phys[index]; 938 break; 939 } 940 941 if (!instance) { 942 dev_err(dev, "failed to find appropriate phy\n"); 943 return ERR_PTR(-EINVAL); 944 } 945 946 instance->type = args->args[0]; 947 if (!(instance->type == PHY_TYPE_USB2 || 948 instance->type == PHY_TYPE_USB3 || 949 instance->type == PHY_TYPE_PCIE || 950 instance->type == PHY_TYPE_SATA)) { 951 dev_err(dev, "unsupported device type: %d\n", instance->type); 952 return ERR_PTR(-EINVAL); 953 } 954 955 if (tphy->pdata->version == MTK_PHY_V1) { 956 phy_v1_banks_init(tphy, instance); 957 } else if (tphy->pdata->version == MTK_PHY_V2) { 958 phy_v2_banks_init(tphy, instance); 959 } else { 960 dev_err(dev, "phy version is not supported\n"); 961 return ERR_PTR(-EINVAL); 962 } 963 964 return instance->phy; 965 } 966 967 static const struct phy_ops mtk_tphy_ops = { 968 .init = mtk_phy_init, 969 .exit = mtk_phy_exit, 970 .power_on = mtk_phy_power_on, 971 .power_off = mtk_phy_power_off, 972 .set_mode = mtk_phy_set_mode, 973 .owner = THIS_MODULE, 974 }; 975 976 static const struct mtk_phy_pdata tphy_v1_pdata = { 977 .avoid_rx_sen_degradation = false, 978 .version = MTK_PHY_V1, 979 }; 980 981 static const struct mtk_phy_pdata tphy_v2_pdata = { 982 .avoid_rx_sen_degradation = false, 983 .version = MTK_PHY_V2, 984 }; 985 986 static const struct mtk_phy_pdata mt8173_pdata = { 987 .avoid_rx_sen_degradation = true, 988 .version = MTK_PHY_V1, 989 }; 990 991 static const struct of_device_id mtk_tphy_id_table[] = { 992 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, 993 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, 994 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, 995 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, 996 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, 997 { }, 998 }; 999 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); 1000 1001 static int mtk_tphy_probe(struct platform_device *pdev) 1002 { 1003 const struct of_device_id *match; 1004 struct device *dev = &pdev->dev; 1005 struct device_node *np = dev->of_node; 1006 struct device_node *child_np; 1007 struct phy_provider *provider; 1008 struct resource *sif_res; 1009 struct mtk_tphy *tphy; 1010 struct resource res; 1011 int port, retval; 1012 1013 match = of_match_node(mtk_tphy_id_table, pdev->dev.of_node); 1014 if (!match) 1015 return -EINVAL; 1016 1017 tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); 1018 if (!tphy) 1019 return -ENOMEM; 1020 1021 tphy->pdata = match->data; 1022 tphy->nphys = of_get_child_count(np); 1023 tphy->phys = devm_kcalloc(dev, tphy->nphys, 1024 sizeof(*tphy->phys), GFP_KERNEL); 1025 if (!tphy->phys) 1026 return -ENOMEM; 1027 1028 tphy->dev = dev; 1029 platform_set_drvdata(pdev, tphy); 1030 1031 if (tphy->pdata->version == MTK_PHY_V1) { 1032 /* get banks shared by multiple phys */ 1033 sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1034 tphy->sif_base = devm_ioremap_resource(dev, sif_res); 1035 if (IS_ERR(tphy->sif_base)) { 1036 dev_err(dev, "failed to remap sif regs\n"); 1037 return PTR_ERR(tphy->sif_base); 1038 } 1039 } 1040 1041 /* it's deprecated, make it optional for backward compatibility */ 1042 tphy->u3phya_ref = devm_clk_get(dev, "u3phya_ref"); 1043 if (IS_ERR(tphy->u3phya_ref)) { 1044 if (PTR_ERR(tphy->u3phya_ref) == -EPROBE_DEFER) 1045 return -EPROBE_DEFER; 1046 1047 tphy->u3phya_ref = NULL; 1048 } 1049 1050 port = 0; 1051 for_each_child_of_node(np, child_np) { 1052 struct mtk_phy_instance *instance; 1053 struct phy *phy; 1054 1055 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); 1056 if (!instance) { 1057 retval = -ENOMEM; 1058 goto put_child; 1059 } 1060 1061 tphy->phys[port] = instance; 1062 1063 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops); 1064 if (IS_ERR(phy)) { 1065 dev_err(dev, "failed to create phy\n"); 1066 retval = PTR_ERR(phy); 1067 goto put_child; 1068 } 1069 1070 retval = of_address_to_resource(child_np, 0, &res); 1071 if (retval) { 1072 dev_err(dev, "failed to get address resource(id-%d)\n", 1073 port); 1074 goto put_child; 1075 } 1076 1077 instance->port_base = devm_ioremap_resource(&phy->dev, &res); 1078 if (IS_ERR(instance->port_base)) { 1079 dev_err(dev, "failed to remap phy regs\n"); 1080 retval = PTR_ERR(instance->port_base); 1081 goto put_child; 1082 } 1083 1084 instance->phy = phy; 1085 instance->index = port; 1086 phy_set_drvdata(phy, instance); 1087 port++; 1088 1089 /* if deprecated clock is provided, ignore instance's one */ 1090 if (tphy->u3phya_ref) 1091 continue; 1092 1093 instance->ref_clk = devm_clk_get(&phy->dev, "ref"); 1094 if (IS_ERR(instance->ref_clk)) { 1095 dev_err(dev, "failed to get ref_clk(id-%d)\n", port); 1096 retval = PTR_ERR(instance->ref_clk); 1097 goto put_child; 1098 } 1099 } 1100 1101 provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); 1102 1103 return PTR_ERR_OR_ZERO(provider); 1104 put_child: 1105 of_node_put(child_np); 1106 return retval; 1107 } 1108 1109 static struct platform_driver mtk_tphy_driver = { 1110 .probe = mtk_tphy_probe, 1111 .driver = { 1112 .name = "mtk-tphy", 1113 .of_match_table = mtk_tphy_id_table, 1114 }, 1115 }; 1116 1117 module_platform_driver(mtk_tphy_driver); 1118 1119 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 1120 MODULE_DESCRIPTION("MediaTek T-PHY driver"); 1121 MODULE_LICENSE("GPL v2"); 1122