1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5  *
6  */
7 
8 #include <dt-bindings/phy/phy.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 
19 /* version V1 sub-banks offset base address */
20 /* banks shared by multiple phys */
21 #define SSUSB_SIFSLV_V1_SPLLC		0x000	/* shared by u3 phys */
22 #define SSUSB_SIFSLV_V1_U2FREQ		0x100	/* shared by u2 phys */
23 #define SSUSB_SIFSLV_V1_CHIP		0x300	/* shared by u3 phys */
24 /* u2 phy bank */
25 #define SSUSB_SIFSLV_V1_U2PHY_COM	0x000
26 /* u3/pcie/sata phy banks */
27 #define SSUSB_SIFSLV_V1_U3PHYD		0x000
28 #define SSUSB_SIFSLV_V1_U3PHYA		0x200
29 
30 /* version V2 sub-banks offset base address */
31 /* u2 phy banks */
32 #define SSUSB_SIFSLV_V2_MISC		0x000
33 #define SSUSB_SIFSLV_V2_U2FREQ		0x100
34 #define SSUSB_SIFSLV_V2_U2PHY_COM	0x300
35 /* u3/pcie/sata phy banks */
36 #define SSUSB_SIFSLV_V2_SPLLC		0x000
37 #define SSUSB_SIFSLV_V2_CHIP		0x100
38 #define SSUSB_SIFSLV_V2_U3PHYD		0x200
39 #define SSUSB_SIFSLV_V2_U3PHYA		0x400
40 
41 #define U3P_USBPHYACR0		0x000
42 #define PA0_RG_U2PLL_FORCE_ON		BIT(15)
43 #define PA0_RG_USB20_INTR_EN		BIT(5)
44 
45 #define U3P_USBPHYACR1		0x004
46 #define PA1_RG_INTR_CAL		GENMASK(23, 19)
47 #define PA1_RG_INTR_CAL_VAL(x)	((0x1f & (x)) << 19)
48 #define PA1_RG_VRT_SEL			GENMASK(14, 12)
49 #define PA1_RG_VRT_SEL_VAL(x)	((0x7 & (x)) << 12)
50 #define PA1_RG_TERM_SEL		GENMASK(10, 8)
51 #define PA1_RG_TERM_SEL_VAL(x)	((0x7 & (x)) << 8)
52 
53 #define U3P_USBPHYACR2		0x008
54 #define PA2_RG_SIF_U2PLL_FORCE_EN	BIT(18)
55 
56 #define U3P_USBPHYACR5		0x014
57 #define PA5_RG_U2_HSTX_SRCAL_EN	BIT(15)
58 #define PA5_RG_U2_HSTX_SRCTRL		GENMASK(14, 12)
59 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x)	((0x7 & (x)) << 12)
60 #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
61 
62 #define U3P_USBPHYACR6		0x018
63 #define PA6_RG_U2_BC11_SW_EN		BIT(23)
64 #define PA6_RG_U2_OTG_VBUSCMP_EN	BIT(20)
65 #define PA6_RG_U2_DISCTH		GENMASK(7, 4)
66 #define PA6_RG_U2_DISCTH_VAL(x)	((0xf & (x)) << 4)
67 #define PA6_RG_U2_SQTH		GENMASK(3, 0)
68 #define PA6_RG_U2_SQTH_VAL(x)	(0xf & (x))
69 
70 #define U3P_U2PHYACR4		0x020
71 #define P2C_RG_USB20_GPIO_CTL		BIT(9)
72 #define P2C_USB20_GPIO_MODE		BIT(8)
73 #define P2C_U2_GPIO_CTR_MSK	(P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
74 
75 #define U3D_U2PHYDCR0		0x060
76 #define P2C_RG_SIF_U2PLL_FORCE_ON	BIT(24)
77 
78 #define U3P_U2PHYDTM0		0x068
79 #define P2C_FORCE_UART_EN		BIT(26)
80 #define P2C_FORCE_DATAIN		BIT(23)
81 #define P2C_FORCE_DM_PULLDOWN		BIT(21)
82 #define P2C_FORCE_DP_PULLDOWN		BIT(20)
83 #define P2C_FORCE_XCVRSEL		BIT(19)
84 #define P2C_FORCE_SUSPENDM		BIT(18)
85 #define P2C_FORCE_TERMSEL		BIT(17)
86 #define P2C_RG_DATAIN			GENMASK(13, 10)
87 #define P2C_RG_DATAIN_VAL(x)		((0xf & (x)) << 10)
88 #define P2C_RG_DMPULLDOWN		BIT(7)
89 #define P2C_RG_DPPULLDOWN		BIT(6)
90 #define P2C_RG_XCVRSEL			GENMASK(5, 4)
91 #define P2C_RG_XCVRSEL_VAL(x)		((0x3 & (x)) << 4)
92 #define P2C_RG_SUSPENDM			BIT(3)
93 #define P2C_RG_TERMSEL			BIT(2)
94 #define P2C_DTM0_PART_MASK \
95 		(P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
96 		P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
97 		P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
98 		P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
99 
100 #define U3P_U2PHYDTM1		0x06C
101 #define P2C_RG_UART_EN			BIT(16)
102 #define P2C_FORCE_IDDIG		BIT(9)
103 #define P2C_RG_VBUSVALID		BIT(5)
104 #define P2C_RG_SESSEND			BIT(4)
105 #define P2C_RG_AVALID			BIT(2)
106 #define P2C_RG_IDDIG			BIT(1)
107 
108 #define U3P_U2PHYBC12C		0x080
109 #define P2C_RG_CHGDT_EN		BIT(0)
110 
111 #define U3P_U3_CHIP_GPIO_CTLD		0x0c
112 #define P3C_REG_IP_SW_RST		BIT(31)
113 #define P3C_MCU_BUS_CK_GATE_EN		BIT(30)
114 #define P3C_FORCE_IP_SW_RST		BIT(29)
115 
116 #define U3P_U3_CHIP_GPIO_CTLE		0x10
117 #define P3C_RG_SWRST_U3_PHYD		BIT(25)
118 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN	BIT(24)
119 
120 #define U3P_U3_PHYA_REG0	0x000
121 #define P3A_RG_CLKDRV_OFF		GENMASK(3, 2)
122 #define P3A_RG_CLKDRV_OFF_VAL(x)	((0x3 & (x)) << 2)
123 
124 #define U3P_U3_PHYA_REG1	0x004
125 #define P3A_RG_CLKDRV_AMP		GENMASK(31, 29)
126 #define P3A_RG_CLKDRV_AMP_VAL(x)	((0x7 & (x)) << 29)
127 
128 #define U3P_U3_PHYA_REG6	0x018
129 #define P3A_RG_TX_EIDLE_CM		GENMASK(31, 28)
130 #define P3A_RG_TX_EIDLE_CM_VAL(x)	((0xf & (x)) << 28)
131 
132 #define U3P_U3_PHYA_REG9	0x024
133 #define P3A_RG_RX_DAC_MUX		GENMASK(5, 1)
134 #define P3A_RG_RX_DAC_MUX_VAL(x)	((0x1f & (x)) << 1)
135 
136 #define U3P_U3_PHYA_DA_REG0	0x100
137 #define P3A_RG_XTAL_EXT_PE2H		GENMASK(17, 16)
138 #define P3A_RG_XTAL_EXT_PE2H_VAL(x)	((0x3 & (x)) << 16)
139 #define P3A_RG_XTAL_EXT_PE1H		GENMASK(13, 12)
140 #define P3A_RG_XTAL_EXT_PE1H_VAL(x)	((0x3 & (x)) << 12)
141 #define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
142 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)	((0x3 & (x)) << 10)
143 
144 #define U3P_U3_PHYA_DA_REG4	0x108
145 #define P3A_RG_PLL_DIVEN_PE2H		GENMASK(21, 19)
146 #define P3A_RG_PLL_BC_PE2H		GENMASK(7, 6)
147 #define P3A_RG_PLL_BC_PE2H_VAL(x)	((0x3 & (x)) << 6)
148 
149 #define U3P_U3_PHYA_DA_REG5	0x10c
150 #define P3A_RG_PLL_BR_PE2H		GENMASK(29, 28)
151 #define P3A_RG_PLL_BR_PE2H_VAL(x)	((0x3 & (x)) << 28)
152 #define P3A_RG_PLL_IC_PE2H		GENMASK(15, 12)
153 #define P3A_RG_PLL_IC_PE2H_VAL(x)	((0xf & (x)) << 12)
154 
155 #define U3P_U3_PHYA_DA_REG6	0x110
156 #define P3A_RG_PLL_IR_PE2H		GENMASK(19, 16)
157 #define P3A_RG_PLL_IR_PE2H_VAL(x)	((0xf & (x)) << 16)
158 
159 #define U3P_U3_PHYA_DA_REG7	0x114
160 #define P3A_RG_PLL_BP_PE2H		GENMASK(19, 16)
161 #define P3A_RG_PLL_BP_PE2H_VAL(x)	((0xf & (x)) << 16)
162 
163 #define U3P_U3_PHYA_DA_REG20	0x13c
164 #define P3A_RG_PLL_DELTA1_PE2H		GENMASK(31, 16)
165 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x)	((0xffff & (x)) << 16)
166 
167 #define U3P_U3_PHYA_DA_REG25	0x148
168 #define P3A_RG_PLL_DELTA_PE2H		GENMASK(15, 0)
169 #define P3A_RG_PLL_DELTA_PE2H_VAL(x)	(0xffff & (x))
170 
171 #define U3P_U3_PHYD_LFPS1		0x00c
172 #define P3D_RG_FWAKE_TH		GENMASK(21, 16)
173 #define P3D_RG_FWAKE_TH_VAL(x)	((0x3f & (x)) << 16)
174 
175 #define U3P_U3_PHYD_CDR1		0x05c
176 #define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
177 #define P3D_RG_CDR_BIR_LTD1_VAL(x)	((0x1f & (x)) << 24)
178 #define P3D_RG_CDR_BIR_LTD0		GENMASK(12, 8)
179 #define P3D_RG_CDR_BIR_LTD0_VAL(x)	((0x1f & (x)) << 8)
180 
181 #define U3P_U3_PHYD_RXDET1		0x128
182 #define P3D_RG_RXDET_STB2_SET		GENMASK(17, 9)
183 #define P3D_RG_RXDET_STB2_SET_VAL(x)	((0x1ff & (x)) << 9)
184 
185 #define U3P_U3_PHYD_RXDET2		0x12c
186 #define P3D_RG_RXDET_STB2_SET_P3	GENMASK(8, 0)
187 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x)	(0x1ff & (x))
188 
189 #define U3P_SPLLC_XTALCTL3		0x018
190 #define XC3_RG_U3_XTAL_RX_PWD		BIT(9)
191 #define XC3_RG_U3_FRC_XTAL_RX_PWD	BIT(8)
192 
193 #define U3P_U2FREQ_FMCR0	0x00
194 #define P2F_RG_MONCLK_SEL	GENMASK(27, 26)
195 #define P2F_RG_MONCLK_SEL_VAL(x)	((0x3 & (x)) << 26)
196 #define P2F_RG_FREQDET_EN	BIT(24)
197 #define P2F_RG_CYCLECNT		GENMASK(23, 0)
198 #define P2F_RG_CYCLECNT_VAL(x)	((P2F_RG_CYCLECNT) & (x))
199 
200 #define U3P_U2FREQ_VALUE	0x0c
201 
202 #define U3P_U2FREQ_FMMONR1	0x10
203 #define P2F_USB_FM_VALID	BIT(0)
204 #define P2F_RG_FRCK_EN		BIT(8)
205 
206 #define U3P_REF_CLK		26	/* MHZ */
207 #define U3P_SLEW_RATE_COEF	28
208 #define U3P_SR_COEF_DIVISOR	1000
209 #define U3P_FM_DET_CYCLE_CNT	1024
210 
211 /* SATA register setting */
212 #define PHYD_CTRL_SIGNAL_MODE4		0x1c
213 /* CDR Charge Pump P-path current adjustment */
214 #define RG_CDR_BICLTD1_GEN1_MSK		GENMASK(23, 20)
215 #define RG_CDR_BICLTD1_GEN1_VAL(x)	((0xf & (x)) << 20)
216 #define RG_CDR_BICLTD0_GEN1_MSK		GENMASK(11, 8)
217 #define RG_CDR_BICLTD0_GEN1_VAL(x)	((0xf & (x)) << 8)
218 
219 #define PHYD_DESIGN_OPTION2		0x24
220 /* Symbol lock count selection */
221 #define RG_LOCK_CNT_SEL_MSK		GENMASK(5, 4)
222 #define RG_LOCK_CNT_SEL_VAL(x)		((0x3 & (x)) << 4)
223 
224 #define PHYD_DESIGN_OPTION9	0x40
225 /* COMWAK GAP width window */
226 #define RG_TG_MAX_MSK		GENMASK(20, 16)
227 #define RG_TG_MAX_VAL(x)	((0x1f & (x)) << 16)
228 /* COMINIT GAP width window */
229 #define RG_T2_MAX_MSK		GENMASK(13, 8)
230 #define RG_T2_MAX_VAL(x)	((0x3f & (x)) << 8)
231 /* COMWAK GAP width window */
232 #define RG_TG_MIN_MSK		GENMASK(7, 5)
233 #define RG_TG_MIN_VAL(x)	((0x7 & (x)) << 5)
234 /* COMINIT GAP width window */
235 #define RG_T2_MIN_MSK		GENMASK(4, 0)
236 #define RG_T2_MIN_VAL(x)	(0x1f & (x))
237 
238 #define ANA_RG_CTRL_SIGNAL1		0x4c
239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
240 #define RG_IDRV_0DB_GEN1_MSK		GENMASK(13, 8)
241 #define RG_IDRV_0DB_GEN1_VAL(x)		((0x3f & (x)) << 8)
242 
243 #define ANA_RG_CTRL_SIGNAL4		0x58
244 #define RG_CDR_BICLTR_GEN1_MSK		GENMASK(23, 20)
245 #define RG_CDR_BICLTR_GEN1_VAL(x)	((0xf & (x)) << 20)
246 /* Loop filter R1 resistance adjustment for Gen1 speed */
247 #define RG_CDR_BR_GEN2_MSK		GENMASK(10, 8)
248 #define RG_CDR_BR_GEN2_VAL(x)		((0x7 & (x)) << 8)
249 
250 #define ANA_RG_CTRL_SIGNAL6		0x60
251 /* I-path capacitance adjustment for Gen1 */
252 #define RG_CDR_BC_GEN1_MSK		GENMASK(28, 24)
253 #define RG_CDR_BC_GEN1_VAL(x)		((0x1f & (x)) << 24)
254 #define RG_CDR_BIRLTR_GEN1_MSK		GENMASK(4, 0)
255 #define RG_CDR_BIRLTR_GEN1_VAL(x)	(0x1f & (x))
256 
257 #define ANA_EQ_EYE_CTRL_SIGNAL1		0x6c
258 /* RX Gen1 LEQ tuning step */
259 #define RG_EQ_DLEQ_LFI_GEN1_MSK		GENMASK(11, 8)
260 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x)	((0xf & (x)) << 8)
261 
262 #define ANA_EQ_EYE_CTRL_SIGNAL4		0xd8
263 #define RG_CDR_BIRLTD0_GEN1_MSK		GENMASK(20, 16)
264 #define RG_CDR_BIRLTD0_GEN1_VAL(x)	((0x1f & (x)) << 16)
265 
266 #define ANA_EQ_EYE_CTRL_SIGNAL5		0xdc
267 #define RG_CDR_BIRLTD0_GEN3_MSK		GENMASK(4, 0)
268 #define RG_CDR_BIRLTD0_GEN3_VAL(x)	(0x1f & (x))
269 
270 enum mtk_phy_version {
271 	MTK_PHY_V1 = 1,
272 	MTK_PHY_V2,
273 };
274 
275 struct mtk_phy_pdata {
276 	/* avoid RX sensitivity level degradation only for mt8173 */
277 	bool avoid_rx_sen_degradation;
278 	enum mtk_phy_version version;
279 };
280 
281 struct u2phy_banks {
282 	void __iomem *misc;
283 	void __iomem *fmreg;
284 	void __iomem *com;
285 };
286 
287 struct u3phy_banks {
288 	void __iomem *spllc;
289 	void __iomem *chip;
290 	void __iomem *phyd; /* include u3phyd_bank2 */
291 	void __iomem *phya; /* include u3phya_da */
292 };
293 
294 struct mtk_phy_instance {
295 	struct phy *phy;
296 	void __iomem *port_base;
297 	union {
298 		struct u2phy_banks u2_banks;
299 		struct u3phy_banks u3_banks;
300 	};
301 	struct clk *ref_clk;	/* reference clock of (digital) phy */
302 	struct clk *da_ref_clk;	/* reference clock of analog phy */
303 	u32 index;
304 	u8 type;
305 	int eye_src;
306 	int eye_vrt;
307 	int eye_term;
308 	int intr;
309 	int discth;
310 	bool bc12_en;
311 };
312 
313 struct mtk_tphy {
314 	struct device *dev;
315 	void __iomem *sif_base;	/* only shared sif */
316 	const struct mtk_phy_pdata *pdata;
317 	struct mtk_phy_instance **phys;
318 	int nphys;
319 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
320 	int src_coef; /* coefficient for slew rate calibrate */
321 };
322 
323 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
324 	struct mtk_phy_instance *instance)
325 {
326 	struct u2phy_banks *u2_banks = &instance->u2_banks;
327 	void __iomem *fmreg = u2_banks->fmreg;
328 	void __iomem *com = u2_banks->com;
329 	int calibration_val;
330 	int fm_out;
331 	u32 tmp;
332 
333 	/* use force value */
334 	if (instance->eye_src)
335 		return;
336 
337 	/* enable USB ring oscillator */
338 	tmp = readl(com + U3P_USBPHYACR5);
339 	tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
340 	writel(tmp, com + U3P_USBPHYACR5);
341 	udelay(1);
342 
343 	/*enable free run clock */
344 	tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
345 	tmp |= P2F_RG_FRCK_EN;
346 	writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
347 
348 	/* set cycle count as 1024, and select u2 channel */
349 	tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
350 	tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
351 	tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
352 	if (tphy->pdata->version == MTK_PHY_V1)
353 		tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
354 
355 	writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
356 
357 	/* enable frequency meter */
358 	tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
359 	tmp |= P2F_RG_FREQDET_EN;
360 	writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
361 
362 	/* ignore return value */
363 	readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
364 			   (tmp & P2F_USB_FM_VALID), 10, 200);
365 
366 	fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
367 
368 	/* disable frequency meter */
369 	tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
370 	tmp &= ~P2F_RG_FREQDET_EN;
371 	writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
372 
373 	/*disable free run clock */
374 	tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
375 	tmp &= ~P2F_RG_FRCK_EN;
376 	writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
377 
378 	if (fm_out) {
379 		/* ( 1024 / FM_OUT ) x reference clock frequency x coef */
380 		tmp = tphy->src_ref_clk * tphy->src_coef;
381 		tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
382 		calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
383 	} else {
384 		/* if FM detection fail, set default value */
385 		calibration_val = 4;
386 	}
387 	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
388 		instance->index, fm_out, calibration_val,
389 		tphy->src_ref_clk, tphy->src_coef);
390 
391 	/* set HS slew rate */
392 	tmp = readl(com + U3P_USBPHYACR5);
393 	tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
394 	tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
395 	writel(tmp, com + U3P_USBPHYACR5);
396 
397 	/* disable USB ring oscillator */
398 	tmp = readl(com + U3P_USBPHYACR5);
399 	tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
400 	writel(tmp, com + U3P_USBPHYACR5);
401 }
402 
403 static void u3_phy_instance_init(struct mtk_tphy *tphy,
404 	struct mtk_phy_instance *instance)
405 {
406 	struct u3phy_banks *u3_banks = &instance->u3_banks;
407 	u32 tmp;
408 
409 	/* gating PCIe Analog XTAL clock */
410 	tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
411 	tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
412 	writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
413 
414 	/* gating XSQ */
415 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
416 	tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
417 	tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
418 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
419 
420 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
421 	tmp &= ~P3A_RG_RX_DAC_MUX;
422 	tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
423 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
424 
425 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
426 	tmp &= ~P3A_RG_TX_EIDLE_CM;
427 	tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
428 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
429 
430 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
431 	tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
432 	tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
433 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
434 
435 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);
436 	tmp &= ~P3D_RG_FWAKE_TH;
437 	tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
438 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);
439 
440 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
441 	tmp &= ~P3D_RG_RXDET_STB2_SET;
442 	tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
443 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
444 
445 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
446 	tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
447 	tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
448 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
449 
450 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
451 }
452 
453 static void u2_phy_instance_init(struct mtk_tphy *tphy,
454 	struct mtk_phy_instance *instance)
455 {
456 	struct u2phy_banks *u2_banks = &instance->u2_banks;
457 	void __iomem *com = u2_banks->com;
458 	u32 index = instance->index;
459 	u32 tmp;
460 
461 	/* switch to USB function, and enable usb pll */
462 	tmp = readl(com + U3P_U2PHYDTM0);
463 	tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
464 	tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
465 	writel(tmp, com + U3P_U2PHYDTM0);
466 
467 	tmp = readl(com + U3P_U2PHYDTM1);
468 	tmp &= ~P2C_RG_UART_EN;
469 	writel(tmp, com + U3P_U2PHYDTM1);
470 
471 	tmp = readl(com + U3P_USBPHYACR0);
472 	tmp |= PA0_RG_USB20_INTR_EN;
473 	writel(tmp, com + U3P_USBPHYACR0);
474 
475 	/* disable switch 100uA current to SSUSB */
476 	tmp = readl(com + U3P_USBPHYACR5);
477 	tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
478 	writel(tmp, com + U3P_USBPHYACR5);
479 
480 	if (!index) {
481 		tmp = readl(com + U3P_U2PHYACR4);
482 		tmp &= ~P2C_U2_GPIO_CTR_MSK;
483 		writel(tmp, com + U3P_U2PHYACR4);
484 	}
485 
486 	if (tphy->pdata->avoid_rx_sen_degradation) {
487 		if (!index) {
488 			tmp = readl(com + U3P_USBPHYACR2);
489 			tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
490 			writel(tmp, com + U3P_USBPHYACR2);
491 
492 			tmp = readl(com + U3D_U2PHYDCR0);
493 			tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
494 			writel(tmp, com + U3D_U2PHYDCR0);
495 		} else {
496 			tmp = readl(com + U3D_U2PHYDCR0);
497 			tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
498 			writel(tmp, com + U3D_U2PHYDCR0);
499 
500 			tmp = readl(com + U3P_U2PHYDTM0);
501 			tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
502 			writel(tmp, com + U3P_U2PHYDTM0);
503 		}
504 	}
505 
506 	tmp = readl(com + U3P_USBPHYACR6);
507 	tmp &= ~PA6_RG_U2_BC11_SW_EN;	/* DP/DM BC1.1 path Disable */
508 	tmp &= ~PA6_RG_U2_SQTH;
509 	tmp |= PA6_RG_U2_SQTH_VAL(2);
510 	writel(tmp, com + U3P_USBPHYACR6);
511 
512 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
513 }
514 
515 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
516 	struct mtk_phy_instance *instance)
517 {
518 	struct u2phy_banks *u2_banks = &instance->u2_banks;
519 	void __iomem *com = u2_banks->com;
520 	u32 index = instance->index;
521 	u32 tmp;
522 
523 	tmp = readl(com + U3P_U2PHYDTM0);
524 	tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
525 	writel(tmp, com + U3P_U2PHYDTM0);
526 
527 	/* OTG Enable */
528 	tmp = readl(com + U3P_USBPHYACR6);
529 	tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
530 	writel(tmp, com + U3P_USBPHYACR6);
531 
532 	tmp = readl(com + U3P_U2PHYDTM1);
533 	tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
534 	tmp &= ~P2C_RG_SESSEND;
535 	writel(tmp, com + U3P_U2PHYDTM1);
536 
537 	if (tphy->pdata->avoid_rx_sen_degradation && index) {
538 		tmp = readl(com + U3D_U2PHYDCR0);
539 		tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
540 		writel(tmp, com + U3D_U2PHYDCR0);
541 
542 		tmp = readl(com + U3P_U2PHYDTM0);
543 		tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
544 		writel(tmp, com + U3P_U2PHYDTM0);
545 	}
546 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
547 }
548 
549 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
550 	struct mtk_phy_instance *instance)
551 {
552 	struct u2phy_banks *u2_banks = &instance->u2_banks;
553 	void __iomem *com = u2_banks->com;
554 	u32 index = instance->index;
555 	u32 tmp;
556 
557 	tmp = readl(com + U3P_U2PHYDTM0);
558 	tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
559 	writel(tmp, com + U3P_U2PHYDTM0);
560 
561 	/* OTG Disable */
562 	tmp = readl(com + U3P_USBPHYACR6);
563 	tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
564 	writel(tmp, com + U3P_USBPHYACR6);
565 
566 	tmp = readl(com + U3P_U2PHYDTM1);
567 	tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
568 	tmp |= P2C_RG_SESSEND;
569 	writel(tmp, com + U3P_U2PHYDTM1);
570 
571 	if (tphy->pdata->avoid_rx_sen_degradation && index) {
572 		tmp = readl(com + U3P_U2PHYDTM0);
573 		tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
574 		writel(tmp, com + U3P_U2PHYDTM0);
575 
576 		tmp = readl(com + U3D_U2PHYDCR0);
577 		tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
578 		writel(tmp, com + U3D_U2PHYDCR0);
579 	}
580 
581 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
582 }
583 
584 static void u2_phy_instance_exit(struct mtk_tphy *tphy,
585 	struct mtk_phy_instance *instance)
586 {
587 	struct u2phy_banks *u2_banks = &instance->u2_banks;
588 	void __iomem *com = u2_banks->com;
589 	u32 index = instance->index;
590 	u32 tmp;
591 
592 	if (tphy->pdata->avoid_rx_sen_degradation && index) {
593 		tmp = readl(com + U3D_U2PHYDCR0);
594 		tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
595 		writel(tmp, com + U3D_U2PHYDCR0);
596 
597 		tmp = readl(com + U3P_U2PHYDTM0);
598 		tmp &= ~P2C_FORCE_SUSPENDM;
599 		writel(tmp, com + U3P_U2PHYDTM0);
600 	}
601 }
602 
603 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
604 				     struct mtk_phy_instance *instance,
605 				     enum phy_mode mode)
606 {
607 	struct u2phy_banks *u2_banks = &instance->u2_banks;
608 	u32 tmp;
609 
610 	tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
611 	switch (mode) {
612 	case PHY_MODE_USB_DEVICE:
613 		tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
614 		break;
615 	case PHY_MODE_USB_HOST:
616 		tmp |= P2C_FORCE_IDDIG;
617 		tmp &= ~P2C_RG_IDDIG;
618 		break;
619 	case PHY_MODE_USB_OTG:
620 		tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
621 		break;
622 	default:
623 		return;
624 	}
625 	writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
626 }
627 
628 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
629 	struct mtk_phy_instance *instance)
630 {
631 	struct u3phy_banks *u3_banks = &instance->u3_banks;
632 	u32 tmp;
633 
634 	if (tphy->pdata->version != MTK_PHY_V1)
635 		return;
636 
637 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
638 	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
639 	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
640 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
641 
642 	/* ref clk drive */
643 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
644 	tmp &= ~P3A_RG_CLKDRV_AMP;
645 	tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
646 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
647 
648 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
649 	tmp &= ~P3A_RG_CLKDRV_OFF;
650 	tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
651 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
652 
653 	/* SSC delta -5000ppm */
654 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
655 	tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
656 	tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
657 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
658 
659 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
660 	tmp &= ~P3A_RG_PLL_DELTA_PE2H;
661 	tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
662 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
663 
664 	/* change pll BW 0.6M */
665 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
666 	tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
667 	tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
668 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
669 
670 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
671 	tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
672 	tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
673 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
674 
675 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
676 	tmp &= ~P3A_RG_PLL_IR_PE2H;
677 	tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
678 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
679 
680 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
681 	tmp &= ~P3A_RG_PLL_BP_PE2H;
682 	tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
683 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
684 
685 	/* Tx Detect Rx Timing: 10us -> 5us */
686 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
687 	tmp &= ~P3D_RG_RXDET_STB2_SET;
688 	tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
689 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
690 
691 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
692 	tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
693 	tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
694 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
695 
696 	/* wait for PCIe subsys register to active */
697 	usleep_range(2500, 3000);
698 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
699 }
700 
701 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
702 	struct mtk_phy_instance *instance)
703 {
704 	struct u3phy_banks *bank = &instance->u3_banks;
705 	u32 tmp;
706 
707 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
708 	tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
709 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
710 
711 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
712 	tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
713 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
714 }
715 
716 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
717 	struct mtk_phy_instance *instance)
718 
719 {
720 	struct u3phy_banks *bank = &instance->u3_banks;
721 	u32 tmp;
722 
723 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
724 	tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
725 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
726 
727 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
728 	tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
729 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
730 }
731 
732 static void sata_phy_instance_init(struct mtk_tphy *tphy,
733 	struct mtk_phy_instance *instance)
734 {
735 	struct u3phy_banks *u3_banks = &instance->u3_banks;
736 	void __iomem *phyd = u3_banks->phyd;
737 	u32 tmp;
738 
739 	/* charge current adjustment */
740 	tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
741 	tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
742 	tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
743 	writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
744 
745 	tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
746 	tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
747 	tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
748 	writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
749 
750 	tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
751 	tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
752 	tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
753 	writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
754 
755 	tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
756 	tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
757 	tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
758 	writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
759 
760 	tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
761 	tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
762 	tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
763 	writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4);
764 
765 	tmp = readl(phyd + PHYD_DESIGN_OPTION2);
766 	tmp &= ~RG_LOCK_CNT_SEL_MSK;
767 	tmp |= RG_LOCK_CNT_SEL_VAL(0x02);
768 	writel(tmp, phyd + PHYD_DESIGN_OPTION2);
769 
770 	tmp = readl(phyd + PHYD_DESIGN_OPTION9);
771 	tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK |
772 		 RG_T2_MAX_MSK | RG_TG_MAX_MSK);
773 	tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
774 	       RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e);
775 	writel(tmp, phyd + PHYD_DESIGN_OPTION9);
776 
777 	tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1);
778 	tmp &= ~RG_IDRV_0DB_GEN1_MSK;
779 	tmp |= RG_IDRV_0DB_GEN1_VAL(0x20);
780 	writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1);
781 
782 	tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
783 	tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK;
784 	tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03);
785 	writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
786 
787 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
788 }
789 
790 static void phy_v1_banks_init(struct mtk_tphy *tphy,
791 			      struct mtk_phy_instance *instance)
792 {
793 	struct u2phy_banks *u2_banks = &instance->u2_banks;
794 	struct u3phy_banks *u3_banks = &instance->u3_banks;
795 
796 	switch (instance->type) {
797 	case PHY_TYPE_USB2:
798 		u2_banks->misc = NULL;
799 		u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
800 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
801 		break;
802 	case PHY_TYPE_USB3:
803 	case PHY_TYPE_PCIE:
804 		u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
805 		u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
806 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
807 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
808 		break;
809 	case PHY_TYPE_SATA:
810 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
811 		break;
812 	default:
813 		dev_err(tphy->dev, "incompatible PHY type\n");
814 		return;
815 	}
816 }
817 
818 static void phy_v2_banks_init(struct mtk_tphy *tphy,
819 			      struct mtk_phy_instance *instance)
820 {
821 	struct u2phy_banks *u2_banks = &instance->u2_banks;
822 	struct u3phy_banks *u3_banks = &instance->u3_banks;
823 
824 	switch (instance->type) {
825 	case PHY_TYPE_USB2:
826 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
827 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
828 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
829 		break;
830 	case PHY_TYPE_USB3:
831 	case PHY_TYPE_PCIE:
832 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
833 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
834 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
835 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
836 		break;
837 	default:
838 		dev_err(tphy->dev, "incompatible PHY type\n");
839 		return;
840 	}
841 }
842 
843 static void phy_parse_property(struct mtk_tphy *tphy,
844 				struct mtk_phy_instance *instance)
845 {
846 	struct device *dev = &instance->phy->dev;
847 
848 	if (instance->type != PHY_TYPE_USB2)
849 		return;
850 
851 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
852 	device_property_read_u32(dev, "mediatek,eye-src",
853 				 &instance->eye_src);
854 	device_property_read_u32(dev, "mediatek,eye-vrt",
855 				 &instance->eye_vrt);
856 	device_property_read_u32(dev, "mediatek,eye-term",
857 				 &instance->eye_term);
858 	device_property_read_u32(dev, "mediatek,intr",
859 				 &instance->intr);
860 	device_property_read_u32(dev, "mediatek,discth",
861 				 &instance->discth);
862 	dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
863 		instance->bc12_en, instance->eye_src,
864 		instance->eye_vrt, instance->eye_term,
865 		instance->intr, instance->discth);
866 }
867 
868 static void u2_phy_props_set(struct mtk_tphy *tphy,
869 			     struct mtk_phy_instance *instance)
870 {
871 	struct u2phy_banks *u2_banks = &instance->u2_banks;
872 	void __iomem *com = u2_banks->com;
873 	u32 tmp;
874 
875 	if (instance->bc12_en) {
876 		tmp = readl(com + U3P_U2PHYBC12C);
877 		tmp |= P2C_RG_CHGDT_EN;	/* BC1.2 path Enable */
878 		writel(tmp, com + U3P_U2PHYBC12C);
879 	}
880 
881 	if (instance->eye_src) {
882 		tmp = readl(com + U3P_USBPHYACR5);
883 		tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
884 		tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
885 		writel(tmp, com + U3P_USBPHYACR5);
886 	}
887 
888 	if (instance->eye_vrt) {
889 		tmp = readl(com + U3P_USBPHYACR1);
890 		tmp &= ~PA1_RG_VRT_SEL;
891 		tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt);
892 		writel(tmp, com + U3P_USBPHYACR1);
893 	}
894 
895 	if (instance->eye_term) {
896 		tmp = readl(com + U3P_USBPHYACR1);
897 		tmp &= ~PA1_RG_TERM_SEL;
898 		tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
899 		writel(tmp, com + U3P_USBPHYACR1);
900 	}
901 
902 	if (instance->intr) {
903 		tmp = readl(com + U3P_USBPHYACR1);
904 		tmp &= ~PA1_RG_INTR_CAL;
905 		tmp |= PA1_RG_INTR_CAL_VAL(instance->intr);
906 		writel(tmp, com + U3P_USBPHYACR1);
907 	}
908 
909 	if (instance->discth) {
910 		tmp = readl(com + U3P_USBPHYACR6);
911 		tmp &= ~PA6_RG_U2_DISCTH;
912 		tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth);
913 		writel(tmp, com + U3P_USBPHYACR6);
914 	}
915 }
916 
917 static int mtk_phy_init(struct phy *phy)
918 {
919 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
920 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
921 	int ret;
922 
923 	ret = clk_prepare_enable(instance->ref_clk);
924 	if (ret) {
925 		dev_err(tphy->dev, "failed to enable ref_clk\n");
926 		return ret;
927 	}
928 
929 	ret = clk_prepare_enable(instance->da_ref_clk);
930 	if (ret) {
931 		dev_err(tphy->dev, "failed to enable da_ref\n");
932 		clk_disable_unprepare(instance->ref_clk);
933 		return ret;
934 	}
935 
936 	switch (instance->type) {
937 	case PHY_TYPE_USB2:
938 		u2_phy_instance_init(tphy, instance);
939 		u2_phy_props_set(tphy, instance);
940 		break;
941 	case PHY_TYPE_USB3:
942 		u3_phy_instance_init(tphy, instance);
943 		break;
944 	case PHY_TYPE_PCIE:
945 		pcie_phy_instance_init(tphy, instance);
946 		break;
947 	case PHY_TYPE_SATA:
948 		sata_phy_instance_init(tphy, instance);
949 		break;
950 	default:
951 		dev_err(tphy->dev, "incompatible PHY type\n");
952 		return -EINVAL;
953 	}
954 
955 	return 0;
956 }
957 
958 static int mtk_phy_power_on(struct phy *phy)
959 {
960 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
961 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
962 
963 	if (instance->type == PHY_TYPE_USB2) {
964 		u2_phy_instance_power_on(tphy, instance);
965 		hs_slew_rate_calibrate(tphy, instance);
966 	} else if (instance->type == PHY_TYPE_PCIE) {
967 		pcie_phy_instance_power_on(tphy, instance);
968 	}
969 
970 	return 0;
971 }
972 
973 static int mtk_phy_power_off(struct phy *phy)
974 {
975 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
976 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
977 
978 	if (instance->type == PHY_TYPE_USB2)
979 		u2_phy_instance_power_off(tphy, instance);
980 	else if (instance->type == PHY_TYPE_PCIE)
981 		pcie_phy_instance_power_off(tphy, instance);
982 
983 	return 0;
984 }
985 
986 static int mtk_phy_exit(struct phy *phy)
987 {
988 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
989 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
990 
991 	if (instance->type == PHY_TYPE_USB2)
992 		u2_phy_instance_exit(tphy, instance);
993 
994 	clk_disable_unprepare(instance->ref_clk);
995 	clk_disable_unprepare(instance->da_ref_clk);
996 	return 0;
997 }
998 
999 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1000 {
1001 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1002 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1003 
1004 	if (instance->type == PHY_TYPE_USB2)
1005 		u2_phy_instance_set_mode(tphy, instance, mode);
1006 
1007 	return 0;
1008 }
1009 
1010 static struct phy *mtk_phy_xlate(struct device *dev,
1011 					struct of_phandle_args *args)
1012 {
1013 	struct mtk_tphy *tphy = dev_get_drvdata(dev);
1014 	struct mtk_phy_instance *instance = NULL;
1015 	struct device_node *phy_np = args->np;
1016 	int index;
1017 
1018 	if (args->args_count != 1) {
1019 		dev_err(dev, "invalid number of cells in 'phy' property\n");
1020 		return ERR_PTR(-EINVAL);
1021 	}
1022 
1023 	for (index = 0; index < tphy->nphys; index++)
1024 		if (phy_np == tphy->phys[index]->phy->dev.of_node) {
1025 			instance = tphy->phys[index];
1026 			break;
1027 		}
1028 
1029 	if (!instance) {
1030 		dev_err(dev, "failed to find appropriate phy\n");
1031 		return ERR_PTR(-EINVAL);
1032 	}
1033 
1034 	instance->type = args->args[0];
1035 	if (!(instance->type == PHY_TYPE_USB2 ||
1036 	      instance->type == PHY_TYPE_USB3 ||
1037 	      instance->type == PHY_TYPE_PCIE ||
1038 	      instance->type == PHY_TYPE_SATA)) {
1039 		dev_err(dev, "unsupported device type: %d\n", instance->type);
1040 		return ERR_PTR(-EINVAL);
1041 	}
1042 
1043 	if (tphy->pdata->version == MTK_PHY_V1) {
1044 		phy_v1_banks_init(tphy, instance);
1045 	} else if (tphy->pdata->version == MTK_PHY_V2) {
1046 		phy_v2_banks_init(tphy, instance);
1047 	} else {
1048 		dev_err(dev, "phy version is not supported\n");
1049 		return ERR_PTR(-EINVAL);
1050 	}
1051 
1052 	phy_parse_property(tphy, instance);
1053 
1054 	return instance->phy;
1055 }
1056 
1057 static const struct phy_ops mtk_tphy_ops = {
1058 	.init		= mtk_phy_init,
1059 	.exit		= mtk_phy_exit,
1060 	.power_on	= mtk_phy_power_on,
1061 	.power_off	= mtk_phy_power_off,
1062 	.set_mode	= mtk_phy_set_mode,
1063 	.owner		= THIS_MODULE,
1064 };
1065 
1066 static const struct mtk_phy_pdata tphy_v1_pdata = {
1067 	.avoid_rx_sen_degradation = false,
1068 	.version = MTK_PHY_V1,
1069 };
1070 
1071 static const struct mtk_phy_pdata tphy_v2_pdata = {
1072 	.avoid_rx_sen_degradation = false,
1073 	.version = MTK_PHY_V2,
1074 };
1075 
1076 static const struct mtk_phy_pdata mt8173_pdata = {
1077 	.avoid_rx_sen_degradation = true,
1078 	.version = MTK_PHY_V1,
1079 };
1080 
1081 static const struct of_device_id mtk_tphy_id_table[] = {
1082 	{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1083 	{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1084 	{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1085 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1086 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1087 	{ },
1088 };
1089 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
1090 
1091 static int mtk_tphy_probe(struct platform_device *pdev)
1092 {
1093 	struct device *dev = &pdev->dev;
1094 	struct device_node *np = dev->of_node;
1095 	struct device_node *child_np;
1096 	struct phy_provider *provider;
1097 	struct resource *sif_res;
1098 	struct mtk_tphy *tphy;
1099 	struct resource res;
1100 	int port, retval;
1101 
1102 	tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
1103 	if (!tphy)
1104 		return -ENOMEM;
1105 
1106 	tphy->pdata = of_device_get_match_data(dev);
1107 	if (!tphy->pdata)
1108 		return -EINVAL;
1109 
1110 	tphy->nphys = of_get_child_count(np);
1111 	tphy->phys = devm_kcalloc(dev, tphy->nphys,
1112 				       sizeof(*tphy->phys), GFP_KERNEL);
1113 	if (!tphy->phys)
1114 		return -ENOMEM;
1115 
1116 	tphy->dev = dev;
1117 	platform_set_drvdata(pdev, tphy);
1118 
1119 	sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 	/* SATA phy of V1 needn't it if not shared with PCIe or USB */
1121 	if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
1122 		/* get banks shared by multiple phys */
1123 		tphy->sif_base = devm_ioremap_resource(dev, sif_res);
1124 		if (IS_ERR(tphy->sif_base)) {
1125 			dev_err(dev, "failed to remap sif regs\n");
1126 			return PTR_ERR(tphy->sif_base);
1127 		}
1128 	}
1129 
1130 	tphy->src_ref_clk = U3P_REF_CLK;
1131 	tphy->src_coef = U3P_SLEW_RATE_COEF;
1132 	/* update parameters of slew rate calibrate if exist */
1133 	device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1134 		&tphy->src_ref_clk);
1135 	device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
1136 
1137 	port = 0;
1138 	for_each_child_of_node(np, child_np) {
1139 		struct mtk_phy_instance *instance;
1140 		struct phy *phy;
1141 
1142 		instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1143 		if (!instance) {
1144 			retval = -ENOMEM;
1145 			goto put_child;
1146 		}
1147 
1148 		tphy->phys[port] = instance;
1149 
1150 		phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
1151 		if (IS_ERR(phy)) {
1152 			dev_err(dev, "failed to create phy\n");
1153 			retval = PTR_ERR(phy);
1154 			goto put_child;
1155 		}
1156 
1157 		retval = of_address_to_resource(child_np, 0, &res);
1158 		if (retval) {
1159 			dev_err(dev, "failed to get address resource(id-%d)\n",
1160 				port);
1161 			goto put_child;
1162 		}
1163 
1164 		instance->port_base = devm_ioremap_resource(&phy->dev, &res);
1165 		if (IS_ERR(instance->port_base)) {
1166 			dev_err(dev, "failed to remap phy regs\n");
1167 			retval = PTR_ERR(instance->port_base);
1168 			goto put_child;
1169 		}
1170 
1171 		instance->phy = phy;
1172 		instance->index = port;
1173 		phy_set_drvdata(phy, instance);
1174 		port++;
1175 
1176 		instance->ref_clk = devm_clk_get_optional(&phy->dev, "ref");
1177 		if (IS_ERR(instance->ref_clk)) {
1178 			dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
1179 			retval = PTR_ERR(instance->ref_clk);
1180 			goto put_child;
1181 		}
1182 
1183 		instance->da_ref_clk =
1184 			devm_clk_get_optional(&phy->dev, "da_ref");
1185 		if (IS_ERR(instance->da_ref_clk)) {
1186 			dev_err(dev, "failed to get da_ref_clk(id-%d)\n", port);
1187 			retval = PTR_ERR(instance->da_ref_clk);
1188 			goto put_child;
1189 		}
1190 	}
1191 
1192 	provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
1193 
1194 	return PTR_ERR_OR_ZERO(provider);
1195 put_child:
1196 	of_node_put(child_np);
1197 	return retval;
1198 }
1199 
1200 static struct platform_driver mtk_tphy_driver = {
1201 	.probe		= mtk_tphy_probe,
1202 	.driver		= {
1203 		.name	= "mtk-tphy",
1204 		.of_match_table = mtk_tphy_id_table,
1205 	},
1206 };
1207 
1208 module_platform_driver(mtk_tphy_driver);
1209 
1210 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1211 MODULE_DESCRIPTION("MediaTek T-PHY driver");
1212 MODULE_LICENSE("GPL v2");
1213