1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5  *
6  */
7 
8 #include <dt-bindings/phy/phy.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/iopoll.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/nvmem-consumer.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 
21 #include "phy-mtk-io.h"
22 
23 /* version V1 sub-banks offset base address */
24 /* banks shared by multiple phys */
25 #define SSUSB_SIFSLV_V1_SPLLC		0x000	/* shared by u3 phys */
26 #define SSUSB_SIFSLV_V1_U2FREQ		0x100	/* shared by u2 phys */
27 #define SSUSB_SIFSLV_V1_CHIP		0x300	/* shared by u3 phys */
28 /* u2 phy bank */
29 #define SSUSB_SIFSLV_V1_U2PHY_COM	0x000
30 /* u3/pcie/sata phy banks */
31 #define SSUSB_SIFSLV_V1_U3PHYD		0x000
32 #define SSUSB_SIFSLV_V1_U3PHYA		0x200
33 
34 /* version V2/V3 sub-banks offset base address */
35 /* V3: U2FREQ is not used anymore, but reserved */
36 /* u2 phy banks */
37 #define SSUSB_SIFSLV_V2_MISC		0x000
38 #define SSUSB_SIFSLV_V2_U2FREQ		0x100
39 #define SSUSB_SIFSLV_V2_U2PHY_COM	0x300
40 /* u3/pcie/sata phy banks */
41 #define SSUSB_SIFSLV_V2_SPLLC		0x000
42 #define SSUSB_SIFSLV_V2_CHIP		0x100
43 #define SSUSB_SIFSLV_V2_U3PHYD		0x200
44 #define SSUSB_SIFSLV_V2_U3PHYA		0x400
45 
46 #define U3P_MISC_REG1		0x04
47 #define MR1_EFUSE_AUTO_LOAD_DIS		BIT(6)
48 
49 #define U3P_USBPHYACR0		0x000
50 #define PA0_RG_U2PLL_FORCE_ON		BIT(15)
51 #define PA0_USB20_PLL_PREDIV		GENMASK(7, 6)
52 #define PA0_RG_USB20_INTR_EN		BIT(5)
53 
54 #define U3P_USBPHYACR1		0x004
55 #define PA1_RG_INTR_CAL		GENMASK(23, 19)
56 #define PA1_RG_VRT_SEL			GENMASK(14, 12)
57 #define PA1_RG_TERM_SEL		GENMASK(10, 8)
58 
59 #define U3P_USBPHYACR2		0x008
60 #define PA2_RG_U2PLL_BW			GENMASK(21, 19)
61 #define PA2_RG_SIF_U2PLL_FORCE_EN	BIT(18)
62 
63 #define U3P_USBPHYACR5		0x014
64 #define PA5_RG_U2_HSTX_SRCAL_EN	BIT(15)
65 #define PA5_RG_U2_HSTX_SRCTRL		GENMASK(14, 12)
66 #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
67 
68 #define U3P_USBPHYACR6		0x018
69 #define PA6_RG_U2_PRE_EMP		GENMASK(31, 30)
70 #define PA6_RG_U2_BC11_SW_EN		BIT(23)
71 #define PA6_RG_U2_OTG_VBUSCMP_EN	BIT(20)
72 #define PA6_RG_U2_DISCTH		GENMASK(7, 4)
73 #define PA6_RG_U2_SQTH		GENMASK(3, 0)
74 
75 #define U3P_U2PHYACR4		0x020
76 #define P2C_RG_USB20_GPIO_CTL		BIT(9)
77 #define P2C_USB20_GPIO_MODE		BIT(8)
78 #define P2C_U2_GPIO_CTR_MSK	(P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
79 
80 #define U3P_U2PHYA_RESV		0x030
81 #define P2R_RG_U2PLL_FBDIV_26M		0x1bb13b
82 #define P2R_RG_U2PLL_FBDIV_48M		0x3c0000
83 
84 #define U3P_U2PHYA_RESV1	0x044
85 #define P2R_RG_U2PLL_REFCLK_SEL	BIT(5)
86 #define P2R_RG_U2PLL_FRA_EN		BIT(3)
87 
88 #define U3D_U2PHYDCR0		0x060
89 #define P2C_RG_SIF_U2PLL_FORCE_ON	BIT(24)
90 
91 #define U3P_U2PHYDTM0		0x068
92 #define P2C_FORCE_UART_EN		BIT(26)
93 #define P2C_FORCE_DATAIN		BIT(23)
94 #define P2C_FORCE_DM_PULLDOWN		BIT(21)
95 #define P2C_FORCE_DP_PULLDOWN		BIT(20)
96 #define P2C_FORCE_XCVRSEL		BIT(19)
97 #define P2C_FORCE_SUSPENDM		BIT(18)
98 #define P2C_FORCE_TERMSEL		BIT(17)
99 #define P2C_RG_DATAIN			GENMASK(13, 10)
100 #define P2C_RG_DMPULLDOWN		BIT(7)
101 #define P2C_RG_DPPULLDOWN		BIT(6)
102 #define P2C_RG_XCVRSEL			GENMASK(5, 4)
103 #define P2C_RG_SUSPENDM			BIT(3)
104 #define P2C_RG_TERMSEL			BIT(2)
105 #define P2C_DTM0_PART_MASK \
106 		(P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
107 		P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
108 		P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
109 		P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
110 
111 #define U3P_U2PHYDTM1		0x06C
112 #define P2C_RG_UART_EN			BIT(16)
113 #define P2C_FORCE_IDDIG		BIT(9)
114 #define P2C_RG_VBUSVALID		BIT(5)
115 #define P2C_RG_SESSEND			BIT(4)
116 #define P2C_RG_AVALID			BIT(2)
117 #define P2C_RG_IDDIG			BIT(1)
118 
119 #define U3P_U2PHYBC12C		0x080
120 #define P2C_RG_CHGDT_EN		BIT(0)
121 
122 #define U3P_U3_CHIP_GPIO_CTLD		0x0c
123 #define P3C_REG_IP_SW_RST		BIT(31)
124 #define P3C_MCU_BUS_CK_GATE_EN		BIT(30)
125 #define P3C_FORCE_IP_SW_RST		BIT(29)
126 
127 #define U3P_U3_CHIP_GPIO_CTLE		0x10
128 #define P3C_RG_SWRST_U3_PHYD		BIT(25)
129 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN	BIT(24)
130 
131 #define U3P_U3_PHYA_REG0	0x000
132 #define P3A_RG_IEXT_INTR		GENMASK(15, 10)
133 #define P3A_RG_CLKDRV_OFF		GENMASK(3, 2)
134 
135 #define U3P_U3_PHYA_REG1	0x004
136 #define P3A_RG_CLKDRV_AMP		GENMASK(31, 29)
137 
138 #define U3P_U3_PHYA_REG6	0x018
139 #define P3A_RG_TX_EIDLE_CM		GENMASK(31, 28)
140 
141 #define U3P_U3_PHYA_REG9	0x024
142 #define P3A_RG_RX_DAC_MUX		GENMASK(5, 1)
143 
144 #define U3P_U3_PHYA_DA_REG0	0x100
145 #define P3A_RG_XTAL_EXT_PE2H		GENMASK(17, 16)
146 #define P3A_RG_XTAL_EXT_PE1H		GENMASK(13, 12)
147 #define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
148 
149 #define U3P_U3_PHYA_DA_REG4	0x108
150 #define P3A_RG_PLL_DIVEN_PE2H		GENMASK(21, 19)
151 #define P3A_RG_PLL_BC_PE2H		GENMASK(7, 6)
152 
153 #define U3P_U3_PHYA_DA_REG5	0x10c
154 #define P3A_RG_PLL_BR_PE2H		GENMASK(29, 28)
155 #define P3A_RG_PLL_IC_PE2H		GENMASK(15, 12)
156 
157 #define U3P_U3_PHYA_DA_REG6	0x110
158 #define P3A_RG_PLL_IR_PE2H		GENMASK(19, 16)
159 
160 #define U3P_U3_PHYA_DA_REG7	0x114
161 #define P3A_RG_PLL_BP_PE2H		GENMASK(19, 16)
162 
163 #define U3P_U3_PHYA_DA_REG20	0x13c
164 #define P3A_RG_PLL_DELTA1_PE2H		GENMASK(31, 16)
165 
166 #define U3P_U3_PHYA_DA_REG25	0x148
167 #define P3A_RG_PLL_DELTA_PE2H		GENMASK(15, 0)
168 
169 #define U3P_U3_PHYD_LFPS1		0x00c
170 #define P3D_RG_FWAKE_TH		GENMASK(21, 16)
171 
172 #define U3P_U3_PHYD_IMPCAL0		0x010
173 #define P3D_RG_FORCE_TX_IMPEL		BIT(31)
174 #define P3D_RG_TX_IMPEL			GENMASK(28, 24)
175 
176 #define U3P_U3_PHYD_IMPCAL1		0x014
177 #define P3D_RG_FORCE_RX_IMPEL		BIT(31)
178 #define P3D_RG_RX_IMPEL			GENMASK(28, 24)
179 
180 #define U3P_U3_PHYD_RSV			0x054
181 #define P3D_RG_EFUSE_AUTO_LOAD_DIS	BIT(12)
182 
183 #define U3P_U3_PHYD_CDR1		0x05c
184 #define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
185 #define P3D_RG_CDR_BIR_LTD0		GENMASK(12, 8)
186 
187 #define U3P_U3_PHYD_RXDET1		0x128
188 #define P3D_RG_RXDET_STB2_SET		GENMASK(17, 9)
189 
190 #define U3P_U3_PHYD_RXDET2		0x12c
191 #define P3D_RG_RXDET_STB2_SET_P3	GENMASK(8, 0)
192 
193 #define U3P_SPLLC_XTALCTL3		0x018
194 #define XC3_RG_U3_XTAL_RX_PWD		BIT(9)
195 #define XC3_RG_U3_FRC_XTAL_RX_PWD	BIT(8)
196 
197 #define U3P_U2FREQ_FMCR0	0x00
198 #define P2F_RG_MONCLK_SEL	GENMASK(27, 26)
199 #define P2F_RG_FREQDET_EN	BIT(24)
200 #define P2F_RG_CYCLECNT		GENMASK(23, 0)
201 
202 #define U3P_U2FREQ_VALUE	0x0c
203 
204 #define U3P_U2FREQ_FMMONR1	0x10
205 #define P2F_USB_FM_VALID	BIT(0)
206 #define P2F_RG_FRCK_EN		BIT(8)
207 
208 #define U3P_REF_CLK		26	/* MHZ */
209 #define U3P_SLEW_RATE_COEF	28
210 #define U3P_SR_COEF_DIVISOR	1000
211 #define U3P_FM_DET_CYCLE_CNT	1024
212 
213 /* SATA register setting */
214 #define PHYD_CTRL_SIGNAL_MODE4		0x1c
215 /* CDR Charge Pump P-path current adjustment */
216 #define RG_CDR_BICLTD1_GEN1_MSK		GENMASK(23, 20)
217 #define RG_CDR_BICLTD0_GEN1_MSK		GENMASK(11, 8)
218 
219 #define PHYD_DESIGN_OPTION2		0x24
220 /* Symbol lock count selection */
221 #define RG_LOCK_CNT_SEL_MSK		GENMASK(5, 4)
222 
223 #define PHYD_DESIGN_OPTION9	0x40
224 /* COMWAK GAP width window */
225 #define RG_TG_MAX_MSK		GENMASK(20, 16)
226 /* COMINIT GAP width window */
227 #define RG_T2_MAX_MSK		GENMASK(13, 8)
228 /* COMWAK GAP width window */
229 #define RG_TG_MIN_MSK		GENMASK(7, 5)
230 /* COMINIT GAP width window */
231 #define RG_T2_MIN_MSK		GENMASK(4, 0)
232 
233 #define ANA_RG_CTRL_SIGNAL1		0x4c
234 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
235 #define RG_IDRV_0DB_GEN1_MSK		GENMASK(13, 8)
236 
237 #define ANA_RG_CTRL_SIGNAL4		0x58
238 #define RG_CDR_BICLTR_GEN1_MSK		GENMASK(23, 20)
239 /* Loop filter R1 resistance adjustment for Gen1 speed */
240 #define RG_CDR_BR_GEN2_MSK		GENMASK(10, 8)
241 
242 #define ANA_RG_CTRL_SIGNAL6		0x60
243 /* I-path capacitance adjustment for Gen1 */
244 #define RG_CDR_BC_GEN1_MSK		GENMASK(28, 24)
245 #define RG_CDR_BIRLTR_GEN1_MSK		GENMASK(4, 0)
246 
247 #define ANA_EQ_EYE_CTRL_SIGNAL1		0x6c
248 /* RX Gen1 LEQ tuning step */
249 #define RG_EQ_DLEQ_LFI_GEN1_MSK		GENMASK(11, 8)
250 
251 #define ANA_EQ_EYE_CTRL_SIGNAL4		0xd8
252 #define RG_CDR_BIRLTD0_GEN1_MSK		GENMASK(20, 16)
253 
254 #define ANA_EQ_EYE_CTRL_SIGNAL5		0xdc
255 #define RG_CDR_BIRLTD0_GEN3_MSK		GENMASK(4, 0)
256 
257 /* PHY switch between pcie/usb3/sgmii/sata */
258 #define USB_PHY_SWITCH_CTRL	0x0
259 #define RG_PHY_SW_TYPE		GENMASK(3, 0)
260 #define RG_PHY_SW_PCIE		0x0
261 #define RG_PHY_SW_USB3		0x1
262 #define RG_PHY_SW_SGMII		0x2
263 #define RG_PHY_SW_SATA		0x3
264 
265 #define TPHY_CLKS_CNT	2
266 
267 enum mtk_phy_version {
268 	MTK_PHY_V1 = 1,
269 	MTK_PHY_V2,
270 	MTK_PHY_V3,
271 };
272 
273 struct mtk_phy_pdata {
274 	/* avoid RX sensitivity level degradation only for mt8173 */
275 	bool avoid_rx_sen_degradation;
276 	/*
277 	 * workaround only for mt8195, HW fix it for others of V3,
278 	 * u2phy should use integer mode instead of fractional mode of
279 	 * 48M PLL, fix it by switching PLL to 26M from default 48M
280 	 */
281 	bool sw_pll_48m_to_26m;
282 	/*
283 	 * Some SoCs (e.g. mt8195) drop a bit when use auto load efuse,
284 	 * support sw way, also support it for v2/v3 optionally.
285 	 */
286 	bool sw_efuse_supported;
287 	enum mtk_phy_version version;
288 };
289 
290 struct u2phy_banks {
291 	void __iomem *misc;
292 	void __iomem *fmreg;
293 	void __iomem *com;
294 };
295 
296 struct u3phy_banks {
297 	void __iomem *spllc;
298 	void __iomem *chip;
299 	void __iomem *phyd; /* include u3phyd_bank2 */
300 	void __iomem *phya; /* include u3phya_da */
301 };
302 
303 struct mtk_phy_instance {
304 	struct phy *phy;
305 	void __iomem *port_base;
306 	union {
307 		struct u2phy_banks u2_banks;
308 		struct u3phy_banks u3_banks;
309 	};
310 	struct clk_bulk_data clks[TPHY_CLKS_CNT];
311 	u32 index;
312 	u32 type;
313 	struct regmap *type_sw;
314 	u32 type_sw_reg;
315 	u32 type_sw_index;
316 	u32 efuse_sw_en;
317 	u32 efuse_intr;
318 	u32 efuse_tx_imp;
319 	u32 efuse_rx_imp;
320 	int eye_src;
321 	int eye_vrt;
322 	int eye_term;
323 	int intr;
324 	int discth;
325 	int pre_emphasis;
326 	bool bc12_en;
327 };
328 
329 struct mtk_tphy {
330 	struct device *dev;
331 	void __iomem *sif_base;	/* only shared sif */
332 	const struct mtk_phy_pdata *pdata;
333 	struct mtk_phy_instance **phys;
334 	int nphys;
335 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
336 	int src_coef; /* coefficient for slew rate calibrate */
337 };
338 
339 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
340 	struct mtk_phy_instance *instance)
341 {
342 	struct u2phy_banks *u2_banks = &instance->u2_banks;
343 	void __iomem *fmreg = u2_banks->fmreg;
344 	void __iomem *com = u2_banks->com;
345 	int calibration_val;
346 	int fm_out;
347 	u32 tmp;
348 
349 	/* HW V3 doesn't support slew rate cal anymore */
350 	if (tphy->pdata->version == MTK_PHY_V3)
351 		return;
352 
353 	/* use force value */
354 	if (instance->eye_src)
355 		return;
356 
357 	/* enable USB ring oscillator */
358 	mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
359 	udelay(1);
360 
361 	/*enable free run clock */
362 	mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
363 
364 	/* set cycle count as 1024, and select u2 channel */
365 	tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
366 	tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
367 	tmp |= FIELD_PREP(P2F_RG_CYCLECNT, U3P_FM_DET_CYCLE_CNT);
368 	if (tphy->pdata->version == MTK_PHY_V1)
369 		tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);
370 
371 	writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
372 
373 	/* enable frequency meter */
374 	mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
375 
376 	/* ignore return value */
377 	readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
378 			   (tmp & P2F_USB_FM_VALID), 10, 200);
379 
380 	fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
381 
382 	/* disable frequency meter */
383 	mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
384 
385 	/*disable free run clock */
386 	mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
387 
388 	if (fm_out) {
389 		/* ( 1024 / FM_OUT ) x reference clock frequency x coef */
390 		tmp = tphy->src_ref_clk * tphy->src_coef;
391 		tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
392 		calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
393 	} else {
394 		/* if FM detection fail, set default value */
395 		calibration_val = 4;
396 	}
397 	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
398 		instance->index, fm_out, calibration_val,
399 		tphy->src_ref_clk, tphy->src_coef);
400 
401 	/* set HS slew rate */
402 	mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
403 			     calibration_val);
404 
405 	/* disable USB ring oscillator */
406 	mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
407 }
408 
409 static void u3_phy_instance_init(struct mtk_tphy *tphy,
410 	struct mtk_phy_instance *instance)
411 {
412 	struct u3phy_banks *u3_banks = &instance->u3_banks;
413 	void __iomem *phya = u3_banks->phya;
414 	void __iomem *phyd = u3_banks->phyd;
415 
416 	/* gating PCIe Analog XTAL clock */
417 	mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
418 			 XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
419 
420 	/* gating XSQ */
421 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2);
422 
423 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4);
424 
425 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe);
426 
427 	mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,
428 			    P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
429 			    FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) |
430 			    FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3));
431 
432 	mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34);
433 
434 	mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10);
435 
436 	mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10);
437 
438 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
439 }
440 
441 static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
442 	struct mtk_phy_instance *instance)
443 {
444 	struct u2phy_banks *u2_banks = &instance->u2_banks;
445 	void __iomem *com = u2_banks->com;
446 
447 	if (!tphy->pdata->sw_pll_48m_to_26m)
448 		return;
449 
450 	mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0);
451 
452 	mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3);
453 
454 	writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
455 
456 	mtk_phy_set_bits(com + U3P_U2PHYA_RESV1,
457 			 P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL);
458 }
459 
460 static void u2_phy_instance_init(struct mtk_tphy *tphy,
461 	struct mtk_phy_instance *instance)
462 {
463 	struct u2phy_banks *u2_banks = &instance->u2_banks;
464 	void __iomem *com = u2_banks->com;
465 	u32 index = instance->index;
466 
467 	/* switch to USB function, and enable usb pll */
468 	mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
469 
470 	mtk_phy_clear_bits(com + U3P_U2PHYDTM0,
471 			   P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
472 
473 	mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
474 
475 	mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
476 
477 	/* disable switch 100uA current to SSUSB */
478 	mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
479 
480 	mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
481 
482 	if (tphy->pdata->avoid_rx_sen_degradation) {
483 		if (!index) {
484 			mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN);
485 
486 			mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
487 		} else {
488 			mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
489 
490 			mtk_phy_set_bits(com + U3P_U2PHYDTM0,
491 					 P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
492 		}
493 	}
494 
495 	/* DP/DM BC1.1 path Disable */
496 	mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
497 
498 	mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2);
499 
500 	/* Workaround only for mt8195, HW fix it for others (V3) */
501 	u2_phy_pll_26m_set(tphy, instance);
502 
503 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
504 }
505 
506 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
507 	struct mtk_phy_instance *instance)
508 {
509 	struct u2phy_banks *u2_banks = &instance->u2_banks;
510 	void __iomem *com = u2_banks->com;
511 	u32 index = instance->index;
512 
513 	/* OTG Enable */
514 	mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
515 
516 	mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
517 
518 	mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
519 
520 	if (tphy->pdata->avoid_rx_sen_degradation && index) {
521 		mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
522 
523 		mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
524 	}
525 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
526 }
527 
528 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
529 	struct mtk_phy_instance *instance)
530 {
531 	struct u2phy_banks *u2_banks = &instance->u2_banks;
532 	void __iomem *com = u2_banks->com;
533 	u32 index = instance->index;
534 
535 	/* OTG Disable */
536 	mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
537 
538 	mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
539 
540 	mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
541 
542 	if (tphy->pdata->avoid_rx_sen_degradation && index) {
543 		mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
544 
545 		mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
546 	}
547 
548 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
549 }
550 
551 static void u2_phy_instance_exit(struct mtk_tphy *tphy,
552 	struct mtk_phy_instance *instance)
553 {
554 	struct u2phy_banks *u2_banks = &instance->u2_banks;
555 	void __iomem *com = u2_banks->com;
556 	u32 index = instance->index;
557 
558 	if (tphy->pdata->avoid_rx_sen_degradation && index) {
559 		mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
560 
561 		mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
562 	}
563 }
564 
565 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
566 				     struct mtk_phy_instance *instance,
567 				     enum phy_mode mode)
568 {
569 	struct u2phy_banks *u2_banks = &instance->u2_banks;
570 	u32 tmp;
571 
572 	tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
573 	switch (mode) {
574 	case PHY_MODE_USB_DEVICE:
575 		tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
576 		break;
577 	case PHY_MODE_USB_HOST:
578 		tmp |= P2C_FORCE_IDDIG;
579 		tmp &= ~P2C_RG_IDDIG;
580 		break;
581 	case PHY_MODE_USB_OTG:
582 		tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
583 		break;
584 	default:
585 		return;
586 	}
587 	writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
588 }
589 
590 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
591 	struct mtk_phy_instance *instance)
592 {
593 	struct u3phy_banks *u3_banks = &instance->u3_banks;
594 	void __iomem *phya = u3_banks->phya;
595 
596 	if (tphy->pdata->version != MTK_PHY_V1)
597 		return;
598 
599 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
600 			    P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
601 			    FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
602 			    FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2));
603 
604 	/* ref clk drive */
605 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4);
606 
607 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1);
608 
609 	/* SSC delta -5000ppm */
610 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c);
611 
612 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36);
613 
614 	/* change pll BW 0.6M */
615 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5,
616 			    P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
617 			    FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) |
618 			    FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1));
619 
620 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4,
621 			    P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
622 			    FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3));
623 
624 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2);
625 
626 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa);
627 
628 	/* Tx Detect Rx Timing: 10us -> 5us */
629 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
630 			     P3D_RG_RXDET_STB2_SET, 0x10);
631 
632 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
633 			     P3D_RG_RXDET_STB2_SET_P3, 0x10);
634 
635 	/* wait for PCIe subsys register to active */
636 	usleep_range(2500, 3000);
637 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
638 }
639 
640 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
641 	struct mtk_phy_instance *instance)
642 {
643 	struct u3phy_banks *bank = &instance->u3_banks;
644 
645 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
646 			   P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
647 
648 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
649 			   P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
650 }
651 
652 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
653 	struct mtk_phy_instance *instance)
654 
655 {
656 	struct u3phy_banks *bank = &instance->u3_banks;
657 
658 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
659 			 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
660 
661 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
662 			 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
663 }
664 
665 static void sata_phy_instance_init(struct mtk_tphy *tphy,
666 	struct mtk_phy_instance *instance)
667 {
668 	struct u3phy_banks *u3_banks = &instance->u3_banks;
669 	void __iomem *phyd = u3_banks->phyd;
670 
671 	/* charge current adjustment */
672 	mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6,
673 			    RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
674 			    FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) |
675 			    FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a));
676 
677 	mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18);
678 
679 	mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06);
680 
681 	mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4,
682 			    RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
683 			    FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) |
684 			    FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07));
685 
686 	mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4,
687 			    RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
688 			    FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) |
689 			    FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02));
690 
691 	mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02);
692 
693 	mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
694 			    RG_T2_MIN_MSK | RG_TG_MIN_MSK,
695 			    FIELD_PREP(RG_T2_MIN_MSK, 0x12) |
696 			    FIELD_PREP(RG_TG_MIN_MSK, 0x04));
697 
698 	mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
699 			    RG_T2_MAX_MSK | RG_TG_MAX_MSK,
700 			    FIELD_PREP(RG_T2_MAX_MSK, 0x31) |
701 			    FIELD_PREP(RG_TG_MAX_MSK, 0x0e));
702 
703 	mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20);
704 
705 	mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03);
706 
707 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
708 }
709 
710 static void phy_v1_banks_init(struct mtk_tphy *tphy,
711 			      struct mtk_phy_instance *instance)
712 {
713 	struct u2phy_banks *u2_banks = &instance->u2_banks;
714 	struct u3phy_banks *u3_banks = &instance->u3_banks;
715 
716 	switch (instance->type) {
717 	case PHY_TYPE_USB2:
718 		u2_banks->misc = NULL;
719 		u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
720 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
721 		break;
722 	case PHY_TYPE_USB3:
723 	case PHY_TYPE_PCIE:
724 		u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
725 		u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
726 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
727 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
728 		break;
729 	case PHY_TYPE_SATA:
730 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
731 		break;
732 	default:
733 		dev_err(tphy->dev, "incompatible PHY type\n");
734 		return;
735 	}
736 }
737 
738 static void phy_v2_banks_init(struct mtk_tphy *tphy,
739 			      struct mtk_phy_instance *instance)
740 {
741 	struct u2phy_banks *u2_banks = &instance->u2_banks;
742 	struct u3phy_banks *u3_banks = &instance->u3_banks;
743 
744 	switch (instance->type) {
745 	case PHY_TYPE_USB2:
746 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
747 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
748 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
749 		break;
750 	case PHY_TYPE_USB3:
751 	case PHY_TYPE_PCIE:
752 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
753 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
754 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
755 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
756 		break;
757 	default:
758 		dev_err(tphy->dev, "incompatible PHY type\n");
759 		return;
760 	}
761 }
762 
763 static void phy_parse_property(struct mtk_tphy *tphy,
764 				struct mtk_phy_instance *instance)
765 {
766 	struct device *dev = &instance->phy->dev;
767 
768 	if (instance->type != PHY_TYPE_USB2)
769 		return;
770 
771 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
772 	device_property_read_u32(dev, "mediatek,eye-src",
773 				 &instance->eye_src);
774 	device_property_read_u32(dev, "mediatek,eye-vrt",
775 				 &instance->eye_vrt);
776 	device_property_read_u32(dev, "mediatek,eye-term",
777 				 &instance->eye_term);
778 	device_property_read_u32(dev, "mediatek,intr",
779 				 &instance->intr);
780 	device_property_read_u32(dev, "mediatek,discth",
781 				 &instance->discth);
782 	device_property_read_u32(dev, "mediatek,pre-emphasis",
783 				 &instance->pre_emphasis);
784 	dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
785 		instance->bc12_en, instance->eye_src,
786 		instance->eye_vrt, instance->eye_term,
787 		instance->intr, instance->discth);
788 	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);
789 }
790 
791 static void u2_phy_props_set(struct mtk_tphy *tphy,
792 			     struct mtk_phy_instance *instance)
793 {
794 	struct u2phy_banks *u2_banks = &instance->u2_banks;
795 	void __iomem *com = u2_banks->com;
796 
797 	if (instance->bc12_en) /* BC1.2 path Enable */
798 		mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN);
799 
800 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)
801 		mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
802 				     instance->eye_src);
803 
804 	if (instance->eye_vrt)
805 		mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
806 				     instance->eye_vrt);
807 
808 	if (instance->eye_term)
809 		mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
810 				     instance->eye_term);
811 
812 	if (instance->intr) {
813 		if (u2_banks->misc)
814 			mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,
815 					 MR1_EFUSE_AUTO_LOAD_DIS);
816 
817 		mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
818 				     instance->intr);
819 	}
820 
821 	if (instance->discth)
822 		mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
823 				     instance->discth);
824 
825 	if (instance->pre_emphasis)
826 		mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
827 				     instance->pre_emphasis);
828 }
829 
830 /* type switch for usb3/pcie/sgmii/sata */
831 static int phy_type_syscon_get(struct mtk_phy_instance *instance,
832 			       struct device_node *dn)
833 {
834 	struct of_phandle_args args;
835 	int ret;
836 
837 	/* type switch function is optional */
838 	if (!of_property_read_bool(dn, "mediatek,syscon-type"))
839 		return 0;
840 
841 	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
842 					       2, 0, &args);
843 	if (ret)
844 		return ret;
845 
846 	instance->type_sw_reg = args.args[0];
847 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
848 	instance->type_sw = syscon_node_to_regmap(args.np);
849 	of_node_put(args.np);
850 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
851 		 instance->type_sw_reg, instance->type_sw_index);
852 
853 	return PTR_ERR_OR_ZERO(instance->type_sw);
854 }
855 
856 static int phy_type_set(struct mtk_phy_instance *instance)
857 {
858 	int type;
859 	u32 offset;
860 
861 	if (!instance->type_sw)
862 		return 0;
863 
864 	switch (instance->type) {
865 	case PHY_TYPE_USB3:
866 		type = RG_PHY_SW_USB3;
867 		break;
868 	case PHY_TYPE_PCIE:
869 		type = RG_PHY_SW_PCIE;
870 		break;
871 	case PHY_TYPE_SGMII:
872 		type = RG_PHY_SW_SGMII;
873 		break;
874 	case PHY_TYPE_SATA:
875 		type = RG_PHY_SW_SATA;
876 		break;
877 	case PHY_TYPE_USB2:
878 	default:
879 		return 0;
880 	}
881 
882 	offset = instance->type_sw_index * BITS_PER_BYTE;
883 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
884 			   RG_PHY_SW_TYPE << offset, type << offset);
885 
886 	return 0;
887 }
888 
889 static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)
890 {
891 	struct device *dev = &instance->phy->dev;
892 	int ret = 0;
893 
894 	/* tphy v1 doesn't support sw efuse, skip it */
895 	if (!tphy->pdata->sw_efuse_supported) {
896 		instance->efuse_sw_en = 0;
897 		return 0;
898 	}
899 
900 	/* software efuse is optional */
901 	instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");
902 	if (!instance->efuse_sw_en)
903 		return 0;
904 
905 	switch (instance->type) {
906 	case PHY_TYPE_USB2:
907 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
908 		if (ret) {
909 			dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
910 			break;
911 		}
912 
913 		/* no efuse, ignore it */
914 		if (!instance->efuse_intr) {
915 			dev_warn(dev, "no u2 intr efuse, but dts enable it\n");
916 			instance->efuse_sw_en = 0;
917 			break;
918 		}
919 
920 		dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);
921 		break;
922 
923 	case PHY_TYPE_USB3:
924 	case PHY_TYPE_PCIE:
925 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
926 		if (ret) {
927 			dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
928 			break;
929 		}
930 
931 		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);
932 		if (ret) {
933 			dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret);
934 			break;
935 		}
936 
937 		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);
938 		if (ret) {
939 			dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret);
940 			break;
941 		}
942 
943 		/* no efuse, ignore it */
944 		if (!instance->efuse_intr &&
945 		    !instance->efuse_rx_imp &&
946 		    !instance->efuse_tx_imp) {
947 			dev_warn(dev, "no u3 intr efuse, but dts enable it\n");
948 			instance->efuse_sw_en = 0;
949 			break;
950 		}
951 
952 		dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
953 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
954 		break;
955 	default:
956 		dev_err(dev, "no sw efuse for type %d\n", instance->type);
957 		ret = -EINVAL;
958 	}
959 
960 	return ret;
961 }
962 
963 static void phy_efuse_set(struct mtk_phy_instance *instance)
964 {
965 	struct device *dev = &instance->phy->dev;
966 	struct u2phy_banks *u2_banks = &instance->u2_banks;
967 	struct u3phy_banks *u3_banks = &instance->u3_banks;
968 
969 	if (!instance->efuse_sw_en)
970 		return;
971 
972 	switch (instance->type) {
973 	case PHY_TYPE_USB2:
974 		mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);
975 
976 		mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
977 				     instance->efuse_intr);
978 		break;
979 	case PHY_TYPE_USB3:
980 	case PHY_TYPE_PCIE:
981 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);
982 
983 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,
984 				    instance->efuse_tx_imp);
985 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
986 
987 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,
988 				    instance->efuse_rx_imp);
989 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
990 
991 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,
992 				    instance->efuse_intr);
993 		break;
994 	default:
995 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);
996 		break;
997 	}
998 }
999 
1000 static int mtk_phy_init(struct phy *phy)
1001 {
1002 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1003 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1004 	int ret;
1005 
1006 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);
1007 	if (ret)
1008 		return ret;
1009 
1010 	phy_efuse_set(instance);
1011 
1012 	switch (instance->type) {
1013 	case PHY_TYPE_USB2:
1014 		u2_phy_instance_init(tphy, instance);
1015 		u2_phy_props_set(tphy, instance);
1016 		break;
1017 	case PHY_TYPE_USB3:
1018 		u3_phy_instance_init(tphy, instance);
1019 		break;
1020 	case PHY_TYPE_PCIE:
1021 		pcie_phy_instance_init(tphy, instance);
1022 		break;
1023 	case PHY_TYPE_SATA:
1024 		sata_phy_instance_init(tphy, instance);
1025 		break;
1026 	case PHY_TYPE_SGMII:
1027 		/* nothing to do, only used to set type */
1028 		break;
1029 	default:
1030 		dev_err(tphy->dev, "incompatible PHY type\n");
1031 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1032 		return -EINVAL;
1033 	}
1034 
1035 	return 0;
1036 }
1037 
1038 static int mtk_phy_power_on(struct phy *phy)
1039 {
1040 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1041 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1042 
1043 	if (instance->type == PHY_TYPE_USB2) {
1044 		u2_phy_instance_power_on(tphy, instance);
1045 		hs_slew_rate_calibrate(tphy, instance);
1046 	} else if (instance->type == PHY_TYPE_PCIE) {
1047 		pcie_phy_instance_power_on(tphy, instance);
1048 	}
1049 
1050 	return 0;
1051 }
1052 
1053 static int mtk_phy_power_off(struct phy *phy)
1054 {
1055 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1056 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1057 
1058 	if (instance->type == PHY_TYPE_USB2)
1059 		u2_phy_instance_power_off(tphy, instance);
1060 	else if (instance->type == PHY_TYPE_PCIE)
1061 		pcie_phy_instance_power_off(tphy, instance);
1062 
1063 	return 0;
1064 }
1065 
1066 static int mtk_phy_exit(struct phy *phy)
1067 {
1068 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1069 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1070 
1071 	if (instance->type == PHY_TYPE_USB2)
1072 		u2_phy_instance_exit(tphy, instance);
1073 
1074 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1075 	return 0;
1076 }
1077 
1078 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1079 {
1080 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1081 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1082 
1083 	if (instance->type == PHY_TYPE_USB2)
1084 		u2_phy_instance_set_mode(tphy, instance, mode);
1085 
1086 	return 0;
1087 }
1088 
1089 static struct phy *mtk_phy_xlate(struct device *dev,
1090 					struct of_phandle_args *args)
1091 {
1092 	struct mtk_tphy *tphy = dev_get_drvdata(dev);
1093 	struct mtk_phy_instance *instance = NULL;
1094 	struct device_node *phy_np = args->np;
1095 	int index;
1096 	int ret;
1097 
1098 	if (args->args_count != 1) {
1099 		dev_err(dev, "invalid number of cells in 'phy' property\n");
1100 		return ERR_PTR(-EINVAL);
1101 	}
1102 
1103 	for (index = 0; index < tphy->nphys; index++)
1104 		if (phy_np == tphy->phys[index]->phy->dev.of_node) {
1105 			instance = tphy->phys[index];
1106 			break;
1107 		}
1108 
1109 	if (!instance) {
1110 		dev_err(dev, "failed to find appropriate phy\n");
1111 		return ERR_PTR(-EINVAL);
1112 	}
1113 
1114 	instance->type = args->args[0];
1115 	if (!(instance->type == PHY_TYPE_USB2 ||
1116 	      instance->type == PHY_TYPE_USB3 ||
1117 	      instance->type == PHY_TYPE_PCIE ||
1118 	      instance->type == PHY_TYPE_SATA ||
1119 	      instance->type == PHY_TYPE_SGMII)) {
1120 		dev_err(dev, "unsupported device type: %d\n", instance->type);
1121 		return ERR_PTR(-EINVAL);
1122 	}
1123 
1124 	switch (tphy->pdata->version) {
1125 	case MTK_PHY_V1:
1126 		phy_v1_banks_init(tphy, instance);
1127 		break;
1128 	case MTK_PHY_V2:
1129 	case MTK_PHY_V3:
1130 		phy_v2_banks_init(tphy, instance);
1131 		break;
1132 	default:
1133 		dev_err(dev, "phy version is not supported\n");
1134 		return ERR_PTR(-EINVAL);
1135 	}
1136 
1137 	ret = phy_efuse_get(tphy, instance);
1138 	if (ret)
1139 		return ERR_PTR(ret);
1140 
1141 	phy_parse_property(tphy, instance);
1142 	phy_type_set(instance);
1143 
1144 	return instance->phy;
1145 }
1146 
1147 static const struct phy_ops mtk_tphy_ops = {
1148 	.init		= mtk_phy_init,
1149 	.exit		= mtk_phy_exit,
1150 	.power_on	= mtk_phy_power_on,
1151 	.power_off	= mtk_phy_power_off,
1152 	.set_mode	= mtk_phy_set_mode,
1153 	.owner		= THIS_MODULE,
1154 };
1155 
1156 static const struct mtk_phy_pdata tphy_v1_pdata = {
1157 	.avoid_rx_sen_degradation = false,
1158 	.version = MTK_PHY_V1,
1159 };
1160 
1161 static const struct mtk_phy_pdata tphy_v2_pdata = {
1162 	.avoid_rx_sen_degradation = false,
1163 	.sw_efuse_supported = true,
1164 	.version = MTK_PHY_V2,
1165 };
1166 
1167 static const struct mtk_phy_pdata tphy_v3_pdata = {
1168 	.sw_efuse_supported = true,
1169 	.version = MTK_PHY_V3,
1170 };
1171 
1172 static const struct mtk_phy_pdata mt8173_pdata = {
1173 	.avoid_rx_sen_degradation = true,
1174 	.version = MTK_PHY_V1,
1175 };
1176 
1177 static const struct mtk_phy_pdata mt8195_pdata = {
1178 	.sw_pll_48m_to_26m = true,
1179 	.sw_efuse_supported = true,
1180 	.version = MTK_PHY_V3,
1181 };
1182 
1183 static const struct of_device_id mtk_tphy_id_table[] = {
1184 	{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1185 	{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1186 	{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1187 	{ .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1188 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1189 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1190 	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1191 	{ },
1192 };
1193 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
1194 
1195 static int mtk_tphy_probe(struct platform_device *pdev)
1196 {
1197 	struct device *dev = &pdev->dev;
1198 	struct device_node *np = dev->of_node;
1199 	struct device_node *child_np;
1200 	struct phy_provider *provider;
1201 	struct resource *sif_res;
1202 	struct mtk_tphy *tphy;
1203 	struct resource res;
1204 	int port, retval;
1205 
1206 	tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
1207 	if (!tphy)
1208 		return -ENOMEM;
1209 
1210 	tphy->pdata = of_device_get_match_data(dev);
1211 	if (!tphy->pdata)
1212 		return -EINVAL;
1213 
1214 	tphy->nphys = of_get_child_count(np);
1215 	tphy->phys = devm_kcalloc(dev, tphy->nphys,
1216 				       sizeof(*tphy->phys), GFP_KERNEL);
1217 	if (!tphy->phys)
1218 		return -ENOMEM;
1219 
1220 	tphy->dev = dev;
1221 	platform_set_drvdata(pdev, tphy);
1222 
1223 	sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1224 	/* SATA phy of V1 needn't it if not shared with PCIe or USB */
1225 	if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
1226 		/* get banks shared by multiple phys */
1227 		tphy->sif_base = devm_ioremap_resource(dev, sif_res);
1228 		if (IS_ERR(tphy->sif_base)) {
1229 			dev_err(dev, "failed to remap sif regs\n");
1230 			return PTR_ERR(tphy->sif_base);
1231 		}
1232 	}
1233 
1234 	if (tphy->pdata->version < MTK_PHY_V3) {
1235 		tphy->src_ref_clk = U3P_REF_CLK;
1236 		tphy->src_coef = U3P_SLEW_RATE_COEF;
1237 		/* update parameters of slew rate calibrate if exist */
1238 		device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1239 					 &tphy->src_ref_clk);
1240 		device_property_read_u32(dev, "mediatek,src-coef",
1241 					 &tphy->src_coef);
1242 	}
1243 
1244 	port = 0;
1245 	for_each_child_of_node(np, child_np) {
1246 		struct mtk_phy_instance *instance;
1247 		struct clk_bulk_data *clks;
1248 		struct device *subdev;
1249 		struct phy *phy;
1250 
1251 		instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1252 		if (!instance) {
1253 			retval = -ENOMEM;
1254 			goto put_child;
1255 		}
1256 
1257 		tphy->phys[port] = instance;
1258 
1259 		phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
1260 		if (IS_ERR(phy)) {
1261 			dev_err(dev, "failed to create phy\n");
1262 			retval = PTR_ERR(phy);
1263 			goto put_child;
1264 		}
1265 
1266 		subdev = &phy->dev;
1267 		retval = of_address_to_resource(child_np, 0, &res);
1268 		if (retval) {
1269 			dev_err(subdev, "failed to get address resource(id-%d)\n",
1270 				port);
1271 			goto put_child;
1272 		}
1273 
1274 		instance->port_base = devm_ioremap_resource(subdev, &res);
1275 		if (IS_ERR(instance->port_base)) {
1276 			retval = PTR_ERR(instance->port_base);
1277 			goto put_child;
1278 		}
1279 
1280 		instance->phy = phy;
1281 		instance->index = port;
1282 		phy_set_drvdata(phy, instance);
1283 		port++;
1284 
1285 		clks = instance->clks;
1286 		clks[0].id = "ref";     /* digital (& analog) clock */
1287 		clks[1].id = "da_ref";  /* analog clock */
1288 		retval = devm_clk_bulk_get_optional(subdev, TPHY_CLKS_CNT, clks);
1289 		if (retval)
1290 			goto put_child;
1291 
1292 		retval = phy_type_syscon_get(instance, child_np);
1293 		if (retval)
1294 			goto put_child;
1295 	}
1296 
1297 	provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
1298 
1299 	return PTR_ERR_OR_ZERO(provider);
1300 put_child:
1301 	of_node_put(child_np);
1302 	return retval;
1303 }
1304 
1305 static struct platform_driver mtk_tphy_driver = {
1306 	.probe		= mtk_tphy_probe,
1307 	.driver		= {
1308 		.name	= "mtk-tphy",
1309 		.of_match_table = mtk_tphy_id_table,
1310 	},
1311 };
1312 
1313 module_platform_driver(mtk_tphy_driver);
1314 
1315 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1316 MODULE_DESCRIPTION("MediaTek T-PHY driver");
1317 MODULE_LICENSE("GPL v2");
1318