1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #include <dt-bindings/phy/phy.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/phy/phy.h> 25 #include <linux/platform_device.h> 26 27 /* version V1 sub-banks offset base address */ 28 /* banks shared by multiple phys */ 29 #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ 30 #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ 31 #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ 32 /* u2 phy bank */ 33 #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 34 /* u3/pcie/sata phy banks */ 35 #define SSUSB_SIFSLV_V1_U3PHYD 0x000 36 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 37 38 /* version V2 sub-banks offset base address */ 39 /* u2 phy banks */ 40 #define SSUSB_SIFSLV_V2_MISC 0x000 41 #define SSUSB_SIFSLV_V2_U2FREQ 0x100 42 #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 43 /* u3/pcie/sata phy banks */ 44 #define SSUSB_SIFSLV_V2_SPLLC 0x000 45 #define SSUSB_SIFSLV_V2_CHIP 0x100 46 #define SSUSB_SIFSLV_V2_U3PHYD 0x200 47 #define SSUSB_SIFSLV_V2_U3PHYA 0x400 48 49 #define U3P_USBPHYACR0 0x000 50 #define PA0_RG_U2PLL_FORCE_ON BIT(15) 51 #define PA0_RG_USB20_INTR_EN BIT(5) 52 53 #define U3P_USBPHYACR2 0x008 54 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) 55 56 #define U3P_USBPHYACR5 0x014 57 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) 58 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) 59 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) 60 #define PA5_RG_U2_HS_100U_U3_EN BIT(11) 61 62 #define U3P_USBPHYACR6 0x018 63 #define PA6_RG_U2_BC11_SW_EN BIT(23) 64 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) 65 #define PA6_RG_U2_SQTH GENMASK(3, 0) 66 #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) 67 68 #define U3P_U2PHYACR4 0x020 69 #define P2C_RG_USB20_GPIO_CTL BIT(9) 70 #define P2C_USB20_GPIO_MODE BIT(8) 71 #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) 72 73 #define U3D_U2PHYDCR0 0x060 74 #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) 75 76 #define U3P_U2PHYDTM0 0x068 77 #define P2C_FORCE_UART_EN BIT(26) 78 #define P2C_FORCE_DATAIN BIT(23) 79 #define P2C_FORCE_DM_PULLDOWN BIT(21) 80 #define P2C_FORCE_DP_PULLDOWN BIT(20) 81 #define P2C_FORCE_XCVRSEL BIT(19) 82 #define P2C_FORCE_SUSPENDM BIT(18) 83 #define P2C_FORCE_TERMSEL BIT(17) 84 #define P2C_RG_DATAIN GENMASK(13, 10) 85 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) 86 #define P2C_RG_DMPULLDOWN BIT(7) 87 #define P2C_RG_DPPULLDOWN BIT(6) 88 #define P2C_RG_XCVRSEL GENMASK(5, 4) 89 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) 90 #define P2C_RG_SUSPENDM BIT(3) 91 #define P2C_RG_TERMSEL BIT(2) 92 #define P2C_DTM0_PART_MASK \ 93 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ 94 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ 95 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ 96 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) 97 98 #define U3P_U2PHYDTM1 0x06C 99 #define P2C_RG_UART_EN BIT(16) 100 #define P2C_FORCE_IDDIG BIT(9) 101 #define P2C_RG_VBUSVALID BIT(5) 102 #define P2C_RG_SESSEND BIT(4) 103 #define P2C_RG_AVALID BIT(2) 104 #define P2C_RG_IDDIG BIT(1) 105 106 #define U3P_U3_CHIP_GPIO_CTLD 0x0c 107 #define P3C_REG_IP_SW_RST BIT(31) 108 #define P3C_MCU_BUS_CK_GATE_EN BIT(30) 109 #define P3C_FORCE_IP_SW_RST BIT(29) 110 111 #define U3P_U3_CHIP_GPIO_CTLE 0x10 112 #define P3C_RG_SWRST_U3_PHYD BIT(25) 113 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) 114 115 #define U3P_U3_PHYA_REG0 0x000 116 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) 117 #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) 118 119 #define U3P_U3_PHYA_REG1 0x004 120 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) 121 #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) 122 123 #define U3P_U3_PHYA_REG6 0x018 124 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) 125 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) 126 127 #define U3P_U3_PHYA_REG9 0x024 128 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) 129 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) 130 131 #define U3P_U3_PHYA_DA_REG0 0x100 132 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) 133 #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) 134 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) 135 #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) 136 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) 137 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) 138 139 #define U3P_U3_PHYA_DA_REG4 0x108 140 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) 141 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) 142 #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) 143 144 #define U3P_U3_PHYA_DA_REG5 0x10c 145 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) 146 #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) 147 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) 148 #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) 149 150 #define U3P_U3_PHYA_DA_REG6 0x110 151 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) 152 #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) 153 154 #define U3P_U3_PHYA_DA_REG7 0x114 155 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) 156 #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) 157 158 #define U3P_U3_PHYA_DA_REG20 0x13c 159 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) 160 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) 161 162 #define U3P_U3_PHYA_DA_REG25 0x148 163 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) 164 #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) 165 166 #define U3P_U3_PHYD_LFPS1 0x00c 167 #define P3D_RG_FWAKE_TH GENMASK(21, 16) 168 #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) 169 170 #define U3P_U3_PHYD_CDR1 0x05c 171 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 172 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) 173 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 174 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) 175 176 #define U3P_U3_PHYD_RXDET1 0x128 177 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 178 #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) 179 180 #define U3P_U3_PHYD_RXDET2 0x12c 181 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) 182 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) 183 184 #define U3P_SPLLC_XTALCTL3 0x018 185 #define XC3_RG_U3_XTAL_RX_PWD BIT(9) 186 #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) 187 188 #define U3P_U2FREQ_FMCR0 0x00 189 #define P2F_RG_MONCLK_SEL GENMASK(27, 26) 190 #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) 191 #define P2F_RG_FREQDET_EN BIT(24) 192 #define P2F_RG_CYCLECNT GENMASK(23, 0) 193 #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) 194 195 #define U3P_U2FREQ_VALUE 0x0c 196 197 #define U3P_U2FREQ_FMMONR1 0x10 198 #define P2F_USB_FM_VALID BIT(0) 199 #define P2F_RG_FRCK_EN BIT(8) 200 201 #define U3P_REF_CLK 26 /* MHZ */ 202 #define U3P_SLEW_RATE_COEF 28 203 #define U3P_SR_COEF_DIVISOR 1000 204 #define U3P_FM_DET_CYCLE_CNT 1024 205 206 /* SATA register setting */ 207 #define PHYD_CTRL_SIGNAL_MODE4 0x1c 208 /* CDR Charge Pump P-path current adjustment */ 209 #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) 210 #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) 211 #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) 212 #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) 213 214 #define PHYD_DESIGN_OPTION2 0x24 215 /* Symbol lock count selection */ 216 #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) 217 #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) 218 219 #define PHYD_DESIGN_OPTION9 0x40 220 /* COMWAK GAP width window */ 221 #define RG_TG_MAX_MSK GENMASK(20, 16) 222 #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) 223 /* COMINIT GAP width window */ 224 #define RG_T2_MAX_MSK GENMASK(13, 8) 225 #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) 226 /* COMWAK GAP width window */ 227 #define RG_TG_MIN_MSK GENMASK(7, 5) 228 #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) 229 /* COMINIT GAP width window */ 230 #define RG_T2_MIN_MSK GENMASK(4, 0) 231 #define RG_T2_MIN_VAL(x) (0x1f & (x)) 232 233 #define ANA_RG_CTRL_SIGNAL1 0x4c 234 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ 235 #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) 236 #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) 237 238 #define ANA_RG_CTRL_SIGNAL4 0x58 239 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) 240 #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) 241 /* Loop filter R1 resistance adjustment for Gen1 speed */ 242 #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) 243 #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) 244 245 #define ANA_RG_CTRL_SIGNAL6 0x60 246 /* I-path capacitance adjustment for Gen1 */ 247 #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) 248 #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) 249 #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) 250 #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) 251 252 #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c 253 /* RX Gen1 LEQ tuning step */ 254 #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) 255 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) 256 257 #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 258 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) 259 #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) 260 261 #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc 262 #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) 263 #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) 264 265 enum mtk_phy_version { 266 MTK_PHY_V1 = 1, 267 MTK_PHY_V2, 268 }; 269 270 struct mtk_phy_pdata { 271 /* avoid RX sensitivity level degradation only for mt8173 */ 272 bool avoid_rx_sen_degradation; 273 enum mtk_phy_version version; 274 }; 275 276 struct u2phy_banks { 277 void __iomem *misc; 278 void __iomem *fmreg; 279 void __iomem *com; 280 }; 281 282 struct u3phy_banks { 283 void __iomem *spllc; 284 void __iomem *chip; 285 void __iomem *phyd; /* include u3phyd_bank2 */ 286 void __iomem *phya; /* include u3phya_da */ 287 }; 288 289 struct mtk_phy_instance { 290 struct phy *phy; 291 void __iomem *port_base; 292 union { 293 struct u2phy_banks u2_banks; 294 struct u3phy_banks u3_banks; 295 }; 296 struct clk *ref_clk; /* reference clock of anolog phy */ 297 u32 index; 298 u8 type; 299 }; 300 301 struct mtk_tphy { 302 struct device *dev; 303 void __iomem *sif_base; /* only shared sif */ 304 /* deprecated, use @ref_clk instead in phy instance */ 305 struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ 306 const struct mtk_phy_pdata *pdata; 307 struct mtk_phy_instance **phys; 308 int nphys; 309 }; 310 311 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, 312 struct mtk_phy_instance *instance) 313 { 314 struct u2phy_banks *u2_banks = &instance->u2_banks; 315 void __iomem *fmreg = u2_banks->fmreg; 316 void __iomem *com = u2_banks->com; 317 int calibration_val; 318 int fm_out; 319 u32 tmp; 320 321 /* enable USB ring oscillator */ 322 tmp = readl(com + U3P_USBPHYACR5); 323 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; 324 writel(tmp, com + U3P_USBPHYACR5); 325 udelay(1); 326 327 /*enable free run clock */ 328 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 329 tmp |= P2F_RG_FRCK_EN; 330 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 331 332 /* set cycle count as 1024, and select u2 channel */ 333 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 334 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); 335 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); 336 if (tphy->pdata->version == MTK_PHY_V1) 337 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); 338 339 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 340 341 /* enable frequency meter */ 342 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 343 tmp |= P2F_RG_FREQDET_EN; 344 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 345 346 /* ignore return value */ 347 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, 348 (tmp & P2F_USB_FM_VALID), 10, 200); 349 350 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); 351 352 /* disable frequency meter */ 353 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 354 tmp &= ~P2F_RG_FREQDET_EN; 355 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 356 357 /*disable free run clock */ 358 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); 359 tmp &= ~P2F_RG_FRCK_EN; 360 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); 361 362 if (fm_out) { 363 /* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */ 364 tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF; 365 tmp /= fm_out; 366 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); 367 } else { 368 /* if FM detection fail, set default value */ 369 calibration_val = 4; 370 } 371 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n", 372 instance->index, fm_out, calibration_val); 373 374 /* set HS slew rate */ 375 tmp = readl(com + U3P_USBPHYACR5); 376 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; 377 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); 378 writel(tmp, com + U3P_USBPHYACR5); 379 380 /* disable USB ring oscillator */ 381 tmp = readl(com + U3P_USBPHYACR5); 382 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; 383 writel(tmp, com + U3P_USBPHYACR5); 384 } 385 386 static void u3_phy_instance_init(struct mtk_tphy *tphy, 387 struct mtk_phy_instance *instance) 388 { 389 struct u3phy_banks *u3_banks = &instance->u3_banks; 390 u32 tmp; 391 392 /* gating PCIe Analog XTAL clock */ 393 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); 394 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; 395 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); 396 397 /* gating XSQ */ 398 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 399 tmp &= ~P3A_RG_XTAL_EXT_EN_U3; 400 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); 401 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 402 403 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); 404 tmp &= ~P3A_RG_RX_DAC_MUX; 405 tmp |= P3A_RG_RX_DAC_MUX_VAL(4); 406 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); 407 408 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); 409 tmp &= ~P3A_RG_TX_EIDLE_CM; 410 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); 411 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); 412 413 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); 414 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); 415 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); 416 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); 417 418 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); 419 tmp &= ~P3D_RG_FWAKE_TH; 420 tmp |= P3D_RG_FWAKE_TH_VAL(0x34); 421 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); 422 423 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 424 tmp &= ~P3D_RG_RXDET_STB2_SET; 425 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 426 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 427 428 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 429 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 430 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 431 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 432 433 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 434 } 435 436 static void u2_phy_instance_init(struct mtk_tphy *tphy, 437 struct mtk_phy_instance *instance) 438 { 439 struct u2phy_banks *u2_banks = &instance->u2_banks; 440 void __iomem *com = u2_banks->com; 441 u32 index = instance->index; 442 u32 tmp; 443 444 /* switch to USB function, and enable usb pll */ 445 tmp = readl(com + U3P_U2PHYDTM0); 446 tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); 447 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); 448 writel(tmp, com + U3P_U2PHYDTM0); 449 450 tmp = readl(com + U3P_U2PHYDTM1); 451 tmp &= ~P2C_RG_UART_EN; 452 writel(tmp, com + U3P_U2PHYDTM1); 453 454 tmp = readl(com + U3P_USBPHYACR0); 455 tmp |= PA0_RG_USB20_INTR_EN; 456 writel(tmp, com + U3P_USBPHYACR0); 457 458 /* disable switch 100uA current to SSUSB */ 459 tmp = readl(com + U3P_USBPHYACR5); 460 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; 461 writel(tmp, com + U3P_USBPHYACR5); 462 463 if (!index) { 464 tmp = readl(com + U3P_U2PHYACR4); 465 tmp &= ~P2C_U2_GPIO_CTR_MSK; 466 writel(tmp, com + U3P_U2PHYACR4); 467 } 468 469 if (tphy->pdata->avoid_rx_sen_degradation) { 470 if (!index) { 471 tmp = readl(com + U3P_USBPHYACR2); 472 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; 473 writel(tmp, com + U3P_USBPHYACR2); 474 475 tmp = readl(com + U3D_U2PHYDCR0); 476 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 477 writel(tmp, com + U3D_U2PHYDCR0); 478 } else { 479 tmp = readl(com + U3D_U2PHYDCR0); 480 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 481 writel(tmp, com + U3D_U2PHYDCR0); 482 483 tmp = readl(com + U3P_U2PHYDTM0); 484 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 485 writel(tmp, com + U3P_U2PHYDTM0); 486 } 487 } 488 489 tmp = readl(com + U3P_USBPHYACR6); 490 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ 491 tmp &= ~PA6_RG_U2_SQTH; 492 tmp |= PA6_RG_U2_SQTH_VAL(2); 493 writel(tmp, com + U3P_USBPHYACR6); 494 495 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 496 } 497 498 static void u2_phy_instance_power_on(struct mtk_tphy *tphy, 499 struct mtk_phy_instance *instance) 500 { 501 struct u2phy_banks *u2_banks = &instance->u2_banks; 502 void __iomem *com = u2_banks->com; 503 u32 index = instance->index; 504 u32 tmp; 505 506 tmp = readl(com + U3P_U2PHYDTM0); 507 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); 508 writel(tmp, com + U3P_U2PHYDTM0); 509 510 /* OTG Enable */ 511 tmp = readl(com + U3P_USBPHYACR6); 512 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; 513 writel(tmp, com + U3P_USBPHYACR6); 514 515 tmp = readl(com + U3P_U2PHYDTM1); 516 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; 517 tmp &= ~P2C_RG_SESSEND; 518 writel(tmp, com + U3P_U2PHYDTM1); 519 520 if (tphy->pdata->avoid_rx_sen_degradation && index) { 521 tmp = readl(com + U3D_U2PHYDCR0); 522 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; 523 writel(tmp, com + U3D_U2PHYDCR0); 524 525 tmp = readl(com + U3P_U2PHYDTM0); 526 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; 527 writel(tmp, com + U3P_U2PHYDTM0); 528 } 529 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 530 } 531 532 static void u2_phy_instance_power_off(struct mtk_tphy *tphy, 533 struct mtk_phy_instance *instance) 534 { 535 struct u2phy_banks *u2_banks = &instance->u2_banks; 536 void __iomem *com = u2_banks->com; 537 u32 index = instance->index; 538 u32 tmp; 539 540 tmp = readl(com + U3P_U2PHYDTM0); 541 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); 542 writel(tmp, com + U3P_U2PHYDTM0); 543 544 /* OTG Disable */ 545 tmp = readl(com + U3P_USBPHYACR6); 546 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; 547 writel(tmp, com + U3P_USBPHYACR6); 548 549 tmp = readl(com + U3P_U2PHYDTM1); 550 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); 551 tmp |= P2C_RG_SESSEND; 552 writel(tmp, com + U3P_U2PHYDTM1); 553 554 if (tphy->pdata->avoid_rx_sen_degradation && index) { 555 tmp = readl(com + U3P_U2PHYDTM0); 556 tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 557 writel(tmp, com + U3P_U2PHYDTM0); 558 559 tmp = readl(com + U3D_U2PHYDCR0); 560 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 561 writel(tmp, com + U3D_U2PHYDCR0); 562 } 563 564 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 565 } 566 567 static void u2_phy_instance_exit(struct mtk_tphy *tphy, 568 struct mtk_phy_instance *instance) 569 { 570 struct u2phy_banks *u2_banks = &instance->u2_banks; 571 void __iomem *com = u2_banks->com; 572 u32 index = instance->index; 573 u32 tmp; 574 575 if (tphy->pdata->avoid_rx_sen_degradation && index) { 576 tmp = readl(com + U3D_U2PHYDCR0); 577 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; 578 writel(tmp, com + U3D_U2PHYDCR0); 579 580 tmp = readl(com + U3P_U2PHYDTM0); 581 tmp &= ~P2C_FORCE_SUSPENDM; 582 writel(tmp, com + U3P_U2PHYDTM0); 583 } 584 } 585 586 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, 587 struct mtk_phy_instance *instance, 588 enum phy_mode mode) 589 { 590 struct u2phy_banks *u2_banks = &instance->u2_banks; 591 u32 tmp; 592 593 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); 594 switch (mode) { 595 case PHY_MODE_USB_DEVICE: 596 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; 597 break; 598 case PHY_MODE_USB_HOST: 599 tmp |= P2C_FORCE_IDDIG; 600 tmp &= ~P2C_RG_IDDIG; 601 break; 602 case PHY_MODE_USB_OTG: 603 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); 604 break; 605 default: 606 return; 607 } 608 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); 609 } 610 611 static void pcie_phy_instance_init(struct mtk_tphy *tphy, 612 struct mtk_phy_instance *instance) 613 { 614 struct u3phy_banks *u3_banks = &instance->u3_banks; 615 u32 tmp; 616 617 if (tphy->pdata->version != MTK_PHY_V1) 618 return; 619 620 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); 621 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); 622 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); 623 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); 624 625 /* ref clk drive */ 626 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); 627 tmp &= ~P3A_RG_CLKDRV_AMP; 628 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); 629 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); 630 631 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); 632 tmp &= ~P3A_RG_CLKDRV_OFF; 633 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); 634 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); 635 636 /* SSC delta -5000ppm */ 637 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); 638 tmp &= ~P3A_RG_PLL_DELTA1_PE2H; 639 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); 640 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); 641 642 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); 643 tmp &= ~P3A_RG_PLL_DELTA_PE2H; 644 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); 645 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); 646 647 /* change pll BW 0.6M */ 648 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); 649 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); 650 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); 651 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); 652 653 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); 654 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); 655 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); 656 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); 657 658 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); 659 tmp &= ~P3A_RG_PLL_IR_PE2H; 660 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); 661 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); 662 663 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); 664 tmp &= ~P3A_RG_PLL_BP_PE2H; 665 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); 666 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); 667 668 /* Tx Detect Rx Timing: 10us -> 5us */ 669 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); 670 tmp &= ~P3D_RG_RXDET_STB2_SET; 671 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); 672 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); 673 674 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); 675 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; 676 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); 677 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); 678 679 /* wait for PCIe subsys register to active */ 680 usleep_range(2500, 3000); 681 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 682 } 683 684 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, 685 struct mtk_phy_instance *instance) 686 { 687 struct u3phy_banks *bank = &instance->u3_banks; 688 u32 tmp; 689 690 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 691 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN | 692 P3C_REG_IP_SW_RST); 693 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 694 695 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 696 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 697 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 698 } 699 700 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, 701 struct mtk_phy_instance *instance) 702 703 { 704 struct u3phy_banks *bank = &instance->u3_banks; 705 u32 tmp; 706 707 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); 708 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; 709 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); 710 711 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); 712 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; 713 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); 714 } 715 716 static void sata_phy_instance_init(struct mtk_tphy *tphy, 717 struct mtk_phy_instance *instance) 718 { 719 struct u3phy_banks *u3_banks = &instance->u3_banks; 720 void __iomem *phyd = u3_banks->phyd; 721 u32 tmp; 722 723 /* charge current adjustment */ 724 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); 725 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); 726 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); 727 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); 728 729 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 730 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; 731 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); 732 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); 733 734 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 735 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; 736 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); 737 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); 738 739 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); 740 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); 741 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); 742 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); 743 744 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); 745 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); 746 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); 747 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); 748 749 tmp = readl(phyd + PHYD_DESIGN_OPTION2); 750 tmp &= ~RG_LOCK_CNT_SEL_MSK; 751 tmp |= RG_LOCK_CNT_SEL_VAL(0x02); 752 writel(tmp, phyd + PHYD_DESIGN_OPTION2); 753 754 tmp = readl(phyd + PHYD_DESIGN_OPTION9); 755 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | 756 RG_T2_MAX_MSK | RG_TG_MAX_MSK); 757 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | 758 RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e); 759 writel(tmp, phyd + PHYD_DESIGN_OPTION9); 760 761 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); 762 tmp &= ~RG_IDRV_0DB_GEN1_MSK; 763 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); 764 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); 765 766 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 767 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; 768 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); 769 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); 770 771 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 772 } 773 774 static void phy_v1_banks_init(struct mtk_tphy *tphy, 775 struct mtk_phy_instance *instance) 776 { 777 struct u2phy_banks *u2_banks = &instance->u2_banks; 778 struct u3phy_banks *u3_banks = &instance->u3_banks; 779 780 switch (instance->type) { 781 case PHY_TYPE_USB2: 782 u2_banks->misc = NULL; 783 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; 784 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; 785 break; 786 case PHY_TYPE_USB3: 787 case PHY_TYPE_PCIE: 788 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; 789 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; 790 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 791 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; 792 break; 793 case PHY_TYPE_SATA: 794 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 795 break; 796 default: 797 dev_err(tphy->dev, "incompatible PHY type\n"); 798 return; 799 } 800 } 801 802 static void phy_v2_banks_init(struct mtk_tphy *tphy, 803 struct mtk_phy_instance *instance) 804 { 805 struct u2phy_banks *u2_banks = &instance->u2_banks; 806 struct u3phy_banks *u3_banks = &instance->u3_banks; 807 808 switch (instance->type) { 809 case PHY_TYPE_USB2: 810 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; 811 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; 812 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; 813 break; 814 case PHY_TYPE_USB3: 815 case PHY_TYPE_PCIE: 816 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; 817 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; 818 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; 819 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; 820 break; 821 default: 822 dev_err(tphy->dev, "incompatible PHY type\n"); 823 return; 824 } 825 } 826 827 static int mtk_phy_init(struct phy *phy) 828 { 829 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 830 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 831 int ret; 832 833 ret = clk_prepare_enable(tphy->u3phya_ref); 834 if (ret) { 835 dev_err(tphy->dev, "failed to enable u3phya_ref\n"); 836 return ret; 837 } 838 839 ret = clk_prepare_enable(instance->ref_clk); 840 if (ret) { 841 dev_err(tphy->dev, "failed to enable ref_clk\n"); 842 return ret; 843 } 844 845 switch (instance->type) { 846 case PHY_TYPE_USB2: 847 u2_phy_instance_init(tphy, instance); 848 break; 849 case PHY_TYPE_USB3: 850 u3_phy_instance_init(tphy, instance); 851 break; 852 case PHY_TYPE_PCIE: 853 pcie_phy_instance_init(tphy, instance); 854 break; 855 case PHY_TYPE_SATA: 856 sata_phy_instance_init(tphy, instance); 857 break; 858 default: 859 dev_err(tphy->dev, "incompatible PHY type\n"); 860 return -EINVAL; 861 } 862 863 return 0; 864 } 865 866 static int mtk_phy_power_on(struct phy *phy) 867 { 868 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 869 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 870 871 if (instance->type == PHY_TYPE_USB2) { 872 u2_phy_instance_power_on(tphy, instance); 873 hs_slew_rate_calibrate(tphy, instance); 874 } else if (instance->type == PHY_TYPE_PCIE) { 875 pcie_phy_instance_power_on(tphy, instance); 876 } 877 878 return 0; 879 } 880 881 static int mtk_phy_power_off(struct phy *phy) 882 { 883 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 884 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 885 886 if (instance->type == PHY_TYPE_USB2) 887 u2_phy_instance_power_off(tphy, instance); 888 else if (instance->type == PHY_TYPE_PCIE) 889 pcie_phy_instance_power_off(tphy, instance); 890 891 return 0; 892 } 893 894 static int mtk_phy_exit(struct phy *phy) 895 { 896 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 897 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 898 899 if (instance->type == PHY_TYPE_USB2) 900 u2_phy_instance_exit(tphy, instance); 901 902 clk_disable_unprepare(instance->ref_clk); 903 clk_disable_unprepare(tphy->u3phya_ref); 904 return 0; 905 } 906 907 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode) 908 { 909 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 910 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 911 912 if (instance->type == PHY_TYPE_USB2) 913 u2_phy_instance_set_mode(tphy, instance, mode); 914 915 return 0; 916 } 917 918 static struct phy *mtk_phy_xlate(struct device *dev, 919 struct of_phandle_args *args) 920 { 921 struct mtk_tphy *tphy = dev_get_drvdata(dev); 922 struct mtk_phy_instance *instance = NULL; 923 struct device_node *phy_np = args->np; 924 int index; 925 926 if (args->args_count != 1) { 927 dev_err(dev, "invalid number of cells in 'phy' property\n"); 928 return ERR_PTR(-EINVAL); 929 } 930 931 for (index = 0; index < tphy->nphys; index++) 932 if (phy_np == tphy->phys[index]->phy->dev.of_node) { 933 instance = tphy->phys[index]; 934 break; 935 } 936 937 if (!instance) { 938 dev_err(dev, "failed to find appropriate phy\n"); 939 return ERR_PTR(-EINVAL); 940 } 941 942 instance->type = args->args[0]; 943 if (!(instance->type == PHY_TYPE_USB2 || 944 instance->type == PHY_TYPE_USB3 || 945 instance->type == PHY_TYPE_PCIE || 946 instance->type == PHY_TYPE_SATA)) { 947 dev_err(dev, "unsupported device type: %d\n", instance->type); 948 return ERR_PTR(-EINVAL); 949 } 950 951 if (tphy->pdata->version == MTK_PHY_V1) { 952 phy_v1_banks_init(tphy, instance); 953 } else if (tphy->pdata->version == MTK_PHY_V2) { 954 phy_v2_banks_init(tphy, instance); 955 } else { 956 dev_err(dev, "phy version is not supported\n"); 957 return ERR_PTR(-EINVAL); 958 } 959 960 return instance->phy; 961 } 962 963 static const struct phy_ops mtk_tphy_ops = { 964 .init = mtk_phy_init, 965 .exit = mtk_phy_exit, 966 .power_on = mtk_phy_power_on, 967 .power_off = mtk_phy_power_off, 968 .set_mode = mtk_phy_set_mode, 969 .owner = THIS_MODULE, 970 }; 971 972 static const struct mtk_phy_pdata tphy_v1_pdata = { 973 .avoid_rx_sen_degradation = false, 974 .version = MTK_PHY_V1, 975 }; 976 977 static const struct mtk_phy_pdata tphy_v2_pdata = { 978 .avoid_rx_sen_degradation = false, 979 .version = MTK_PHY_V2, 980 }; 981 982 static const struct mtk_phy_pdata mt8173_pdata = { 983 .avoid_rx_sen_degradation = true, 984 .version = MTK_PHY_V1, 985 }; 986 987 static const struct of_device_id mtk_tphy_id_table[] = { 988 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, 989 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, 990 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, 991 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, 992 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, 993 { }, 994 }; 995 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); 996 997 static int mtk_tphy_probe(struct platform_device *pdev) 998 { 999 struct device *dev = &pdev->dev; 1000 struct device_node *np = dev->of_node; 1001 struct device_node *child_np; 1002 struct phy_provider *provider; 1003 struct resource *sif_res; 1004 struct mtk_tphy *tphy; 1005 struct resource res; 1006 int port, retval; 1007 1008 tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); 1009 if (!tphy) 1010 return -ENOMEM; 1011 1012 tphy->pdata = of_device_get_match_data(dev); 1013 if (!tphy->pdata) 1014 return -EINVAL; 1015 1016 tphy->nphys = of_get_child_count(np); 1017 tphy->phys = devm_kcalloc(dev, tphy->nphys, 1018 sizeof(*tphy->phys), GFP_KERNEL); 1019 if (!tphy->phys) 1020 return -ENOMEM; 1021 1022 tphy->dev = dev; 1023 platform_set_drvdata(pdev, tphy); 1024 1025 sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1026 /* SATA phy of V1 needn't it if not shared with PCIe or USB */ 1027 if (sif_res && tphy->pdata->version == MTK_PHY_V1) { 1028 /* get banks shared by multiple phys */ 1029 tphy->sif_base = devm_ioremap_resource(dev, sif_res); 1030 if (IS_ERR(tphy->sif_base)) { 1031 dev_err(dev, "failed to remap sif regs\n"); 1032 return PTR_ERR(tphy->sif_base); 1033 } 1034 } 1035 1036 /* it's deprecated, make it optional for backward compatibility */ 1037 tphy->u3phya_ref = devm_clk_get(dev, "u3phya_ref"); 1038 if (IS_ERR(tphy->u3phya_ref)) { 1039 if (PTR_ERR(tphy->u3phya_ref) == -EPROBE_DEFER) 1040 return -EPROBE_DEFER; 1041 1042 tphy->u3phya_ref = NULL; 1043 } 1044 1045 port = 0; 1046 for_each_child_of_node(np, child_np) { 1047 struct mtk_phy_instance *instance; 1048 struct phy *phy; 1049 1050 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); 1051 if (!instance) { 1052 retval = -ENOMEM; 1053 goto put_child; 1054 } 1055 1056 tphy->phys[port] = instance; 1057 1058 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops); 1059 if (IS_ERR(phy)) { 1060 dev_err(dev, "failed to create phy\n"); 1061 retval = PTR_ERR(phy); 1062 goto put_child; 1063 } 1064 1065 retval = of_address_to_resource(child_np, 0, &res); 1066 if (retval) { 1067 dev_err(dev, "failed to get address resource(id-%d)\n", 1068 port); 1069 goto put_child; 1070 } 1071 1072 instance->port_base = devm_ioremap_resource(&phy->dev, &res); 1073 if (IS_ERR(instance->port_base)) { 1074 dev_err(dev, "failed to remap phy regs\n"); 1075 retval = PTR_ERR(instance->port_base); 1076 goto put_child; 1077 } 1078 1079 instance->phy = phy; 1080 instance->index = port; 1081 phy_set_drvdata(phy, instance); 1082 port++; 1083 1084 /* if deprecated clock is provided, ignore instance's one */ 1085 if (tphy->u3phya_ref) 1086 continue; 1087 1088 instance->ref_clk = devm_clk_get(&phy->dev, "ref"); 1089 if (IS_ERR(instance->ref_clk)) { 1090 dev_err(dev, "failed to get ref_clk(id-%d)\n", port); 1091 retval = PTR_ERR(instance->ref_clk); 1092 goto put_child; 1093 } 1094 } 1095 1096 provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); 1097 1098 return PTR_ERR_OR_ZERO(provider); 1099 put_child: 1100 of_node_put(child_np); 1101 return retval; 1102 } 1103 1104 static struct platform_driver mtk_tphy_driver = { 1105 .probe = mtk_tphy_probe, 1106 .driver = { 1107 .name = "mtk-tphy", 1108 .of_match_table = mtk_tphy_id_table, 1109 }, 1110 }; 1111 1112 module_platform_driver(mtk_tphy_driver); 1113 1114 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 1115 MODULE_DESCRIPTION("MediaTek T-PHY driver"); 1116 MODULE_LICENSE("GPL v2"); 1117