1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: jitao.shi <jitao.shi@mediatek.com> 5 */ 6 7 #include "phy-mtk-mipi-dsi.h" 8 9 #define MIPITX_DSI_CON 0x00 10 #define RG_DSI_LDOCORE_EN BIT(0) 11 #define RG_DSI_CKG_LDOOUT_EN BIT(1) 12 #define RG_DSI_BCLK_SEL GENMASK(3, 2) 13 #define RG_DSI_LD_IDX_SEL GENMASK(6, 4) 14 #define RG_DSI_PHYCLK_SEL GENMASK(9, 8) 15 #define RG_DSI_DSICLK_FREQ_SEL BIT(10) 16 #define RG_DSI_LPTX_CLMP_EN BIT(11) 17 18 #define MIPITX_DSI_CLOCK_LANE 0x04 19 #define MIPITX_DSI_DATA_LANE0 0x08 20 #define MIPITX_DSI_DATA_LANE1 0x0c 21 #define MIPITX_DSI_DATA_LANE2 0x10 22 #define MIPITX_DSI_DATA_LANE3 0x14 23 #define RG_DSI_LNTx_LDOOUT_EN BIT(0) 24 #define RG_DSI_LNTx_CKLANE_EN BIT(1) 25 #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2) 26 #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3) 27 #define RG_DSI_LNTx_LPTX_IMINUS BIT(4) 28 #define RG_DSI_LNTx_LPCD_IPLUS BIT(5) 29 #define RG_DSI_LNTx_LPCD_IMINUS BIT(6) 30 #define RG_DSI_LNTx_RT_CODE GENMASK(11, 8) 31 32 #define MIPITX_DSI_TOP_CON 0x40 33 #define RG_DSI_LNT_INTR_EN BIT(0) 34 #define RG_DSI_LNT_HS_BIAS_EN BIT(1) 35 #define RG_DSI_LNT_IMP_CAL_EN BIT(2) 36 #define RG_DSI_LNT_TESTMODE_EN BIT(3) 37 #define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4) 38 #define RG_DSI_LNT_AIO_SEL GENMASK(10, 8) 39 #define RG_DSI_PAD_TIE_LOW_EN BIT(11) 40 #define RG_DSI_DEBUG_INPUT_EN BIT(12) 41 #define RG_DSI_PRESERVE GENMASK(15, 13) 42 43 #define MIPITX_DSI_BG_CON 0x44 44 #define RG_DSI_BG_CORE_EN BIT(0) 45 #define RG_DSI_BG_CKEN BIT(1) 46 #define RG_DSI_BG_DIV GENMASK(3, 2) 47 #define RG_DSI_BG_FAST_CHARGE BIT(4) 48 49 #define RG_DSI_V12_SEL GENMASK(7, 5) 50 #define RG_DSI_V10_SEL GENMASK(10, 8) 51 #define RG_DSI_V072_SEL GENMASK(13, 11) 52 #define RG_DSI_V04_SEL GENMASK(16, 14) 53 #define RG_DSI_V032_SEL GENMASK(19, 17) 54 #define RG_DSI_V02_SEL GENMASK(22, 20) 55 #define RG_DSI_VOUT_MSK \ 56 (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \ 57 RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL) 58 #define RG_DSI_BG_R1_TRIM GENMASK(27, 24) 59 #define RG_DSI_BG_R2_TRIM GENMASK(31, 28) 60 61 #define MIPITX_DSI_PLL_CON0 0x50 62 #define RG_DSI_MPPLL_PLL_EN BIT(0) 63 #define RG_DSI_MPPLL_PREDIV GENMASK(2, 1) 64 #define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3) 65 #define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5) 66 #define RG_DSI_MPPLL_POSDIV GENMASK(9, 7) 67 #define RG_DSI_MPPLL_DIV_MSK \ 68 (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \ 69 RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV) 70 #define RG_DSI_MPPLL_MONVC_EN BIT(10) 71 #define RG_DSI_MPPLL_MONREF_EN BIT(11) 72 #define RG_DSI_MPPLL_VOD_EN BIT(12) 73 74 #define MIPITX_DSI_PLL_CON1 0x54 75 #define RG_DSI_MPPLL_SDM_FRA_EN BIT(0) 76 #define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) 77 #define RG_DSI_MPPLL_SDM_SSC_EN BIT(2) 78 #define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16) 79 80 #define MIPITX_DSI_PLL_CON2 0x58 81 82 #define MIPITX_DSI_PLL_TOP 0x64 83 #define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8) 84 85 #define MIPITX_DSI_PLL_PWR 0x68 86 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) 87 #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1) 88 #define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8) 89 90 #define MIPITX_DSI_SW_CTRL 0x80 91 #define SW_CTRL_EN BIT(0) 92 93 #define MIPITX_DSI_SW_CTRL_CON0 0x84 94 #define SW_LNTC_LPTX_PRE_OE BIT(0) 95 #define SW_LNTC_LPTX_OE BIT(1) 96 #define SW_LNTC_LPTX_P BIT(2) 97 #define SW_LNTC_LPTX_N BIT(3) 98 #define SW_LNTC_HSTX_PRE_OE BIT(4) 99 #define SW_LNTC_HSTX_OE BIT(5) 100 #define SW_LNTC_HSTX_ZEROCLK BIT(6) 101 #define SW_LNT0_LPTX_PRE_OE BIT(7) 102 #define SW_LNT0_LPTX_OE BIT(8) 103 #define SW_LNT0_LPTX_P BIT(9) 104 #define SW_LNT0_LPTX_N BIT(10) 105 #define SW_LNT0_HSTX_PRE_OE BIT(11) 106 #define SW_LNT0_HSTX_OE BIT(12) 107 #define SW_LNT0_LPRX_EN BIT(13) 108 #define SW_LNT1_LPTX_PRE_OE BIT(14) 109 #define SW_LNT1_LPTX_OE BIT(15) 110 #define SW_LNT1_LPTX_P BIT(16) 111 #define SW_LNT1_LPTX_N BIT(17) 112 #define SW_LNT1_HSTX_PRE_OE BIT(18) 113 #define SW_LNT1_HSTX_OE BIT(19) 114 #define SW_LNT2_LPTX_PRE_OE BIT(20) 115 #define SW_LNT2_LPTX_OE BIT(21) 116 #define SW_LNT2_LPTX_P BIT(22) 117 #define SW_LNT2_LPTX_N BIT(23) 118 #define SW_LNT2_HSTX_PRE_OE BIT(24) 119 #define SW_LNT2_HSTX_OE BIT(25) 120 121 static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) 122 { 123 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); 124 u8 txdiv, txdiv0, txdiv1; 125 u64 pcw; 126 127 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); 128 129 if (mipi_tx->data_rate >= 500000000) { 130 txdiv = 1; 131 txdiv0 = 0; 132 txdiv1 = 0; 133 } else if (mipi_tx->data_rate >= 250000000) { 134 txdiv = 2; 135 txdiv0 = 1; 136 txdiv1 = 0; 137 } else if (mipi_tx->data_rate >= 125000000) { 138 txdiv = 4; 139 txdiv0 = 2; 140 txdiv1 = 0; 141 } else if (mipi_tx->data_rate > 62000000) { 142 txdiv = 8; 143 txdiv0 = 2; 144 txdiv1 = 1; 145 } else if (mipi_tx->data_rate >= 50000000) { 146 txdiv = 16; 147 txdiv0 = 2; 148 txdiv1 = 2; 149 } else { 150 return -EINVAL; 151 } 152 153 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON, 154 RG_DSI_VOUT_MSK | 155 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN, 156 FIELD_PREP(RG_DSI_V02_SEL, 4) | 157 FIELD_PREP(RG_DSI_V032_SEL, 4) | 158 FIELD_PREP(RG_DSI_V04_SEL, 4) | 159 FIELD_PREP(RG_DSI_V072_SEL, 4) | 160 FIELD_PREP(RG_DSI_V10_SEL, 4) | 161 FIELD_PREP(RG_DSI_V12_SEL, 4) | 162 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); 163 164 usleep_range(30, 100); 165 166 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON, 167 RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN, 168 FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) | 169 RG_DSI_LNT_HS_BIAS_EN); 170 171 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON, 172 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); 173 174 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, 175 RG_DSI_MPPLL_SDM_PWR_ON | 176 RG_DSI_MPPLL_SDM_ISO_EN, 177 RG_DSI_MPPLL_SDM_PWR_ON); 178 179 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, 180 RG_DSI_MPPLL_PLL_EN); 181 182 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0, 183 RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | 184 RG_DSI_MPPLL_PREDIV, 185 FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) | 186 FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1)); 187 188 /* 189 * PLL PCW config 190 * PCW bit 24~30 = integer part of pcw 191 * PCW bit 0~23 = fractional part of pcw 192 * pcw = data_Rate*4*txdiv/(Ref_clk*2); 193 * Post DIV =4, so need data_Rate*4 194 * Ref_clk is 26MHz 195 */ 196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 197 26000000); 198 writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2); 199 200 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1, 201 RG_DSI_MPPLL_SDM_FRA_EN); 202 203 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); 204 205 usleep_range(20, 100); 206 207 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1, 208 RG_DSI_MPPLL_SDM_SSC_EN); 209 210 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, 211 RG_DSI_MPPLL_PRESERVE, 212 mipi_tx->driver_data->mppll_preserve); 213 214 return 0; 215 } 216 217 static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw) 218 { 219 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); 220 221 dev_dbg(mipi_tx->dev, "unprepare\n"); 222 223 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, 224 RG_DSI_MPPLL_PLL_EN); 225 226 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP, 227 RG_DSI_MPPLL_PRESERVE, 0); 228 229 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR, 230 RG_DSI_MPPLL_SDM_ISO_EN | 231 RG_DSI_MPPLL_SDM_PWR_ON, 232 RG_DSI_MPPLL_SDM_ISO_EN); 233 234 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON, 235 RG_DSI_LNT_HS_BIAS_EN); 236 237 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON, 238 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); 239 240 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON, 241 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN); 242 243 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0, 244 RG_DSI_MPPLL_DIV_MSK); 245 } 246 247 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, 248 unsigned long *prate) 249 { 250 return clamp_val(rate, 50000000, 1250000000); 251 } 252 253 static const struct clk_ops mtk_mipi_tx_pll_ops = { 254 .prepare = mtk_mipi_tx_pll_prepare, 255 .unprepare = mtk_mipi_tx_pll_unprepare, 256 .round_rate = mtk_mipi_tx_pll_round_rate, 257 .set_rate = mtk_mipi_tx_pll_set_rate, 258 .recalc_rate = mtk_mipi_tx_pll_recalc_rate, 259 }; 260 261 static void mtk_mipi_tx_power_on_signal(struct phy *phy) 262 { 263 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); 264 u32 reg; 265 266 for (reg = MIPITX_DSI_CLOCK_LANE; 267 reg <= MIPITX_DSI_DATA_LANE3; reg += 4) 268 mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); 269 270 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON, 271 RG_DSI_PAD_TIE_LOW_EN); 272 } 273 274 static void mtk_mipi_tx_power_off_signal(struct phy *phy) 275 { 276 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); 277 u32 reg; 278 279 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON, 280 RG_DSI_PAD_TIE_LOW_EN); 281 282 for (reg = MIPITX_DSI_CLOCK_LANE; 283 reg <= MIPITX_DSI_DATA_LANE3; reg += 4) 284 mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); 285 } 286 287 const struct mtk_mipitx_data mt2701_mipitx_data = { 288 .mppll_preserve = (3 << 8), 289 .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, 290 .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, 291 .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, 292 }; 293 294 const struct mtk_mipitx_data mt8173_mipitx_data = { 295 .mppll_preserve = (0 << 8), 296 .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, 297 .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, 298 .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, 299 }; 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