11371b9a5SChunfeng Yun /* SPDX-License-Identifier: GPL-2.0 */ 21371b9a5SChunfeng Yun /* 31371b9a5SChunfeng Yun * Copyright (C) 2021 MediaTek Inc. 41371b9a5SChunfeng Yun * 51371b9a5SChunfeng Yun * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 61371b9a5SChunfeng Yun */ 71371b9a5SChunfeng Yun 81371b9a5SChunfeng Yun #ifndef __PHY_MTK_H__ 91371b9a5SChunfeng Yun #define __PHY_MTK_H__ 101371b9a5SChunfeng Yun 11*29c07477SChunfeng Yun #include <linux/bitfield.h> 121371b9a5SChunfeng Yun #include <linux/io.h> 131371b9a5SChunfeng Yun 141371b9a5SChunfeng Yun static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits) 151371b9a5SChunfeng Yun { 161371b9a5SChunfeng Yun u32 tmp = readl(reg); 171371b9a5SChunfeng Yun 181371b9a5SChunfeng Yun tmp &= ~bits; 191371b9a5SChunfeng Yun writel(tmp, reg); 201371b9a5SChunfeng Yun } 211371b9a5SChunfeng Yun 221371b9a5SChunfeng Yun static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits) 231371b9a5SChunfeng Yun { 241371b9a5SChunfeng Yun u32 tmp = readl(reg); 251371b9a5SChunfeng Yun 261371b9a5SChunfeng Yun tmp |= bits; 271371b9a5SChunfeng Yun writel(tmp, reg); 281371b9a5SChunfeng Yun } 291371b9a5SChunfeng Yun 301371b9a5SChunfeng Yun static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) 311371b9a5SChunfeng Yun { 321371b9a5SChunfeng Yun u32 tmp = readl(reg); 331371b9a5SChunfeng Yun 341371b9a5SChunfeng Yun tmp &= ~mask; 351371b9a5SChunfeng Yun tmp |= val & mask; 361371b9a5SChunfeng Yun writel(tmp, reg); 371371b9a5SChunfeng Yun } 381371b9a5SChunfeng Yun 39*29c07477SChunfeng Yun /* field @mask should be constant and continuous */ 40*29c07477SChunfeng Yun static inline void mtk_phy_update_field(void __iomem *reg, u32 mask, u32 val) 41*29c07477SChunfeng Yun { 42*29c07477SChunfeng Yun mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); 43*29c07477SChunfeng Yun } 44*29c07477SChunfeng Yun 451371b9a5SChunfeng Yun #endif 46