1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include "phy-mtk-hdmi.h" 8 9 #define HDMI_CON0 0x00 10 #define RG_HDMITX_PLL_EN BIT(31) 11 #define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24) 12 #define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22) 13 #define RG_HDMITX_PLL_PREDIV GENMASK(21, 20) 14 #define RG_HDMITX_PLL_POSDIV GENMASK(19, 18) 15 #define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16) 16 #define RG_HDMITX_PLL_IR GENMASK(15, 12) 17 #define RG_HDMITX_PLL_IC GENMASK(11, 8) 18 #define RG_HDMITX_PLL_BP GENMASK(7, 4) 19 #define RG_HDMITX_PLL_BR GENMASK(3, 2) 20 #define RG_HDMITX_PLL_BC GENMASK(1, 0) 21 #define HDMI_CON1 0x04 22 #define RG_HDMITX_PLL_DIVEN GENMASK(31, 29) 23 #define RG_HDMITX_PLL_AUTOK_EN BIT(28) 24 #define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26) 25 #define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24) 26 #define RG_HDMITX_PLL_AUTOK_LOAD BIT(23) 27 #define RG_HDMITX_PLL_BAND GENMASK(21, 16) 28 #define RG_HDMITX_PLL_REF_SEL BIT(15) 29 #define RG_HDMITX_PLL_BIAS_EN BIT(14) 30 #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13) 31 #define RG_HDMITX_PLL_TXDIV_EN BIT(12) 32 #define RG_HDMITX_PLL_TXDIV GENMASK(11, 10) 33 #define RG_HDMITX_PLL_LVROD_EN BIT(9) 34 #define RG_HDMITX_PLL_MONVC_EN BIT(8) 35 #define RG_HDMITX_PLL_MONCK_EN BIT(7) 36 #define RG_HDMITX_PLL_MONREF_EN BIT(6) 37 #define RG_HDMITX_PLL_TST_EN BIT(5) 38 #define RG_HDMITX_PLL_TST_CK_EN BIT(4) 39 #define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0) 40 #define HDMI_CON2 0x08 41 #define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8) 42 #define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1) 43 #define RG_HDMITX_EN_TX_CKLDO BIT(0) 44 #define HDMI_CON3 0x0c 45 #define RG_HDMITX_SER_EN GENMASK(31, 28) 46 #define RG_HDMITX_PRD_EN GENMASK(27, 24) 47 #define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20) 48 #define RG_HDMITX_DRV_EN GENMASK(19, 16) 49 #define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12) 50 #define RG_HDMITX_MHLCK_FORCE BIT(10) 51 #define RG_HDMITX_MHLCK_PPIX_EN BIT(9) 52 #define RG_HDMITX_MHLCK_EN BIT(8) 53 #define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4) 54 #define RG_HDMITX_SER_5T1_BIST_EN BIT(3) 55 #define RG_HDMITX_SER_BIST_TOG BIT(2) 56 #define RG_HDMITX_SER_DIN_TOG BIT(1) 57 #define RG_HDMITX_SER_CLKDIG_INV BIT(0) 58 #define HDMI_CON4 0x10 59 #define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24) 60 #define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16) 61 #define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8) 62 #define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0) 63 #define HDMI_CON5 0x14 64 #define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24) 65 #define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16) 66 #define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8) 67 #define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0) 68 #define HDMI_CON6 0x18 69 #define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24) 70 #define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16) 71 #define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8) 72 #define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0) 73 #define HDMI_CON7 0x1c 74 #define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27) 75 #define RG_HDMITX_SER_DIN GENMASK(25, 16) 76 #define RG_HDMITX_CHLDC_TST GENMASK(15, 12) 77 #define RG_HDMITX_CHLCK_TST GENMASK(11, 8) 78 #define RG_HDMITX_RESERVE GENMASK(7, 0) 79 #define HDMI_CON8 0x20 80 #define RGS_HDMITX_2T1_LEV GENMASK(19, 16) 81 #define RGS_HDMITX_2T1_EDG GENMASK(15, 12) 82 #define RGS_HDMITX_5T1_LEV GENMASK(11, 8) 83 #define RGS_HDMITX_5T1_EDG GENMASK(7, 4) 84 #define RGS_HDMITX_PLUG_TST BIT(0) 85 86 static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 87 { 88 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 89 90 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 91 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 92 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN); 93 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 94 usleep_range(100, 150); 95 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); 96 usleep_range(100, 150); 97 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 98 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 99 100 return 0; 101 } 102 103 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 104 { 105 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 106 107 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 108 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 109 usleep_range(100, 150); 110 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); 111 usleep_range(100, 150); 112 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 113 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 114 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 115 usleep_range(100, 150); 116 } 117 118 static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, 119 unsigned long *parent_rate) 120 { 121 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 122 123 hdmi_phy->pll_rate = rate; 124 if (rate <= 74250000) 125 *parent_rate = rate; 126 else 127 *parent_rate = rate / 2; 128 129 return rate; 130 } 131 132 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 133 unsigned long parent_rate) 134 { 135 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 136 unsigned int pre_div; 137 unsigned int div; 138 unsigned int pre_ibias; 139 unsigned int hdmi_ibias; 140 unsigned int imp_en; 141 142 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, 143 rate, parent_rate); 144 145 if (rate <= 27000000) { 146 pre_div = 0; 147 div = 3; 148 } else if (rate <= 74250000) { 149 pre_div = 1; 150 div = 2; 151 } else { 152 pre_div = 1; 153 div = 1; 154 } 155 156 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 157 FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div), 158 RG_HDMITX_PLL_PREDIV); 159 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 160 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 161 FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) | 162 FIELD_PREP(RG_HDMITX_PLL_IR, 0x1), 163 RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR); 164 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, 165 FIELD_PREP(RG_HDMITX_PLL_TXDIV, div), 166 RG_HDMITX_PLL_TXDIV); 167 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 168 FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) | 169 FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19), 170 RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV); 171 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, 172 FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2), 173 RG_HDMITX_PLL_DIVEN); 174 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 175 FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) | 176 FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) | 177 FIELD_PREP(RG_HDMITX_PLL_BR, 0x1), 178 RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | 179 RG_HDMITX_PLL_BR); 180 if (rate < 165000000) { 181 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, 182 RG_HDMITX_PRD_IMP_EN); 183 pre_ibias = 0x3; 184 imp_en = 0x0; 185 hdmi_ibias = hdmi_phy->ibias; 186 } else { 187 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, 188 RG_HDMITX_PRD_IMP_EN); 189 pre_ibias = 0x6; 190 imp_en = 0xf; 191 hdmi_ibias = hdmi_phy->ibias_up; 192 } 193 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 194 FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) | 195 FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) | 196 FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) | 197 FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias), 198 RG_HDMITX_PRD_IBIAS_CLK | 199 RG_HDMITX_PRD_IBIAS_D2 | 200 RG_HDMITX_PRD_IBIAS_D1 | 201 RG_HDMITX_PRD_IBIAS_D0); 202 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, 203 FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en), 204 RG_HDMITX_DRV_IMP_EN); 205 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, 206 FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) | 207 FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) | 208 FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) | 209 FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0), 210 RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | 211 RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); 212 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, 213 FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) | 214 FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) | 215 FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) | 216 FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias), 217 RG_HDMITX_DRV_IBIAS_CLK | 218 RG_HDMITX_DRV_IBIAS_D2 | 219 RG_HDMITX_DRV_IBIAS_D1 | 220 RG_HDMITX_DRV_IBIAS_D0); 221 return 0; 222 } 223 224 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, 225 unsigned long parent_rate) 226 { 227 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 228 229 return hdmi_phy->pll_rate; 230 } 231 232 static const struct clk_ops mtk_hdmi_phy_pll_ops = { 233 .prepare = mtk_hdmi_pll_prepare, 234 .unprepare = mtk_hdmi_pll_unprepare, 235 .set_rate = mtk_hdmi_pll_set_rate, 236 .round_rate = mtk_hdmi_pll_round_rate, 237 .recalc_rate = mtk_hdmi_pll_recalc_rate, 238 }; 239 240 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 241 { 242 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, 243 RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | 244 RG_HDMITX_DRV_EN); 245 usleep_range(100, 150); 246 } 247 248 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 249 { 250 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, 251 RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | 252 RG_HDMITX_SER_EN); 253 } 254 255 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = { 256 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 257 .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, 258 .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, 259 .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, 260 }; 261 262 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 263 MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver"); 264 MODULE_LICENSE("GPL v2"); 265