1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include "phy-mtk-hdmi.h" 8 9 #define HDMI_CON0 0x00 10 #define RG_HDMITX_PLL_EN BIT(31) 11 #define RG_HDMITX_PLL_FBKDIV (0x7f << 24) 12 #define PLL_FBKDIV_SHIFT 24 13 #define RG_HDMITX_PLL_FBKSEL (0x3 << 22) 14 #define PLL_FBKSEL_SHIFT 22 15 #define RG_HDMITX_PLL_PREDIV (0x3 << 20) 16 #define PREDIV_SHIFT 20 17 #define RG_HDMITX_PLL_POSDIV (0x3 << 18) 18 #define POSDIV_SHIFT 18 19 #define RG_HDMITX_PLL_RST_DLY (0x3 << 16) 20 #define RG_HDMITX_PLL_IR (0xf << 12) 21 #define PLL_IR_SHIFT 12 22 #define RG_HDMITX_PLL_IC (0xf << 8) 23 #define PLL_IC_SHIFT 8 24 #define RG_HDMITX_PLL_BP (0xf << 4) 25 #define PLL_BP_SHIFT 4 26 #define RG_HDMITX_PLL_BR (0x3 << 2) 27 #define PLL_BR_SHIFT 2 28 #define RG_HDMITX_PLL_BC (0x3 << 0) 29 #define PLL_BC_SHIFT 0 30 #define HDMI_CON1 0x04 31 #define RG_HDMITX_PLL_DIVEN (0x7 << 29) 32 #define PLL_DIVEN_SHIFT 29 33 #define RG_HDMITX_PLL_AUTOK_EN BIT(28) 34 #define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26) 35 #define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24) 36 #define RG_HDMITX_PLL_AUTOK_LOAD BIT(23) 37 #define RG_HDMITX_PLL_BAND (0x3f << 16) 38 #define RG_HDMITX_PLL_REF_SEL BIT(15) 39 #define RG_HDMITX_PLL_BIAS_EN BIT(14) 40 #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13) 41 #define RG_HDMITX_PLL_TXDIV_EN BIT(12) 42 #define RG_HDMITX_PLL_TXDIV (0x3 << 10) 43 #define PLL_TXDIV_SHIFT 10 44 #define RG_HDMITX_PLL_LVROD_EN BIT(9) 45 #define RG_HDMITX_PLL_MONVC_EN BIT(8) 46 #define RG_HDMITX_PLL_MONCK_EN BIT(7) 47 #define RG_HDMITX_PLL_MONREF_EN BIT(6) 48 #define RG_HDMITX_PLL_TST_EN BIT(5) 49 #define RG_HDMITX_PLL_TST_CK_EN BIT(4) 50 #define RG_HDMITX_PLL_TST_SEL (0xf << 0) 51 #define HDMI_CON2 0x08 52 #define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8) 53 #define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1) 54 #define RG_HDMITX_EN_TX_CKLDO BIT(0) 55 #define HDMI_CON3 0x0c 56 #define RG_HDMITX_SER_EN (0xf << 28) 57 #define RG_HDMITX_PRD_EN (0xf << 24) 58 #define RG_HDMITX_PRD_IMP_EN (0xf << 20) 59 #define RG_HDMITX_DRV_EN (0xf << 16) 60 #define RG_HDMITX_DRV_IMP_EN (0xf << 12) 61 #define DRV_IMP_EN_SHIFT 12 62 #define RG_HDMITX_MHLCK_FORCE BIT(10) 63 #define RG_HDMITX_MHLCK_PPIX_EN BIT(9) 64 #define RG_HDMITX_MHLCK_EN BIT(8) 65 #define RG_HDMITX_SER_DIN_SEL (0xf << 4) 66 #define RG_HDMITX_SER_5T1_BIST_EN BIT(3) 67 #define RG_HDMITX_SER_BIST_TOG BIT(2) 68 #define RG_HDMITX_SER_DIN_TOG BIT(1) 69 #define RG_HDMITX_SER_CLKDIG_INV BIT(0) 70 #define HDMI_CON4 0x10 71 #define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24) 72 #define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16) 73 #define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8) 74 #define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0) 75 #define PRD_IBIAS_CLK_SHIFT 24 76 #define PRD_IBIAS_D2_SHIFT 16 77 #define PRD_IBIAS_D1_SHIFT 8 78 #define PRD_IBIAS_D0_SHIFT 0 79 #define HDMI_CON5 0x14 80 #define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24) 81 #define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16) 82 #define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8) 83 #define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0) 84 #define DRV_IBIAS_CLK_SHIFT 24 85 #define DRV_IBIAS_D2_SHIFT 16 86 #define DRV_IBIAS_D1_SHIFT 8 87 #define DRV_IBIAS_D0_SHIFT 0 88 #define HDMI_CON6 0x18 89 #define RG_HDMITX_DRV_IMP_CLK (0x3f << 24) 90 #define RG_HDMITX_DRV_IMP_D2 (0x3f << 16) 91 #define RG_HDMITX_DRV_IMP_D1 (0x3f << 8) 92 #define RG_HDMITX_DRV_IMP_D0 (0x3f << 0) 93 #define DRV_IMP_CLK_SHIFT 24 94 #define DRV_IMP_D2_SHIFT 16 95 #define DRV_IMP_D1_SHIFT 8 96 #define DRV_IMP_D0_SHIFT 0 97 #define HDMI_CON7 0x1c 98 #define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27) 99 #define RG_HDMITX_SER_DIN (0x3ff << 16) 100 #define RG_HDMITX_CHLDC_TST (0xf << 12) 101 #define RG_HDMITX_CHLCK_TST (0xf << 8) 102 #define RG_HDMITX_RESERVE (0xff << 0) 103 #define HDMI_CON8 0x20 104 #define RGS_HDMITX_2T1_LEV (0xf << 16) 105 #define RGS_HDMITX_2T1_EDG (0xf << 12) 106 #define RGS_HDMITX_5T1_LEV (0xf << 8) 107 #define RGS_HDMITX_5T1_EDG (0xf << 4) 108 #define RGS_HDMITX_PLUG_TST BIT(0) 109 110 static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 111 { 112 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 113 114 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 115 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 116 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN); 117 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 118 usleep_range(100, 150); 119 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); 120 usleep_range(100, 150); 121 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 122 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 123 124 return 0; 125 } 126 127 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 128 { 129 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 130 131 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); 132 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); 133 usleep_range(100, 150); 134 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN); 135 usleep_range(100, 150); 136 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); 137 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 138 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); 139 usleep_range(100, 150); 140 } 141 142 static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, 143 unsigned long *parent_rate) 144 { 145 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 146 147 hdmi_phy->pll_rate = rate; 148 if (rate <= 74250000) 149 *parent_rate = rate; 150 else 151 *parent_rate = rate / 2; 152 153 return rate; 154 } 155 156 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 157 unsigned long parent_rate) 158 { 159 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 160 unsigned int pre_div; 161 unsigned int div; 162 unsigned int pre_ibias; 163 unsigned int hdmi_ibias; 164 unsigned int imp_en; 165 166 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, 167 rate, parent_rate); 168 169 if (rate <= 27000000) { 170 pre_div = 0; 171 div = 3; 172 } else if (rate <= 74250000) { 173 pre_div = 1; 174 div = 2; 175 } else { 176 pre_div = 1; 177 div = 1; 178 } 179 180 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 181 (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV); 182 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV); 183 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 184 (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT), 185 RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR); 186 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, 187 (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV); 188 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 189 (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT), 190 RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV); 191 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, 192 (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN); 193 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, 194 (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) | 195 (0x1 << PLL_BR_SHIFT), 196 RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | 197 RG_HDMITX_PLL_BR); 198 if (rate < 165000000) { 199 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, 200 RG_HDMITX_PRD_IMP_EN); 201 pre_ibias = 0x3; 202 imp_en = 0x0; 203 hdmi_ibias = hdmi_phy->ibias; 204 } else { 205 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, 206 RG_HDMITX_PRD_IMP_EN); 207 pre_ibias = 0x6; 208 imp_en = 0xf; 209 hdmi_ibias = hdmi_phy->ibias_up; 210 } 211 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 212 (pre_ibias << PRD_IBIAS_CLK_SHIFT) | 213 (pre_ibias << PRD_IBIAS_D2_SHIFT) | 214 (pre_ibias << PRD_IBIAS_D1_SHIFT) | 215 (pre_ibias << PRD_IBIAS_D0_SHIFT), 216 RG_HDMITX_PRD_IBIAS_CLK | 217 RG_HDMITX_PRD_IBIAS_D2 | 218 RG_HDMITX_PRD_IBIAS_D1 | 219 RG_HDMITX_PRD_IBIAS_D0); 220 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, 221 (imp_en << DRV_IMP_EN_SHIFT), 222 RG_HDMITX_DRV_IMP_EN); 223 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, 224 (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | 225 (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | 226 (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) | 227 (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT), 228 RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | 229 RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); 230 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, 231 (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | 232 (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | 233 (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | 234 (hdmi_ibias << DRV_IBIAS_D0_SHIFT), 235 RG_HDMITX_DRV_IBIAS_CLK | 236 RG_HDMITX_DRV_IBIAS_D2 | 237 RG_HDMITX_DRV_IBIAS_D1 | 238 RG_HDMITX_DRV_IBIAS_D0); 239 return 0; 240 } 241 242 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, 243 unsigned long parent_rate) 244 { 245 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 246 247 return hdmi_phy->pll_rate; 248 } 249 250 static const struct clk_ops mtk_hdmi_phy_pll_ops = { 251 .prepare = mtk_hdmi_pll_prepare, 252 .unprepare = mtk_hdmi_pll_unprepare, 253 .set_rate = mtk_hdmi_pll_set_rate, 254 .round_rate = mtk_hdmi_pll_round_rate, 255 .recalc_rate = mtk_hdmi_pll_recalc_rate, 256 }; 257 258 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 259 { 260 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, 261 RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN | 262 RG_HDMITX_DRV_EN); 263 usleep_range(100, 150); 264 } 265 266 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 267 { 268 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, 269 RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN | 270 RG_HDMITX_SER_EN); 271 } 272 273 struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = { 274 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 275 .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, 276 .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, 277 .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, 278 }; 279 280 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 281 MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver"); 282 MODULE_LICENSE("GPL v2"); 283