1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Chunhui Dai <chunhui.dai@mediatek.com> 5 */ 6 7 #include "phy-mtk-hdmi.h" 8 9 #define HDMI_CON0 0x00 10 #define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0) 11 #define RG_HDMITX_EN_SER_MASK GENMASK(15, 12) 12 #define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16) 13 #define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20) 14 #define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24) 15 #define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28) 16 17 #define HDMI_CON1 0x04 18 #define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18) 19 #define RG_HDMITX_PRED_IMP BIT(22) 20 #define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26) 21 22 #define HDMI_CON2 0x08 23 #define RG_HDMITX_EN_TX_CKLDO BIT(0) 24 #define RG_HDMITX_EN_TX_POSDIV BIT(1) 25 #define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3) 26 #define RG_HDMITX_EN_MBIAS BIT(6) 27 #define RG_HDMITX_MBIAS_LPF_EN BIT(7) 28 29 #define HDMI_CON4 0x10 30 #define RG_HDMITX_RESERVE_MASK GENMASK(31, 0) 31 32 #define HDMI_CON6 0x18 33 #define RG_HTPLL_BR_MASK GENMASK(1, 0) 34 #define RG_HTPLL_BC_MASK GENMASK(3, 2) 35 #define RG_HTPLL_BP_MASK GENMASK(7, 4) 36 #define RG_HTPLL_IR_MASK GENMASK(11, 8) 37 #define RG_HTPLL_IC_MASK GENMASK(15, 12) 38 #define RG_HTPLL_POSDIV_MASK GENMASK(17, 16) 39 #define RG_HTPLL_PREDIV_MASK GENMASK(19, 18) 40 #define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20) 41 #define RG_HTPLL_RLH_EN BIT(22) 42 #define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24) 43 #define RG_HTPLL_EN BIT(31) 44 45 #define HDMI_CON7 0x1c 46 #define RG_HTPLL_AUTOK_EN BIT(23) 47 #define RG_HTPLL_DIVEN_MASK GENMASK(30, 28) 48 49 static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 50 { 51 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 52 53 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 54 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 55 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 56 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 57 usleep_range(80, 100); 58 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 59 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 60 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 61 usleep_range(80, 100); 62 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 63 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 64 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 65 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 66 usleep_range(80, 100); 67 return 0; 68 } 69 70 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 71 { 72 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 73 74 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 75 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 76 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 77 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 78 usleep_range(80, 100); 79 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 80 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 81 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 82 usleep_range(80, 100); 83 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 84 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 85 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 86 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 87 usleep_range(80, 100); 88 } 89 90 static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, 91 unsigned long *parent_rate) 92 { 93 return rate; 94 } 95 96 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 97 unsigned long parent_rate) 98 { 99 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 100 u32 pos_div; 101 102 if (rate <= 64000000) 103 pos_div = 3; 104 else if (rate <= 128000000) 105 pos_div = 2; 106 else 107 pos_div = 1; 108 109 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK); 110 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 111 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); 112 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1), 113 RG_HTPLL_IC_MASK); 114 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1), 115 RG_HTPLL_IR_MASK); 116 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div), 117 RG_HDMITX_TX_POSDIV_MASK); 118 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1), 119 RG_HTPLL_FBKSEL_MASK); 120 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19), 121 RG_HTPLL_FBKDIV_MASK); 122 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2), 123 RG_HTPLL_DIVEN_MASK); 124 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc), 125 RG_HTPLL_BP_MASK); 126 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2), 127 RG_HTPLL_BC_MASK); 128 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1), 129 RG_HTPLL_BR_MASK); 130 131 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP); 132 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3), 133 RG_HDMITX_PRED_IBIAS_MASK); 134 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); 135 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28), 136 RG_HDMITX_DRV_IMP_MASK); 137 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK); 138 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa), 139 RG_HDMITX_DRV_IBIAS_MASK); 140 return 0; 141 } 142 143 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, 144 unsigned long parent_rate) 145 { 146 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 147 unsigned long out_rate, val; 148 u32 tmp; 149 150 tmp = readl(hdmi_phy->regs + HDMI_CON6); 151 val = FIELD_GET(RG_HTPLL_PREDIV_MASK, tmp); 152 switch (val) { 153 case 0x00: 154 out_rate = parent_rate; 155 break; 156 case 0x01: 157 out_rate = parent_rate / 2; 158 break; 159 default: 160 out_rate = parent_rate / 4; 161 break; 162 } 163 164 val = FIELD_GET(RG_HTPLL_FBKDIV_MASK, tmp); 165 out_rate *= (val + 1) * 2; 166 167 tmp = readl(hdmi_phy->regs + HDMI_CON2); 168 val = FIELD_GET(RG_HDMITX_TX_POSDIV_MASK, tmp); 169 out_rate >>= val; 170 171 if (tmp & RG_HDMITX_EN_TX_POSDIV) 172 out_rate /= 5; 173 174 return out_rate; 175 } 176 177 static const struct clk_ops mtk_hdmi_phy_pll_ops = { 178 .prepare = mtk_hdmi_pll_prepare, 179 .unprepare = mtk_hdmi_pll_unprepare, 180 .set_rate = mtk_hdmi_pll_set_rate, 181 .round_rate = mtk_hdmi_pll_round_rate, 182 .recalc_rate = mtk_hdmi_pll_recalc_rate, 183 }; 184 185 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 186 { 187 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 188 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 189 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 190 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 191 usleep_range(80, 100); 192 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 193 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 194 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 195 usleep_range(80, 100); 196 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 197 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 198 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 199 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 200 usleep_range(80, 100); 201 } 202 203 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 204 { 205 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 206 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 207 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 208 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 209 usleep_range(80, 100); 210 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 211 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 212 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 213 usleep_range(80, 100); 214 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 215 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 216 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 217 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 218 usleep_range(80, 100); 219 } 220 221 struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = { 222 .flags = CLK_SET_RATE_GATE, 223 .pll_default_off = true, 224 .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, 225 .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, 226 .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, 227 }; 228 229 MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>"); 230 MODULE_DESCRIPTION("MediaTek HDMI PHY Driver"); 231 MODULE_LICENSE("GPL v2"); 232