1b28be59aSCK Hu // SPDX-License-Identifier: GPL-2.0 2b28be59aSCK Hu /* 3b28be59aSCK Hu * Copyright (c) 2018 MediaTek Inc. 4b28be59aSCK Hu * Author: Chunhui Dai <chunhui.dai@mediatek.com> 5b28be59aSCK Hu */ 6b28be59aSCK Hu 7b28be59aSCK Hu #include "phy-mtk-hdmi.h" 8b28be59aSCK Hu 9b28be59aSCK Hu #define HDMI_CON0 0x00 10b28be59aSCK Hu #define RG_HDMITX_DRV_IBIAS 0 11b28be59aSCK Hu #define RG_HDMITX_DRV_IBIAS_MASK (0x3f << 0) 12b28be59aSCK Hu #define RG_HDMITX_EN_SER 12 13b28be59aSCK Hu #define RG_HDMITX_EN_SER_MASK (0x0f << 12) 14b28be59aSCK Hu #define RG_HDMITX_EN_SLDO 16 15b28be59aSCK Hu #define RG_HDMITX_EN_SLDO_MASK (0x0f << 16) 16b28be59aSCK Hu #define RG_HDMITX_EN_PRED 20 17b28be59aSCK Hu #define RG_HDMITX_EN_PRED_MASK (0x0f << 20) 18b28be59aSCK Hu #define RG_HDMITX_EN_IMP 24 19b28be59aSCK Hu #define RG_HDMITX_EN_IMP_MASK (0x0f << 24) 20b28be59aSCK Hu #define RG_HDMITX_EN_DRV 28 21b28be59aSCK Hu #define RG_HDMITX_EN_DRV_MASK (0x0f << 28) 22b28be59aSCK Hu 23b28be59aSCK Hu #define HDMI_CON1 0x04 24b28be59aSCK Hu #define RG_HDMITX_PRED_IBIAS 18 25b28be59aSCK Hu #define RG_HDMITX_PRED_IBIAS_MASK (0x0f << 18) 26b28be59aSCK Hu #define RG_HDMITX_PRED_IMP (0x01 << 22) 27b28be59aSCK Hu #define RG_HDMITX_DRV_IMP 26 28b28be59aSCK Hu #define RG_HDMITX_DRV_IMP_MASK (0x3f << 26) 29b28be59aSCK Hu 30b28be59aSCK Hu #define HDMI_CON2 0x08 31b28be59aSCK Hu #define RG_HDMITX_EN_TX_CKLDO (0x01 << 0) 32b28be59aSCK Hu #define RG_HDMITX_EN_TX_POSDIV (0x01 << 1) 33b28be59aSCK Hu #define RG_HDMITX_TX_POSDIV 3 34b28be59aSCK Hu #define RG_HDMITX_TX_POSDIV_MASK (0x03 << 3) 35b28be59aSCK Hu #define RG_HDMITX_EN_MBIAS (0x01 << 6) 36b28be59aSCK Hu #define RG_HDMITX_MBIAS_LPF_EN (0x01 << 7) 37b28be59aSCK Hu 38b28be59aSCK Hu #define HDMI_CON4 0x10 39b28be59aSCK Hu #define RG_HDMITX_RESERVE_MASK (0xffffffff << 0) 40b28be59aSCK Hu 41b28be59aSCK Hu #define HDMI_CON6 0x18 42b28be59aSCK Hu #define RG_HTPLL_BR 0 43b28be59aSCK Hu #define RG_HTPLL_BR_MASK (0x03 << 0) 44b28be59aSCK Hu #define RG_HTPLL_BC 2 45b28be59aSCK Hu #define RG_HTPLL_BC_MASK (0x03 << 2) 46b28be59aSCK Hu #define RG_HTPLL_BP 4 47b28be59aSCK Hu #define RG_HTPLL_BP_MASK (0x0f << 4) 48b28be59aSCK Hu #define RG_HTPLL_IR 8 49b28be59aSCK Hu #define RG_HTPLL_IR_MASK (0x0f << 8) 50b28be59aSCK Hu #define RG_HTPLL_IC 12 51b28be59aSCK Hu #define RG_HTPLL_IC_MASK (0x0f << 12) 52b28be59aSCK Hu #define RG_HTPLL_POSDIV 16 53b28be59aSCK Hu #define RG_HTPLL_POSDIV_MASK (0x03 << 16) 54b28be59aSCK Hu #define RG_HTPLL_PREDIV 18 55b28be59aSCK Hu #define RG_HTPLL_PREDIV_MASK (0x03 << 18) 56b28be59aSCK Hu #define RG_HTPLL_FBKSEL 20 57b28be59aSCK Hu #define RG_HTPLL_FBKSEL_MASK (0x03 << 20) 58b28be59aSCK Hu #define RG_HTPLL_RLH_EN (0x01 << 22) 59b28be59aSCK Hu #define RG_HTPLL_FBKDIV 24 60b28be59aSCK Hu #define RG_HTPLL_FBKDIV_MASK (0x7f << 24) 61b28be59aSCK Hu #define RG_HTPLL_EN (0x01 << 31) 62b28be59aSCK Hu 63b28be59aSCK Hu #define HDMI_CON7 0x1c 64b28be59aSCK Hu #define RG_HTPLL_AUTOK_EN (0x01 << 23) 65b28be59aSCK Hu #define RG_HTPLL_DIVEN 28 66b28be59aSCK Hu #define RG_HTPLL_DIVEN_MASK (0x07 << 28) 67b28be59aSCK Hu 68b28be59aSCK Hu static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 69b28be59aSCK Hu { 70b28be59aSCK Hu struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 71b28be59aSCK Hu 72b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 73b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 74b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 75b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 76b28be59aSCK Hu usleep_range(80, 100); 77b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 78b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 79b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 80b28be59aSCK Hu usleep_range(80, 100); 81b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 82b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 83b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 84b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 85b28be59aSCK Hu usleep_range(80, 100); 86b28be59aSCK Hu return 0; 87b28be59aSCK Hu } 88b28be59aSCK Hu 89b28be59aSCK Hu static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 90b28be59aSCK Hu { 91b28be59aSCK Hu struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 92b28be59aSCK Hu 93b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 94b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 95b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 96b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 97b28be59aSCK Hu usleep_range(80, 100); 98b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 99b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 100b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 101b28be59aSCK Hu usleep_range(80, 100); 102b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 103b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 104b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 105b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 106b28be59aSCK Hu usleep_range(80, 100); 107b28be59aSCK Hu } 108b28be59aSCK Hu 109b28be59aSCK Hu static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, 110b28be59aSCK Hu unsigned long *parent_rate) 111b28be59aSCK Hu { 112b28be59aSCK Hu return rate; 113b28be59aSCK Hu } 114b28be59aSCK Hu 115b28be59aSCK Hu static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 116b28be59aSCK Hu unsigned long parent_rate) 117b28be59aSCK Hu { 118b28be59aSCK Hu struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 119b28be59aSCK Hu u32 pos_div; 120b28be59aSCK Hu 121b28be59aSCK Hu if (rate <= 64000000) 122b28be59aSCK Hu pos_div = 3; 123b28be59aSCK Hu else if (rate <= 128000000) 124b28be59aSCK Hu pos_div = 2; 125b28be59aSCK Hu else 126b28be59aSCK Hu pos_div = 1; 127b28be59aSCK Hu 128b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK); 129b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 130b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); 131b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC), 132b28be59aSCK Hu RG_HTPLL_IC_MASK); 133b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR), 134b28be59aSCK Hu RG_HTPLL_IR_MASK); 135b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV), 136b28be59aSCK Hu RG_HDMITX_TX_POSDIV_MASK); 137b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL), 138b28be59aSCK Hu RG_HTPLL_FBKSEL_MASK); 139b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV), 140b28be59aSCK Hu RG_HTPLL_FBKDIV_MASK); 141b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN), 142b28be59aSCK Hu RG_HTPLL_DIVEN_MASK); 143b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP), 144b28be59aSCK Hu RG_HTPLL_BP_MASK); 145b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC), 146b28be59aSCK Hu RG_HTPLL_BC_MASK); 147b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR), 148b28be59aSCK Hu RG_HTPLL_BR_MASK); 149b28be59aSCK Hu 150b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP); 151b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS), 152b28be59aSCK Hu RG_HDMITX_PRED_IBIAS_MASK); 153b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); 154b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP), 155b28be59aSCK Hu RG_HDMITX_DRV_IMP_MASK); 156b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK); 157b28be59aSCK Hu mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS), 158b28be59aSCK Hu RG_HDMITX_DRV_IBIAS_MASK); 159b28be59aSCK Hu return 0; 160b28be59aSCK Hu } 161b28be59aSCK Hu 162b28be59aSCK Hu static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, 163b28be59aSCK Hu unsigned long parent_rate) 164b28be59aSCK Hu { 165b28be59aSCK Hu struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 166b28be59aSCK Hu unsigned long out_rate, val; 167b28be59aSCK Hu 168b28be59aSCK Hu val = (readl(hdmi_phy->regs + HDMI_CON6) 169b28be59aSCK Hu & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV; 170b28be59aSCK Hu switch (val) { 171b28be59aSCK Hu case 0x00: 172b28be59aSCK Hu out_rate = parent_rate; 173b28be59aSCK Hu break; 174b28be59aSCK Hu case 0x01: 175b28be59aSCK Hu out_rate = parent_rate / 2; 176b28be59aSCK Hu break; 177b28be59aSCK Hu default: 178b28be59aSCK Hu out_rate = parent_rate / 4; 179b28be59aSCK Hu break; 180b28be59aSCK Hu } 181b28be59aSCK Hu 182b28be59aSCK Hu val = (readl(hdmi_phy->regs + HDMI_CON6) 183b28be59aSCK Hu & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV; 184b28be59aSCK Hu out_rate *= (val + 1) * 2; 185b28be59aSCK Hu val = (readl(hdmi_phy->regs + HDMI_CON2) 186b28be59aSCK Hu & RG_HDMITX_TX_POSDIV_MASK); 187b28be59aSCK Hu out_rate >>= (val >> RG_HDMITX_TX_POSDIV); 188b28be59aSCK Hu 189b28be59aSCK Hu if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV) 190b28be59aSCK Hu out_rate /= 5; 191b28be59aSCK Hu 192b28be59aSCK Hu return out_rate; 193b28be59aSCK Hu } 194b28be59aSCK Hu 195b28be59aSCK Hu static const struct clk_ops mtk_hdmi_phy_pll_ops = { 196b28be59aSCK Hu .prepare = mtk_hdmi_pll_prepare, 197b28be59aSCK Hu .unprepare = mtk_hdmi_pll_unprepare, 198b28be59aSCK Hu .set_rate = mtk_hdmi_pll_set_rate, 199b28be59aSCK Hu .round_rate = mtk_hdmi_pll_round_rate, 200b28be59aSCK Hu .recalc_rate = mtk_hdmi_pll_recalc_rate, 201b28be59aSCK Hu }; 202b28be59aSCK Hu 203b28be59aSCK Hu static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 204b28be59aSCK Hu { 205b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 206b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 207b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 208b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 209b28be59aSCK Hu usleep_range(80, 100); 210b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 211b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 212b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 213b28be59aSCK Hu usleep_range(80, 100); 214b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 215b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 216b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 217b28be59aSCK Hu mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 218b28be59aSCK Hu usleep_range(80, 100); 219b28be59aSCK Hu } 220b28be59aSCK Hu 221b28be59aSCK Hu static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 222b28be59aSCK Hu { 223b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 224b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 225b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 226b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 227b28be59aSCK Hu usleep_range(80, 100); 228b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 229b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 230b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 231b28be59aSCK Hu usleep_range(80, 100); 232b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 233b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 234b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 235b28be59aSCK Hu mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 236b28be59aSCK Hu usleep_range(80, 100); 237b28be59aSCK Hu } 238b28be59aSCK Hu 239b28be59aSCK Hu struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = { 240b28be59aSCK Hu .flags = CLK_SET_RATE_GATE, 24109e872d5Schunhui dai .pll_default_off = true, 242b28be59aSCK Hu .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, 243b28be59aSCK Hu .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, 244b28be59aSCK Hu .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds, 245b28be59aSCK Hu }; 246b28be59aSCK Hu 247b28be59aSCK Hu MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>"); 248b28be59aSCK Hu MODULE_DESCRIPTION("MediaTek HDMI PHY Driver"); 249b28be59aSCK Hu MODULE_LICENSE("GPL v2"); 250