19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20b56e9a7SVivek Gautam /* 30b56e9a7SVivek Gautam * Copyright (C) 2015 Linaro, Ltd. 40b56e9a7SVivek Gautam * Rob Herring <robh@kernel.org> 50b56e9a7SVivek Gautam * 60b56e9a7SVivek Gautam * Based on vendor driver: 70b56e9a7SVivek Gautam * Copyright (C) 2013 Marvell Inc. 80b56e9a7SVivek Gautam * Author: Chao Xie <xiechao.mail@gmail.com> 90b56e9a7SVivek Gautam */ 100b56e9a7SVivek Gautam 110b56e9a7SVivek Gautam #include <linux/delay.h> 120b56e9a7SVivek Gautam #include <linux/slab.h> 130b56e9a7SVivek Gautam #include <linux/of.h> 140b56e9a7SVivek Gautam #include <linux/io.h> 15f63602b1SChunfeng Yun #include <linux/iopoll.h> 160b56e9a7SVivek Gautam #include <linux/err.h> 170b56e9a7SVivek Gautam #include <linux/clk.h> 180b56e9a7SVivek Gautam #include <linux/module.h> 190b56e9a7SVivek Gautam #include <linux/platform_device.h> 200b56e9a7SVivek Gautam #include <linux/phy/phy.h> 210b56e9a7SVivek Gautam 220b56e9a7SVivek Gautam #define PHY_28NM_HSIC_CTRL 0x08 230b56e9a7SVivek Gautam #define PHY_28NM_HSIC_IMPCAL_CAL 0x18 240b56e9a7SVivek Gautam #define PHY_28NM_HSIC_PLL_CTRL01 0x1c 250b56e9a7SVivek Gautam #define PHY_28NM_HSIC_PLL_CTRL2 0x20 260b56e9a7SVivek Gautam #define PHY_28NM_HSIC_INT 0x28 270b56e9a7SVivek Gautam 280b56e9a7SVivek Gautam #define PHY_28NM_HSIC_PLL_SELLPFR_SHIFT 26 290b56e9a7SVivek Gautam #define PHY_28NM_HSIC_PLL_FBDIV_SHIFT 0 300b56e9a7SVivek Gautam #define PHY_28NM_HSIC_PLL_REFDIV_SHIFT 9 310b56e9a7SVivek Gautam 320b56e9a7SVivek Gautam #define PHY_28NM_HSIC_S2H_PU_PLL BIT(10) 330b56e9a7SVivek Gautam #define PHY_28NM_HSIC_H2S_PLL_LOCK BIT(15) 340b56e9a7SVivek Gautam #define PHY_28NM_HSIC_S2H_HSIC_EN BIT(7) 350b56e9a7SVivek Gautam #define S2H_DRV_SE0_4RESUME BIT(14) 360b56e9a7SVivek Gautam #define PHY_28NM_HSIC_H2S_IMPCAL_DONE BIT(27) 370b56e9a7SVivek Gautam 380b56e9a7SVivek Gautam #define PHY_28NM_HSIC_CONNECT_INT BIT(1) 390b56e9a7SVivek Gautam #define PHY_28NM_HSIC_HS_READY_INT BIT(2) 400b56e9a7SVivek Gautam 410b56e9a7SVivek Gautam struct mv_hsic_phy { 420b56e9a7SVivek Gautam struct phy *phy; 430b56e9a7SVivek Gautam struct platform_device *pdev; 440b56e9a7SVivek Gautam void __iomem *base; 450b56e9a7SVivek Gautam struct clk *clk; 460b56e9a7SVivek Gautam }; 470b56e9a7SVivek Gautam 48f63602b1SChunfeng Yun static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms) 490b56e9a7SVivek Gautam { 50f63602b1SChunfeng Yun u32 val; 51f63602b1SChunfeng Yun 52f63602b1SChunfeng Yun return readl_poll_timeout(reg, val, ((val & mask) == mask), 53f63602b1SChunfeng Yun 1000, 1000 * ms); 540b56e9a7SVivek Gautam } 550b56e9a7SVivek Gautam 560b56e9a7SVivek Gautam static int mv_hsic_phy_init(struct phy *phy) 570b56e9a7SVivek Gautam { 580b56e9a7SVivek Gautam struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); 590b56e9a7SVivek Gautam struct platform_device *pdev = mv_phy->pdev; 600b56e9a7SVivek Gautam void __iomem *base = mv_phy->base; 61f63602b1SChunfeng Yun int ret; 620b56e9a7SVivek Gautam 630b56e9a7SVivek Gautam clk_prepare_enable(mv_phy->clk); 640b56e9a7SVivek Gautam 650b56e9a7SVivek Gautam /* Set reference clock */ 660b56e9a7SVivek Gautam writel(0x1 << PHY_28NM_HSIC_PLL_SELLPFR_SHIFT | 670b56e9a7SVivek Gautam 0xf0 << PHY_28NM_HSIC_PLL_FBDIV_SHIFT | 680b56e9a7SVivek Gautam 0xd << PHY_28NM_HSIC_PLL_REFDIV_SHIFT, 690b56e9a7SVivek Gautam base + PHY_28NM_HSIC_PLL_CTRL01); 700b56e9a7SVivek Gautam 710b56e9a7SVivek Gautam /* Turn on PLL */ 720b56e9a7SVivek Gautam writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) | 730b56e9a7SVivek Gautam PHY_28NM_HSIC_S2H_PU_PLL, 740b56e9a7SVivek Gautam base + PHY_28NM_HSIC_PLL_CTRL2); 750b56e9a7SVivek Gautam 760b56e9a7SVivek Gautam /* Make sure PHY PLL is locked */ 77f63602b1SChunfeng Yun ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2, 78f63602b1SChunfeng Yun PHY_28NM_HSIC_H2S_PLL_LOCK, 100); 79f63602b1SChunfeng Yun if (ret) { 800b56e9a7SVivek Gautam dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); 810b56e9a7SVivek Gautam clk_disable_unprepare(mv_phy->clk); 820b56e9a7SVivek Gautam } 830b56e9a7SVivek Gautam 84f63602b1SChunfeng Yun return ret; 850b56e9a7SVivek Gautam } 860b56e9a7SVivek Gautam 870b56e9a7SVivek Gautam static int mv_hsic_phy_power_on(struct phy *phy) 880b56e9a7SVivek Gautam { 890b56e9a7SVivek Gautam struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); 900b56e9a7SVivek Gautam struct platform_device *pdev = mv_phy->pdev; 910b56e9a7SVivek Gautam void __iomem *base = mv_phy->base; 920b56e9a7SVivek Gautam u32 reg; 93f63602b1SChunfeng Yun int ret; 940b56e9a7SVivek Gautam 950b56e9a7SVivek Gautam reg = readl(base + PHY_28NM_HSIC_CTRL); 960b56e9a7SVivek Gautam /* Avoid SE0 state when resume for some device will take it as reset */ 970b56e9a7SVivek Gautam reg &= ~S2H_DRV_SE0_4RESUME; 980b56e9a7SVivek Gautam reg |= PHY_28NM_HSIC_S2H_HSIC_EN; /* Enable HSIC PHY */ 990b56e9a7SVivek Gautam writel(reg, base + PHY_28NM_HSIC_CTRL); 1000b56e9a7SVivek Gautam 1010b56e9a7SVivek Gautam /* 1020b56e9a7SVivek Gautam * Calibration Timing 1030b56e9a7SVivek Gautam * ____________________________ 1040b56e9a7SVivek Gautam * CAL START ___| 1050b56e9a7SVivek Gautam * ____________________ 1060b56e9a7SVivek Gautam * CAL_DONE ___________| 1070b56e9a7SVivek Gautam * | 400us | 1080b56e9a7SVivek Gautam */ 1090b56e9a7SVivek Gautam 1100b56e9a7SVivek Gautam /* Make sure PHY Calibration is ready */ 111f63602b1SChunfeng Yun ret = wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL, 112f63602b1SChunfeng Yun PHY_28NM_HSIC_H2S_IMPCAL_DONE, 100); 113f63602b1SChunfeng Yun if (ret) { 1140b56e9a7SVivek Gautam dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS."); 115f63602b1SChunfeng Yun return ret; 1160b56e9a7SVivek Gautam } 1170b56e9a7SVivek Gautam 1180b56e9a7SVivek Gautam /* Waiting for HSIC connect int*/ 119f63602b1SChunfeng Yun ret = wait_for_reg(base + PHY_28NM_HSIC_INT, 120f63602b1SChunfeng Yun PHY_28NM_HSIC_CONNECT_INT, 200); 121f63602b1SChunfeng Yun if (ret) 1220b56e9a7SVivek Gautam dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout."); 1230b56e9a7SVivek Gautam 124f63602b1SChunfeng Yun return ret; 1250b56e9a7SVivek Gautam } 1260b56e9a7SVivek Gautam 1270b56e9a7SVivek Gautam static int mv_hsic_phy_power_off(struct phy *phy) 1280b56e9a7SVivek Gautam { 1290b56e9a7SVivek Gautam struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); 1300b56e9a7SVivek Gautam void __iomem *base = mv_phy->base; 1310b56e9a7SVivek Gautam 1320b56e9a7SVivek Gautam writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN, 1330b56e9a7SVivek Gautam base + PHY_28NM_HSIC_CTRL); 1340b56e9a7SVivek Gautam 1350b56e9a7SVivek Gautam return 0; 1360b56e9a7SVivek Gautam } 1370b56e9a7SVivek Gautam 1380b56e9a7SVivek Gautam static int mv_hsic_phy_exit(struct phy *phy) 1390b56e9a7SVivek Gautam { 1400b56e9a7SVivek Gautam struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); 1410b56e9a7SVivek Gautam void __iomem *base = mv_phy->base; 1420b56e9a7SVivek Gautam 1430b56e9a7SVivek Gautam /* Turn off PLL */ 1440b56e9a7SVivek Gautam writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) & 1450b56e9a7SVivek Gautam ~PHY_28NM_HSIC_S2H_PU_PLL, 1460b56e9a7SVivek Gautam base + PHY_28NM_HSIC_PLL_CTRL2); 1470b56e9a7SVivek Gautam 1480b56e9a7SVivek Gautam clk_disable_unprepare(mv_phy->clk); 1490b56e9a7SVivek Gautam return 0; 1500b56e9a7SVivek Gautam } 1510b56e9a7SVivek Gautam 1520b56e9a7SVivek Gautam 1530b56e9a7SVivek Gautam static const struct phy_ops hsic_ops = { 1540b56e9a7SVivek Gautam .init = mv_hsic_phy_init, 1550b56e9a7SVivek Gautam .power_on = mv_hsic_phy_power_on, 1560b56e9a7SVivek Gautam .power_off = mv_hsic_phy_power_off, 1570b56e9a7SVivek Gautam .exit = mv_hsic_phy_exit, 1580b56e9a7SVivek Gautam .owner = THIS_MODULE, 1590b56e9a7SVivek Gautam }; 1600b56e9a7SVivek Gautam 1610b56e9a7SVivek Gautam static int mv_hsic_phy_probe(struct platform_device *pdev) 1620b56e9a7SVivek Gautam { 1630b56e9a7SVivek Gautam struct phy_provider *phy_provider; 1640b56e9a7SVivek Gautam struct mv_hsic_phy *mv_phy; 1650b56e9a7SVivek Gautam 1660b56e9a7SVivek Gautam mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL); 1670b56e9a7SVivek Gautam if (!mv_phy) 1680b56e9a7SVivek Gautam return -ENOMEM; 1690b56e9a7SVivek Gautam 1700b56e9a7SVivek Gautam mv_phy->pdev = pdev; 1710b56e9a7SVivek Gautam 1720b56e9a7SVivek Gautam mv_phy->clk = devm_clk_get(&pdev->dev, NULL); 1730b56e9a7SVivek Gautam if (IS_ERR(mv_phy->clk)) { 1740b56e9a7SVivek Gautam dev_err(&pdev->dev, "failed to get clock.\n"); 1750b56e9a7SVivek Gautam return PTR_ERR(mv_phy->clk); 1760b56e9a7SVivek Gautam } 1770b56e9a7SVivek Gautam 178*ee55b501SChunfeng Yun mv_phy->base = devm_platform_ioremap_resource(pdev, 0); 1790b56e9a7SVivek Gautam if (IS_ERR(mv_phy->base)) 1800b56e9a7SVivek Gautam return PTR_ERR(mv_phy->base); 1810b56e9a7SVivek Gautam 1820b56e9a7SVivek Gautam mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &hsic_ops); 1830b56e9a7SVivek Gautam if (IS_ERR(mv_phy->phy)) 1840b56e9a7SVivek Gautam return PTR_ERR(mv_phy->phy); 1850b56e9a7SVivek Gautam 1860b56e9a7SVivek Gautam phy_set_drvdata(mv_phy->phy, mv_phy); 1870b56e9a7SVivek Gautam 1880b56e9a7SVivek Gautam phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); 1890b56e9a7SVivek Gautam return PTR_ERR_OR_ZERO(phy_provider); 1900b56e9a7SVivek Gautam } 1910b56e9a7SVivek Gautam 1920b56e9a7SVivek Gautam static const struct of_device_id mv_hsic_phy_dt_match[] = { 1930b56e9a7SVivek Gautam { .compatible = "marvell,pxa1928-hsic-phy", }, 1940b56e9a7SVivek Gautam {}, 1950b56e9a7SVivek Gautam }; 1960b56e9a7SVivek Gautam MODULE_DEVICE_TABLE(of, mv_hsic_phy_dt_match); 1970b56e9a7SVivek Gautam 1980b56e9a7SVivek Gautam static struct platform_driver mv_hsic_phy_driver = { 1990b56e9a7SVivek Gautam .probe = mv_hsic_phy_probe, 2000b56e9a7SVivek Gautam .driver = { 2010b56e9a7SVivek Gautam .name = "mv-hsic-phy", 2020b56e9a7SVivek Gautam .of_match_table = of_match_ptr(mv_hsic_phy_dt_match), 2030b56e9a7SVivek Gautam }, 2040b56e9a7SVivek Gautam }; 2050b56e9a7SVivek Gautam module_platform_driver(mv_hsic_phy_driver); 2060b56e9a7SVivek Gautam 2070b56e9a7SVivek Gautam MODULE_AUTHOR("Rob Herring <robh@kernel.org>"); 2080b56e9a7SVivek Gautam MODULE_DESCRIPTION("Marvell HSIC phy driver"); 2090b56e9a7SVivek Gautam MODULE_LICENSE("GPL v2"); 210