1 /* 2 * Copyright (C) 2017 Marvell 3 * 4 * Antoine Tenart <antoine.tenart@free-electrons.com> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 /* Relative to priv->base */ 20 #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000) 21 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1) 22 #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3) 23 #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7) 24 #define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11) 25 #define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12) 26 #define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14) 27 #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000) 28 #define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3) 29 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4) 30 #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5) 31 #define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6) 32 #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000) 33 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4) 34 #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000) 35 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2) 36 #define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3) 37 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4) 38 #define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000) 39 #define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0) 40 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5) 41 #define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000) 42 #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10) 43 #define MVEBU_COMPHY_IMP_CAL_TX_EXT_EN BIT(15) 44 #define MVEBU_COMPHY_DFE_RES(n) (0x81c + (n) * 0x1000) 45 #define MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL BIT(15) 46 #define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000) 47 #define MVEBU_COMPHY_COEF_DFE_EN BIT(14) 48 #define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15) 49 #define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000) 50 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1) 51 #define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7) 52 #define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000) 53 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0) 54 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3) 55 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(n) ((n) << 6) 56 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8) 57 #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10) 58 #define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11) 59 #define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000) 60 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0) 61 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4) 62 #define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000) 63 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1) 64 #define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000) 65 #define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15) 66 #define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000) 67 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5) 68 #define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000) 69 #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5) 70 #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10) 71 #define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000) 72 #define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11) 73 #define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12) 74 #define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000) 75 #define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7) 76 #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000) 77 #define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8) 78 #define MVEBU_SP_CALIB_SAMPLER_EN BIT(12) 79 #define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000) 80 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5) 81 #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10) 82 #define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000) 83 #define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2) 84 #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000) 85 #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7) 86 #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000) 87 #define MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN BIT(12) 88 #define MVEBU_COMPHY_DME(n) (0xa28 + (n) * 0x1000) 89 #define MVEBU_COMPHY_DME_ETH_MODE BIT(7) 90 #define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000) 91 #define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15) 92 #define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000) 93 #define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0) 94 #define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000) 95 #define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8) 96 #define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9) 97 #define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000) 98 #define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9) 99 #define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000) 100 #define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8) 101 #define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000) 102 #define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0) 103 #define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000) 104 #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0) 105 106 /* Relative to priv->regmap */ 107 #define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28) 108 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1) 109 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */ 110 #define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28) 111 #define MVEBU_COMPHY_CONF6_40B BIT(18) 112 #define MVEBU_COMPHY_SELECTOR 0x1140 113 #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4) 114 #define MVEBU_COMPHY_PIPE_SELECTOR 0x1144 115 #define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4) 116 117 #define MVEBU_COMPHY_LANES 6 118 #define MVEBU_COMPHY_PORTS 3 119 120 struct mvebu_comhy_conf { 121 enum phy_mode mode; 122 unsigned lane; 123 unsigned port; 124 u32 mux; 125 }; 126 127 #define MVEBU_COMPHY_CONF(_lane, _port, _mode, _mux) \ 128 { \ 129 .lane = _lane, \ 130 .port = _port, \ 131 .mode = _mode, \ 132 .mux = _mux, \ 133 } 134 135 static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = { 136 /* lane 0 */ 137 MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1), 138 /* lane 1 */ 139 MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1), 140 /* lane 2 */ 141 MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1), 142 MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1), 143 /* lane 3 */ 144 MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2), 145 /* lane 4 */ 146 MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2), 147 MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2), 148 MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1), 149 /* lane 5 */ 150 MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1), 151 }; 152 153 struct mvebu_comphy_priv { 154 void __iomem *base; 155 struct regmap *regmap; 156 struct device *dev; 157 int modes[MVEBU_COMPHY_LANES]; 158 }; 159 160 struct mvebu_comphy_lane { 161 struct mvebu_comphy_priv *priv; 162 unsigned id; 163 enum phy_mode mode; 164 int port; 165 }; 166 167 static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) 168 { 169 int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes); 170 171 /* Unused PHY mux value is 0x0 */ 172 if (mode == PHY_MODE_INVALID) 173 return 0; 174 175 for (i = 0; i < n; i++) { 176 if (mvebu_comphy_cp110_modes[i].lane == lane && 177 mvebu_comphy_cp110_modes[i].port == port && 178 mvebu_comphy_cp110_modes[i].mode == mode) 179 break; 180 } 181 182 if (i == n) 183 return -EINVAL; 184 185 return mvebu_comphy_cp110_modes[i].mux; 186 } 187 188 static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, 189 enum phy_mode mode) 190 { 191 struct mvebu_comphy_priv *priv = lane->priv; 192 u32 val; 193 194 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); 195 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; 196 val |= MVEBU_COMPHY_CONF1_PWRUP; 197 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); 198 199 /* Select baud rates and PLLs */ 200 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 201 val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL | 202 MVEBU_COMPHY_SERDES_CFG0_PU_RX | 203 MVEBU_COMPHY_SERDES_CFG0_PU_TX | 204 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS | 205 MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) | 206 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf)); 207 if (mode == PHY_MODE_10GKR) 208 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | 209 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe); 210 else if (mode == PHY_MODE_SGMII) 211 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | 212 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) | 213 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; 214 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 215 216 /* reset */ 217 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 218 val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | 219 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET | 220 MVEBU_COMPHY_SERDES_CFG1_RF_RESET); 221 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 222 223 /* de-assert reset */ 224 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 225 val |= MVEBU_COMPHY_SERDES_CFG1_RESET | 226 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET; 227 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 228 229 /* wait until clocks are ready */ 230 mdelay(1); 231 232 /* exlicitly disable 40B, the bits isn't clear on reset */ 233 regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val); 234 val &= ~MVEBU_COMPHY_CONF6_40B; 235 regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val); 236 237 /* refclk selection */ 238 val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); 239 val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; 240 if (mode == PHY_MODE_10GKR) 241 val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; 242 writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); 243 244 /* power and pll selection */ 245 val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); 246 val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) | 247 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7)); 248 val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) | 249 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x4); 250 writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); 251 252 val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); 253 val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7); 254 val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1); 255 writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); 256 } 257 258 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane, 259 enum phy_mode mode) 260 { 261 struct mvebu_comphy_priv *priv = lane->priv; 262 u32 val; 263 264 /* SERDES external config */ 265 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 266 val |= MVEBU_COMPHY_SERDES_CFG0_PU_PLL | 267 MVEBU_COMPHY_SERDES_CFG0_PU_RX | 268 MVEBU_COMPHY_SERDES_CFG0_PU_TX; 269 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 270 271 /* check rx/tx pll */ 272 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), 273 val, 274 val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | 275 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY), 276 1000, 150000); 277 if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | 278 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY))) 279 return -ETIMEDOUT; 280 281 /* rx init */ 282 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 283 val |= MVEBU_COMPHY_SERDES_CFG1_RX_INIT; 284 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 285 286 /* check rx */ 287 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), 288 val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT, 289 1000, 10000); 290 if (!(val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT)) 291 return -ETIMEDOUT; 292 293 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 294 val &= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT; 295 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 296 297 return 0; 298 } 299 300 static int mvebu_comphy_set_mode_sgmii(struct phy *phy) 301 { 302 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 303 struct mvebu_comphy_priv *priv = lane->priv; 304 u32 val; 305 306 mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_SGMII); 307 308 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 309 val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; 310 val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL; 311 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 312 313 val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 314 val &= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; 315 writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 316 317 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); 318 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; 319 val |= MVEBU_COMPHY_CONF1_PWRUP; 320 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); 321 322 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 323 val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf); 324 val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1); 325 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 326 327 return mvebu_comphy_init_plls(lane, PHY_MODE_SGMII); 328 } 329 330 static int mvebu_comphy_set_mode_10gkr(struct phy *phy) 331 { 332 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 333 struct mvebu_comphy_priv *priv = lane->priv; 334 u32 val; 335 336 mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_10GKR); 337 338 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 339 val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | 340 MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; 341 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 342 343 val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 344 val |= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; 345 writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 346 347 /* Speed divider */ 348 val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); 349 val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE; 350 writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); 351 352 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); 353 val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN; 354 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); 355 356 /* DFE resolution */ 357 val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); 358 val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; 359 writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); 360 361 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 362 val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) | 363 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf)); 364 val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) | 365 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xe); 366 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 367 368 val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); 369 val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf); 370 val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN; 371 writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); 372 373 val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); 374 val |= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) | 375 MVEBU_COMPHY_TX_SLEW_RATE_SLC(0x3f); 376 writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); 377 378 /* Impedance calibration */ 379 val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); 380 val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f); 381 val |= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) | 382 MVEBU_COMPHY_IMP_CAL_TX_EXT_EN; 383 writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); 384 385 val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); 386 val &= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf); 387 writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); 388 389 val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); 390 val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) | 391 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7) | 392 MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x3) | 393 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3)); 394 val |= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN | 395 MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x2) | 396 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x2) | 397 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x1) | 398 MVEBU_COMPHY_GEN1_S1_RX_DIV(0x3); 399 writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); 400 401 val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); 402 val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL); 403 writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); 404 405 val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); 406 val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3); 407 val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1); 408 writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); 409 410 val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); 411 val |= MVEBU_COMPHY_GEN1_S3_FBCK_SEL; 412 writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); 413 414 /* rx training timer */ 415 val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); 416 val &= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff); 417 val |= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13); 418 writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); 419 420 /* tx train peak to peak hold */ 421 val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); 422 val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD; 423 writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); 424 425 val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); 426 val &= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf); 427 val |= MVEBU_COMPHY_TX_PRESET_INDEX(0x2); /* preset coeff */ 428 writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); 429 430 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); 431 val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN; 432 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); 433 434 val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); 435 val |= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN | 436 MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11; 437 writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); 438 439 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); 440 val &= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff); 441 val |= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88); 442 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); 443 444 val = readl(priv->base + MVEBU_COMPHY_DME(lane->id)); 445 val |= MVEBU_COMPHY_DME_ETH_MODE; 446 writel(val, priv->base + MVEBU_COMPHY_DME(lane->id)); 447 448 val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); 449 val |= MVEBU_COMPHY_VDD_CAL0_CONT_MODE; 450 writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); 451 452 val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); 453 val &= ~MVEBU_SP_CALIB_SAMPLER(0x3); 454 val |= MVEBU_SP_CALIB_SAMPLER(0x3) | 455 MVEBU_SP_CALIB_SAMPLER_EN; 456 writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); 457 val &= ~MVEBU_SP_CALIB_SAMPLER_EN; 458 writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); 459 460 /* External rx regulator */ 461 val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); 462 val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f); 463 val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a); 464 writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); 465 466 return mvebu_comphy_init_plls(lane, PHY_MODE_10GKR); 467 } 468 469 static int mvebu_comphy_power_on(struct phy *phy) 470 { 471 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 472 struct mvebu_comphy_priv *priv = lane->priv; 473 int ret, mux; 474 u32 val; 475 476 mux = mvebu_comphy_get_mux(lane->id, lane->port, lane->mode); 477 if (mux < 0) 478 return -ENOTSUPP; 479 480 regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val); 481 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); 482 regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); 483 484 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); 485 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); 486 val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); 487 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); 488 489 switch (lane->mode) { 490 case PHY_MODE_SGMII: 491 ret = mvebu_comphy_set_mode_sgmii(phy); 492 break; 493 case PHY_MODE_10GKR: 494 ret = mvebu_comphy_set_mode_10gkr(phy); 495 break; 496 default: 497 return -ENOTSUPP; 498 } 499 500 /* digital reset */ 501 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 502 val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET; 503 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 504 505 return ret; 506 } 507 508 static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode) 509 { 510 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 511 512 if (mvebu_comphy_get_mux(lane->id, lane->port, mode) < 0) 513 return -EINVAL; 514 515 lane->mode = mode; 516 return 0; 517 } 518 519 static int mvebu_comphy_power_off(struct phy *phy) 520 { 521 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 522 struct mvebu_comphy_priv *priv = lane->priv; 523 u32 val; 524 525 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 526 val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | 527 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET | 528 MVEBU_COMPHY_SERDES_CFG1_RF_RESET); 529 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 530 531 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); 532 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); 533 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); 534 535 regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val); 536 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); 537 regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); 538 539 return 0; 540 } 541 542 static const struct phy_ops mvebu_comphy_ops = { 543 .power_on = mvebu_comphy_power_on, 544 .power_off = mvebu_comphy_power_off, 545 .set_mode = mvebu_comphy_set_mode, 546 .owner = THIS_MODULE, 547 }; 548 549 static struct phy *mvebu_comphy_xlate(struct device *dev, 550 struct of_phandle_args *args) 551 { 552 struct mvebu_comphy_lane *lane; 553 struct phy *phy; 554 555 if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS)) 556 return ERR_PTR(-EINVAL); 557 558 phy = of_phy_simple_xlate(dev, args); 559 if (IS_ERR(phy)) 560 return phy; 561 562 lane = phy_get_drvdata(phy); 563 if (lane->port >= 0) 564 return ERR_PTR(-EBUSY); 565 lane->port = args->args[0]; 566 567 return phy; 568 } 569 570 static int mvebu_comphy_probe(struct platform_device *pdev) 571 { 572 struct mvebu_comphy_priv *priv; 573 struct phy_provider *provider; 574 struct device_node *child; 575 struct resource *res; 576 577 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 578 if (!priv) 579 return -ENOMEM; 580 581 priv->dev = &pdev->dev; 582 priv->regmap = 583 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 584 "marvell,system-controller"); 585 if (IS_ERR(priv->regmap)) 586 return PTR_ERR(priv->regmap); 587 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 588 priv->base = devm_ioremap_resource(&pdev->dev, res); 589 if (IS_ERR(priv->base)) 590 return PTR_ERR(priv->base); 591 592 for_each_available_child_of_node(pdev->dev.of_node, child) { 593 struct mvebu_comphy_lane *lane; 594 struct phy *phy; 595 int ret; 596 u32 val; 597 598 ret = of_property_read_u32(child, "reg", &val); 599 if (ret < 0) { 600 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", 601 ret); 602 continue; 603 } 604 605 if (val >= MVEBU_COMPHY_LANES) { 606 dev_err(&pdev->dev, "invalid 'reg' property\n"); 607 continue; 608 } 609 610 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); 611 if (!lane) 612 return -ENOMEM; 613 614 phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops); 615 if (IS_ERR(phy)) 616 return PTR_ERR(phy); 617 618 lane->priv = priv; 619 lane->mode = PHY_MODE_INVALID; 620 lane->id = val; 621 lane->port = -1; 622 phy_set_drvdata(phy, lane); 623 624 /* 625 * Once all modes are supported in this driver we should call 626 * mvebu_comphy_power_off(phy) here to avoid relying on the 627 * bootloader/firmware configuration. 628 */ 629 } 630 631 dev_set_drvdata(&pdev->dev, priv); 632 provider = devm_of_phy_provider_register(&pdev->dev, 633 mvebu_comphy_xlate); 634 return PTR_ERR_OR_ZERO(provider); 635 } 636 637 static const struct of_device_id mvebu_comphy_of_match_table[] = { 638 { .compatible = "marvell,comphy-cp110" }, 639 { }, 640 }; 641 MODULE_DEVICE_TABLE(of, mvebu_comphy_of_match_table); 642 643 static struct platform_driver mvebu_comphy_driver = { 644 .probe = mvebu_comphy_probe, 645 .driver = { 646 .name = "mvebu-comphy", 647 .of_match_table = mvebu_comphy_of_match_table, 648 }, 649 }; 650 module_platform_driver(mvebu_comphy_driver); 651 652 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>"); 653 MODULE_DESCRIPTION("Common PHY driver for mvebu SoCs"); 654 MODULE_LICENSE("GPL v2"); 655