1 /* 2 * Copyright (C) 2017 Marvell 3 * 4 * Antoine Tenart <antoine.tenart@free-electrons.com> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 /* Relative to priv->base */ 20 #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000) 21 #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1) 22 #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3) 23 #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7) 24 #define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11) 25 #define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12) 26 #define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14) 27 #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000) 28 #define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3) 29 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4) 30 #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5) 31 #define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6) 32 #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000) 33 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4) 34 #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000) 35 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2) 36 #define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3) 37 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4) 38 #define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000) 39 #define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0) 40 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5) 41 #define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000) 42 #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10) 43 #define MVEBU_COMPHY_IMP_CAL_TX_EXT_EN BIT(15) 44 #define MVEBU_COMPHY_DFE_RES(n) (0x81c + (n) * 0x1000) 45 #define MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL BIT(15) 46 #define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000) 47 #define MVEBU_COMPHY_COEF_DFE_EN BIT(14) 48 #define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15) 49 #define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000) 50 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1) 51 #define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7) 52 #define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000) 53 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0) 54 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3) 55 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(n) ((n) << 6) 56 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8) 57 #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10) 58 #define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11) 59 #define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000) 60 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0) 61 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4) 62 #define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000) 63 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1) 64 #define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000) 65 #define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15) 66 #define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000) 67 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5) 68 #define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000) 69 #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5) 70 #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10) 71 #define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000) 72 #define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11) 73 #define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12) 74 #define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000) 75 #define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7) 76 #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000) 77 #define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8) 78 #define MVEBU_SP_CALIB_SAMPLER_EN BIT(12) 79 #define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000) 80 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5) 81 #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10) 82 #define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000) 83 #define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2) 84 #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000) 85 #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7) 86 #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000) 87 #define MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN BIT(12) 88 #define MVEBU_COMPHY_DME(n) (0xa28 + (n) * 0x1000) 89 #define MVEBU_COMPHY_DME_ETH_MODE BIT(7) 90 #define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000) 91 #define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15) 92 #define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000) 93 #define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0) 94 #define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000) 95 #define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8) 96 #define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9) 97 #define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000) 98 #define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9) 99 #define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000) 100 #define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8) 101 #define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000) 102 #define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0) 103 #define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000) 104 #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0) 105 106 /* Relative to priv->regmap */ 107 #define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28) 108 #define MVEBU_COMPHY_CONF1_PWRUP BIT(1) 109 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */ 110 #define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28) 111 #define MVEBU_COMPHY_CONF6_40B BIT(18) 112 #define MVEBU_COMPHY_SELECTOR 0x1140 113 #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4) 114 115 #define MVEBU_COMPHY_LANES 6 116 #define MVEBU_COMPHY_PORTS 3 117 118 struct mvebu_comhy_conf { 119 enum phy_mode mode; 120 unsigned lane; 121 unsigned port; 122 u32 mux; 123 }; 124 125 #define MVEBU_COMPHY_CONF(_lane, _port, _mode, _mux) \ 126 { \ 127 .lane = _lane, \ 128 .port = _port, \ 129 .mode = _mode, \ 130 .mux = _mux, \ 131 } 132 133 static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = { 134 /* lane 0 */ 135 MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1), 136 /* lane 1 */ 137 MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1), 138 /* lane 2 */ 139 MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1), 140 MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1), 141 /* lane 3 */ 142 MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2), 143 /* lane 4 */ 144 MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2), 145 MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2), 146 MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1), 147 /* lane 5 */ 148 MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1), 149 }; 150 151 struct mvebu_comphy_priv { 152 void __iomem *base; 153 struct regmap *regmap; 154 struct device *dev; 155 int modes[MVEBU_COMPHY_LANES]; 156 }; 157 158 struct mvebu_comphy_lane { 159 struct mvebu_comphy_priv *priv; 160 unsigned id; 161 enum phy_mode mode; 162 int port; 163 }; 164 165 static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) 166 { 167 int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes); 168 169 /* Unused PHY mux value is 0x0 */ 170 if (mode == PHY_MODE_INVALID) 171 return 0; 172 173 for (i = 0; i < n; i++) { 174 if (mvebu_comphy_cp110_modes[i].lane == lane && 175 mvebu_comphy_cp110_modes[i].port == port && 176 mvebu_comphy_cp110_modes[i].mode == mode) 177 break; 178 } 179 180 if (i == n) 181 return -EINVAL; 182 183 return mvebu_comphy_cp110_modes[i].mux; 184 } 185 186 static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, 187 enum phy_mode mode) 188 { 189 struct mvebu_comphy_priv *priv = lane->priv; 190 u32 val; 191 192 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); 193 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; 194 val |= MVEBU_COMPHY_CONF1_PWRUP; 195 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); 196 197 /* Select baud rates and PLLs */ 198 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 199 val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL | 200 MVEBU_COMPHY_SERDES_CFG0_PU_RX | 201 MVEBU_COMPHY_SERDES_CFG0_PU_TX | 202 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS | 203 MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) | 204 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf)); 205 if (mode == PHY_MODE_10GKR) 206 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | 207 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe); 208 else if (mode == PHY_MODE_SGMII) 209 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | 210 MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) | 211 MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; 212 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 213 214 /* reset */ 215 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 216 val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | 217 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET | 218 MVEBU_COMPHY_SERDES_CFG1_RF_RESET); 219 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 220 221 /* de-assert reset */ 222 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 223 val |= MVEBU_COMPHY_SERDES_CFG1_RESET | 224 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET; 225 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 226 227 /* wait until clocks are ready */ 228 mdelay(1); 229 230 /* exlicitly disable 40B, the bits isn't clear on reset */ 231 regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val); 232 val &= ~MVEBU_COMPHY_CONF6_40B; 233 regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val); 234 235 /* refclk selection */ 236 val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); 237 val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; 238 if (mode == PHY_MODE_10GKR) 239 val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; 240 writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); 241 242 /* power and pll selection */ 243 val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); 244 val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) | 245 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7)); 246 val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) | 247 MVEBU_COMPHY_PWRPLL_PHY_MODE(0x4); 248 writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); 249 250 val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); 251 val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7); 252 val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1); 253 writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); 254 } 255 256 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane, 257 enum phy_mode mode) 258 { 259 struct mvebu_comphy_priv *priv = lane->priv; 260 u32 val; 261 262 /* SERDES external config */ 263 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 264 val |= MVEBU_COMPHY_SERDES_CFG0_PU_PLL | 265 MVEBU_COMPHY_SERDES_CFG0_PU_RX | 266 MVEBU_COMPHY_SERDES_CFG0_PU_TX; 267 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); 268 269 /* check rx/tx pll */ 270 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), 271 val, 272 val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | 273 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY), 274 1000, 150000); 275 if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | 276 MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY))) 277 return -ETIMEDOUT; 278 279 /* rx init */ 280 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 281 val |= MVEBU_COMPHY_SERDES_CFG1_RX_INIT; 282 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 283 284 /* check rx */ 285 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), 286 val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT, 287 1000, 10000); 288 if (!(val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT)) 289 return -ETIMEDOUT; 290 291 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 292 val &= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT; 293 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 294 295 return 0; 296 } 297 298 static int mvebu_comphy_set_mode_sgmii(struct phy *phy) 299 { 300 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 301 struct mvebu_comphy_priv *priv = lane->priv; 302 u32 val; 303 304 mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_SGMII); 305 306 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 307 val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; 308 val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL; 309 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 310 311 val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 312 val &= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; 313 writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 314 315 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); 316 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; 317 val |= MVEBU_COMPHY_CONF1_PWRUP; 318 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); 319 320 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 321 val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf); 322 val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1); 323 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 324 325 return mvebu_comphy_init_plls(lane, PHY_MODE_SGMII); 326 } 327 328 static int mvebu_comphy_set_mode_10gkr(struct phy *phy) 329 { 330 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 331 struct mvebu_comphy_priv *priv = lane->priv; 332 u32 val; 333 334 mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_10GKR); 335 336 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 337 val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | 338 MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; 339 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); 340 341 val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 342 val |= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; 343 writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); 344 345 /* Speed divider */ 346 val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); 347 val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE; 348 writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); 349 350 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); 351 val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN; 352 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); 353 354 /* DFE resolution */ 355 val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); 356 val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; 357 writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); 358 359 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 360 val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) | 361 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf)); 362 val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) | 363 MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xe); 364 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); 365 366 val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); 367 val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf); 368 val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN; 369 writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); 370 371 val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); 372 val |= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) | 373 MVEBU_COMPHY_TX_SLEW_RATE_SLC(0x3f); 374 writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); 375 376 /* Impedance calibration */ 377 val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); 378 val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f); 379 val |= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) | 380 MVEBU_COMPHY_IMP_CAL_TX_EXT_EN; 381 writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); 382 383 val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); 384 val &= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf); 385 writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); 386 387 val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); 388 val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) | 389 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7) | 390 MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x3) | 391 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3)); 392 val |= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN | 393 MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x2) | 394 MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x2) | 395 MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x1) | 396 MVEBU_COMPHY_GEN1_S1_RX_DIV(0x3); 397 writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); 398 399 val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); 400 val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL); 401 writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); 402 403 val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); 404 val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3); 405 val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1); 406 writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); 407 408 val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); 409 val |= MVEBU_COMPHY_GEN1_S3_FBCK_SEL; 410 writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); 411 412 /* rx training timer */ 413 val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); 414 val &= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff); 415 val |= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13); 416 writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); 417 418 /* tx train peak to peak hold */ 419 val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); 420 val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD; 421 writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); 422 423 val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); 424 val &= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf); 425 val |= MVEBU_COMPHY_TX_PRESET_INDEX(0x2); /* preset coeff */ 426 writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); 427 428 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); 429 val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN; 430 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); 431 432 val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); 433 val |= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN | 434 MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11; 435 writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); 436 437 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); 438 val &= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff); 439 val |= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88); 440 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); 441 442 val = readl(priv->base + MVEBU_COMPHY_DME(lane->id)); 443 val |= MVEBU_COMPHY_DME_ETH_MODE; 444 writel(val, priv->base + MVEBU_COMPHY_DME(lane->id)); 445 446 val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); 447 val |= MVEBU_COMPHY_VDD_CAL0_CONT_MODE; 448 writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); 449 450 val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); 451 val &= ~MVEBU_SP_CALIB_SAMPLER(0x3); 452 val |= MVEBU_SP_CALIB_SAMPLER(0x3) | 453 MVEBU_SP_CALIB_SAMPLER_EN; 454 writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); 455 val &= ~MVEBU_SP_CALIB_SAMPLER_EN; 456 writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); 457 458 /* External rx regulator */ 459 val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); 460 val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f); 461 val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a); 462 writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); 463 464 return mvebu_comphy_init_plls(lane, PHY_MODE_10GKR); 465 } 466 467 static int mvebu_comphy_power_on(struct phy *phy) 468 { 469 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 470 struct mvebu_comphy_priv *priv = lane->priv; 471 int ret; 472 u32 mux, val; 473 474 mux = mvebu_comphy_get_mux(lane->id, lane->port, lane->mode); 475 if (mux < 0) 476 return -ENOTSUPP; 477 478 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); 479 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); 480 val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); 481 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); 482 483 switch (lane->mode) { 484 case PHY_MODE_SGMII: 485 ret = mvebu_comphy_set_mode_sgmii(phy); 486 break; 487 case PHY_MODE_10GKR: 488 ret = mvebu_comphy_set_mode_10gkr(phy); 489 break; 490 default: 491 return -ENOTSUPP; 492 } 493 494 /* digital reset */ 495 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 496 val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET; 497 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 498 499 return ret; 500 } 501 502 static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode) 503 { 504 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 505 506 if (mvebu_comphy_get_mux(lane->id, lane->port, mode) < 0) 507 return -EINVAL; 508 509 lane->mode = mode; 510 return 0; 511 } 512 513 static int mvebu_comphy_power_off(struct phy *phy) 514 { 515 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); 516 struct mvebu_comphy_priv *priv = lane->priv; 517 u32 val; 518 519 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 520 val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | 521 MVEBU_COMPHY_SERDES_CFG1_CORE_RESET | 522 MVEBU_COMPHY_SERDES_CFG1_RF_RESET); 523 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); 524 525 regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); 526 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); 527 regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); 528 529 return 0; 530 } 531 532 static const struct phy_ops mvebu_comphy_ops = { 533 .power_on = mvebu_comphy_power_on, 534 .power_off = mvebu_comphy_power_off, 535 .set_mode = mvebu_comphy_set_mode, 536 .owner = THIS_MODULE, 537 }; 538 539 static struct phy *mvebu_comphy_xlate(struct device *dev, 540 struct of_phandle_args *args) 541 { 542 struct mvebu_comphy_lane *lane; 543 struct phy *phy; 544 545 if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS)) 546 return ERR_PTR(-EINVAL); 547 548 phy = of_phy_simple_xlate(dev, args); 549 if (IS_ERR(phy)) 550 return phy; 551 552 lane = phy_get_drvdata(phy); 553 if (lane->port >= 0) 554 return ERR_PTR(-EBUSY); 555 lane->port = args->args[0]; 556 557 return phy; 558 } 559 560 static int mvebu_comphy_probe(struct platform_device *pdev) 561 { 562 struct mvebu_comphy_priv *priv; 563 struct phy_provider *provider; 564 struct device_node *child; 565 struct resource *res; 566 567 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 568 if (!priv) 569 return -ENOMEM; 570 571 priv->dev = &pdev->dev; 572 priv->regmap = 573 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 574 "marvell,system-controller"); 575 if (IS_ERR(priv->regmap)) 576 return PTR_ERR(priv->regmap); 577 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 578 priv->base = devm_ioremap_resource(&pdev->dev, res); 579 if (!priv->base) 580 return -ENOMEM; 581 582 for_each_available_child_of_node(pdev->dev.of_node, child) { 583 struct mvebu_comphy_lane *lane; 584 struct phy *phy; 585 int ret; 586 u32 val; 587 588 ret = of_property_read_u32(child, "reg", &val); 589 if (ret < 0) { 590 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", 591 ret); 592 continue; 593 } 594 595 if (val >= MVEBU_COMPHY_LANES) { 596 dev_err(&pdev->dev, "invalid 'reg' property\n"); 597 continue; 598 } 599 600 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); 601 if (!lane) 602 return -ENOMEM; 603 604 phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops); 605 if (IS_ERR(phy)) 606 return PTR_ERR(phy); 607 608 lane->priv = priv; 609 lane->mode = PHY_MODE_INVALID; 610 lane->id = val; 611 lane->port = -1; 612 phy_set_drvdata(phy, lane); 613 614 /* 615 * Once all modes are supported in this driver we should call 616 * mvebu_comphy_power_off(phy) here to avoid relying on the 617 * bootloader/firmware configuration. 618 */ 619 } 620 621 dev_set_drvdata(&pdev->dev, priv); 622 provider = devm_of_phy_provider_register(&pdev->dev, 623 mvebu_comphy_xlate); 624 return PTR_ERR_OR_ZERO(provider); 625 } 626 627 static const struct of_device_id mvebu_comphy_of_match_table[] = { 628 { .compatible = "marvell,comphy-cp110" }, 629 { }, 630 }; 631 MODULE_DEVICE_TABLE(of, mvebu_comphy_of_match_table); 632 633 static struct platform_driver mvebu_comphy_driver = { 634 .probe = mvebu_comphy_probe, 635 .driver = { 636 .name = "mvebu-comphy", 637 .of_match_table = mvebu_comphy_of_match_table, 638 }, 639 }; 640 module_platform_driver(mvebu_comphy_driver); 641 642 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>"); 643 MODULE_DESCRIPTION("Common PHY driver for mvebu SoCs"); 644 MODULE_LICENSE("GPL v2"); 645