19695375aSMiquel Raynal // SPDX-License-Identifier: GPL-2.0 29695375aSMiquel Raynal /* 39695375aSMiquel Raynal * Copyright (C) 2018 Marvell 49695375aSMiquel Raynal * 59695375aSMiquel Raynal * Authors: 69695375aSMiquel Raynal * Evan Wang <xswang@marvell.com> 79695375aSMiquel Raynal * Miquèl Raynal <miquel.raynal@bootlin.com> 8*93433708SPali Rohár * Pali Rohár <pali@kernel.org> 9*93433708SPali Rohár * Marek Behún <kabel@kernel.org> 109695375aSMiquel Raynal * 119695375aSMiquel Raynal * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart. 12*93433708SPali Rohár * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org> 13*93433708SPali Rohár * and Marek Behún <kabel@kernel.org>. 149695375aSMiquel Raynal */ 159695375aSMiquel Raynal 16*93433708SPali Rohár #include <linux/bitfield.h> 17*93433708SPali Rohár #include <linux/clk.h> 189695375aSMiquel Raynal #include <linux/io.h> 199695375aSMiquel Raynal #include <linux/iopoll.h> 209695375aSMiquel Raynal #include <linux/mfd/syscon.h> 219695375aSMiquel Raynal #include <linux/module.h> 229695375aSMiquel Raynal #include <linux/phy.h> 239695375aSMiquel Raynal #include <linux/phy/phy.h> 249695375aSMiquel Raynal #include <linux/platform_device.h> 25*93433708SPali Rohár #include <linux/spinlock.h> 269695375aSMiquel Raynal 27*93433708SPali Rohár #define PLL_SET_DELAY_US 600 28*93433708SPali Rohár #define COMPHY_PLL_SLEEP 1000 29*93433708SPali Rohár #define COMPHY_PLL_TIMEOUT 150000 309695375aSMiquel Raynal 31*93433708SPali Rohár /* Comphy lane2 indirect access register offset */ 32*93433708SPali Rohár #define COMPHY_LANE2_INDIR_ADDR 0x0 33*93433708SPali Rohár #define COMPHY_LANE2_INDIR_DATA 0x4 349695375aSMiquel Raynal 35*93433708SPali Rohár /* SATA and USB3 PHY offset compared to SATA PHY */ 36*93433708SPali Rohár #define COMPHY_LANE2_REGS_BASE 0x200 379695375aSMiquel Raynal 38*93433708SPali Rohár /* 39*93433708SPali Rohár * When accessing common PHY lane registers directly, we need to shift by 1, 40*93433708SPali Rohár * since the registers are 16-bit. 41*93433708SPali Rohár */ 42*93433708SPali Rohár #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1) 439695375aSMiquel Raynal 44*93433708SPali Rohár /* COMPHY registers */ 45*93433708SPali Rohár #define COMPHY_POWER_PLL_CTRL 0x01 46*93433708SPali Rohár #define PU_IVREF_BIT BIT(15) 47*93433708SPali Rohár #define PU_PLL_BIT BIT(14) 48*93433708SPali Rohár #define PU_RX_BIT BIT(13) 49*93433708SPali Rohár #define PU_TX_BIT BIT(12) 50*93433708SPali Rohár #define PU_TX_INTP_BIT BIT(11) 51*93433708SPali Rohár #define PU_DFE_BIT BIT(10) 52*93433708SPali Rohár #define RESET_DTL_RX_BIT BIT(9) 53*93433708SPali Rohár #define PLL_LOCK_BIT BIT(8) 54*93433708SPali Rohár #define REF_FREF_SEL_MASK GENMASK(4, 0) 55*93433708SPali Rohár #define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1) 56*93433708SPali Rohár #define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) 57*93433708SPali Rohár #define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4) 58*93433708SPali Rohár #define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2) 59*93433708SPali Rohár #define REF_FREF_SEL_PCIE_USB3_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) 60*93433708SPali Rohár #define COMPHY_MODE_MASK GENMASK(7, 5) 61*93433708SPali Rohár #define COMPHY_MODE_SATA FIELD_PREP(COMPHY_MODE_MASK, 0x0) 62*93433708SPali Rohár #define COMPHY_MODE_PCIE FIELD_PREP(COMPHY_MODE_MASK, 0x3) 63*93433708SPali Rohár #define COMPHY_MODE_SERDES FIELD_PREP(COMPHY_MODE_MASK, 0x4) 64*93433708SPali Rohár #define COMPHY_MODE_USB3 FIELD_PREP(COMPHY_MODE_MASK, 0x5) 65*93433708SPali Rohár 66*93433708SPali Rohár #define COMPHY_KVCO_CAL_CTRL 0x02 67*93433708SPali Rohár #define USE_MAX_PLL_RATE_BIT BIT(12) 68*93433708SPali Rohár #define SPEED_PLL_MASK GENMASK(7, 2) 69*93433708SPali Rohár #define SPEED_PLL_VALUE_16 FIELD_PREP(SPEED_PLL_MASK, 0x10) 70*93433708SPali Rohár 71*93433708SPali Rohár #define COMPHY_DIG_LOOPBACK_EN 0x23 72*93433708SPali Rohár #define SEL_DATA_WIDTH_MASK GENMASK(11, 10) 73*93433708SPali Rohár #define DATA_WIDTH_10BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0) 74*93433708SPali Rohár #define DATA_WIDTH_20BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1) 75*93433708SPali Rohár #define DATA_WIDTH_40BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2) 76*93433708SPali Rohár #define PLL_READY_TX_BIT BIT(4) 77*93433708SPali Rohár 78*93433708SPali Rohár #define COMPHY_SYNC_PATTERN 0x24 79*93433708SPali Rohár #define TXD_INVERT_BIT BIT(10) 80*93433708SPali Rohár #define RXD_INVERT_BIT BIT(11) 81*93433708SPali Rohár 82*93433708SPali Rohár #define COMPHY_SYNC_MASK_GEN 0x25 83*93433708SPali Rohár #define PHY_GEN_MAX_MASK GENMASK(11, 10) 84*93433708SPali Rohár #define PHY_GEN_MAX_USB3_5G FIELD_PREP(PHY_GEN_MAX_MASK, 0x1) 85*93433708SPali Rohár 86*93433708SPali Rohár #define COMPHY_ISOLATION_CTRL 0x26 87*93433708SPali Rohár #define PHY_ISOLATE_MODE BIT(15) 88*93433708SPali Rohár 89*93433708SPali Rohár #define COMPHY_GEN2_SET2 0x3e 90*93433708SPali Rohár #define GS2_TX_SSC_AMP_MASK GENMASK(15, 9) 91*93433708SPali Rohár #define GS2_TX_SSC_AMP_4128 FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20) 92*93433708SPali Rohár #define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7) 93*93433708SPali Rohár #define GS2_VREG_RXTX_MAS_ISET_60U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 94*93433708SPali Rohár 0x0) 95*93433708SPali Rohár #define GS2_VREG_RXTX_MAS_ISET_80U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 96*93433708SPali Rohár 0x1) 97*93433708SPali Rohár #define GS2_VREG_RXTX_MAS_ISET_100U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 98*93433708SPali Rohár 0x2) 99*93433708SPali Rohár #define GS2_VREG_RXTX_MAS_ISET_120U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 100*93433708SPali Rohár 0x3) 101*93433708SPali Rohár #define GS2_RSVD_6_0_MASK GENMASK(6, 0) 102*93433708SPali Rohár 103*93433708SPali Rohár #define COMPHY_GEN3_SET2 0x3f 104*93433708SPali Rohár 105*93433708SPali Rohár #define COMPHY_IDLE_SYNC_EN 0x48 106*93433708SPali Rohár #define IDLE_SYNC_EN BIT(12) 107*93433708SPali Rohár 108*93433708SPali Rohár #define COMPHY_MISC_CTRL0 0x4F 109*93433708SPali Rohár #define CLK100M_125M_EN BIT(4) 110*93433708SPali Rohár #define TXDCLK_2X_SEL BIT(6) 111*93433708SPali Rohár #define CLK500M_EN BIT(7) 112*93433708SPali Rohár #define PHY_REF_CLK_SEL BIT(10) 113*93433708SPali Rohár 114*93433708SPali Rohár #define COMPHY_SFT_RESET 0x52 115*93433708SPali Rohár #define SFT_RST BIT(9) 116*93433708SPali Rohár #define SFT_RST_NO_REG BIT(10) 117*93433708SPali Rohár 118*93433708SPali Rohár #define COMPHY_MISC_CTRL1 0x73 119*93433708SPali Rohár #define SEL_BITS_PCIE_FORCE BIT(15) 120*93433708SPali Rohár 121*93433708SPali Rohár #define COMPHY_GEN2_SET3 0x112 122*93433708SPali Rohár #define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0) 123*93433708SPali Rohár #define GS3_FFE_CAP_SEL_VALUE FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF) 124*93433708SPali Rohár 125*93433708SPali Rohár /* PIPE registers */ 126*93433708SPali Rohár #define COMPHY_PIPE_LANE_CFG0 0x180 127*93433708SPali Rohár #define PRD_TXDEEMPH0_MASK BIT(0) 128*93433708SPali Rohár #define PRD_TXMARGIN_MASK GENMASK(3, 1) 129*93433708SPali Rohár #define PRD_TXSWING_MASK BIT(4) 130*93433708SPali Rohár #define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5) 131*93433708SPali Rohár 132*93433708SPali Rohár #define COMPHY_PIPE_LANE_CFG1 0x181 133*93433708SPali Rohár #define PRD_TXDEEMPH1_MASK BIT(15) 134*93433708SPali Rohár #define USE_MAX_PLL_RATE_EN BIT(9) 135*93433708SPali Rohár #define TX_DET_RX_MODE BIT(6) 136*93433708SPali Rohár #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3) 137*93433708SPali Rohár #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2) 138*93433708SPali Rohár #define TX_ELEC_IDLE_MODE_EN BIT(0) 139*93433708SPali Rohár 140*93433708SPali Rohár #define COMPHY_PIPE_LANE_STAT1 0x183 141*93433708SPali Rohár #define TXDCLK_PCLK_EN BIT(0) 142*93433708SPali Rohár 143*93433708SPali Rohár #define COMPHY_PIPE_LANE_CFG4 0x188 144*93433708SPali Rohár #define SPREAD_SPECTRUM_CLK_EN BIT(7) 145*93433708SPali Rohár 146*93433708SPali Rohár #define COMPHY_PIPE_RST_CLK_CTRL 0x1C1 147*93433708SPali Rohár #define PIPE_SOFT_RESET BIT(0) 148*93433708SPali Rohár #define PIPE_REG_RESET BIT(1) 149*93433708SPali Rohár #define MODE_CORE_CLK_FREQ_SEL BIT(9) 150*93433708SPali Rohár #define MODE_PIPE_WIDTH_32 BIT(3) 151*93433708SPali Rohár #define MODE_REFDIV_MASK GENMASK(5, 4) 152*93433708SPali Rohár #define MODE_REFDIV_BY_4 FIELD_PREP(MODE_REFDIV_MASK, 0x2) 153*93433708SPali Rohár 154*93433708SPali Rohár #define COMPHY_PIPE_TEST_MODE_CTRL 0x1C2 155*93433708SPali Rohár #define MODE_MARGIN_OVERRIDE BIT(2) 156*93433708SPali Rohár 157*93433708SPali Rohár #define COMPHY_PIPE_CLK_SRC_LO 0x1C3 158*93433708SPali Rohár #define MODE_CLK_SRC BIT(0) 159*93433708SPali Rohár #define BUNDLE_PERIOD_SEL BIT(1) 160*93433708SPali Rohár #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2) 161*93433708SPali Rohár #define BUNDLE_SAMPLE_CTRL BIT(4) 162*93433708SPali Rohár #define PLL_READY_DLY_MASK GENMASK(7, 5) 163*93433708SPali Rohár #define CFG_SEL_20B BIT(15) 164*93433708SPali Rohár 165*93433708SPali Rohár #define COMPHY_PIPE_PWR_MGM_TIM1 0x1D0 166*93433708SPali Rohár #define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12) 167*93433708SPali Rohár #define CFG_PM_RXDEN_WAIT_MASK GENMASK(11, 8) 168*93433708SPali Rohár #define CFG_PM_RXDEN_WAIT_1_UNIT FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1) 169*93433708SPali Rohár #define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0) 170*93433708SPali Rohár #define CFG_PM_RXDLOZ_WAIT_7_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7) 171*93433708SPali Rohár #define CFG_PM_RXDLOZ_WAIT_12_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC) 172*93433708SPali Rohár 173*93433708SPali Rohár /* 174*93433708SPali Rohár * This register is not from PHY lane register space. It only exists in the 175*93433708SPali Rohár * indirect register space, before the actual PHY lane 2 registers. So the 176*93433708SPali Rohár * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE. 177*93433708SPali Rohár * It is used only for SATA PHY initialization. 178*93433708SPali Rohár */ 179*93433708SPali Rohár #define COMPHY_RESERVED_REG 0x0E 180*93433708SPali Rohár #define PHYCTRL_FRM_PIN_BIT BIT(13) 181*93433708SPali Rohár 182*93433708SPali Rohár /* South Bridge PHY Configuration Registers */ 183*93433708SPali Rohár #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) 184*93433708SPali Rohár 185*93433708SPali Rohár /* 186*93433708SPali Rohár * lane0: USB3/GbE1 PHY Configuration 1 187*93433708SPali Rohár * lane1: PCIe/GbE0 PHY Configuration 1 188*93433708SPali Rohár * (used only by SGMII code) 189*93433708SPali Rohár */ 190*93433708SPali Rohár #define COMPHY_PHY_CFG1 0x0 191*93433708SPali Rohár #define PIN_PU_IVREF_BIT BIT(1) 192*93433708SPali Rohár #define PIN_RESET_CORE_BIT BIT(11) 193*93433708SPali Rohár #define PIN_RESET_COMPHY_BIT BIT(12) 194*93433708SPali Rohár #define PIN_PU_PLL_BIT BIT(16) 195*93433708SPali Rohár #define PIN_PU_RX_BIT BIT(17) 196*93433708SPali Rohár #define PIN_PU_TX_BIT BIT(18) 197*93433708SPali Rohár #define PIN_TX_IDLE_BIT BIT(19) 198*93433708SPali Rohár #define GEN_RX_SEL_MASK GENMASK(25, 22) 199*93433708SPali Rohár #define GEN_RX_SEL_VALUE(val) FIELD_PREP(GEN_RX_SEL_MASK, (val)) 200*93433708SPali Rohár #define GEN_TX_SEL_MASK GENMASK(29, 26) 201*93433708SPali Rohár #define GEN_TX_SEL_VALUE(val) FIELD_PREP(GEN_TX_SEL_MASK, (val)) 202*93433708SPali Rohár #define SERDES_SPEED_1_25_G 0x6 203*93433708SPali Rohár #define SERDES_SPEED_3_125_G 0x8 204*93433708SPali Rohár #define PHY_RX_INIT_BIT BIT(30) 205*93433708SPali Rohár 206*93433708SPali Rohár /* 207*93433708SPali Rohár * lane0: USB3/GbE1 PHY Status 1 208*93433708SPali Rohár * lane1: PCIe/GbE0 PHY Status 1 209*93433708SPali Rohár * (used only by SGMII code) 210*93433708SPali Rohár */ 211*93433708SPali Rohár #define COMPHY_PHY_STAT1 0x18 212*93433708SPali Rohár #define PHY_RX_INIT_DONE_BIT BIT(0) 213*93433708SPali Rohár #define PHY_PLL_READY_RX_BIT BIT(2) 214*93433708SPali Rohár #define PHY_PLL_READY_TX_BIT BIT(3) 215*93433708SPali Rohár 216*93433708SPali Rohár /* PHY Selector */ 217*93433708SPali Rohár #define COMPHY_SELECTOR_PHY_REG 0xFC 218*93433708SPali Rohár /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */ 219*93433708SPali Rohár #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0) 220*93433708SPali Rohár /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */ 221*93433708SPali Rohár #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4) 222*93433708SPali Rohár /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */ 223*93433708SPali Rohár #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8) 2249695375aSMiquel Raynal 2259695375aSMiquel Raynal struct mvebu_a3700_comphy_conf { 2269695375aSMiquel Raynal unsigned int lane; 2279695375aSMiquel Raynal enum phy_mode mode; 2289695375aSMiquel Raynal int submode; 2299695375aSMiquel Raynal }; 2309695375aSMiquel Raynal 231*93433708SPali Rohár #define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode) \ 2329695375aSMiquel Raynal { \ 2339695375aSMiquel Raynal .lane = _lane, \ 2349695375aSMiquel Raynal .mode = _mode, \ 2359695375aSMiquel Raynal .submode = _smode, \ 2369695375aSMiquel Raynal } 2379695375aSMiquel Raynal 238*93433708SPali Rohár #define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \ 239*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA) 2409695375aSMiquel Raynal 241*93433708SPali Rohár #define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \ 242*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode) 2439695375aSMiquel Raynal 2449695375aSMiquel Raynal static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = { 2459695375aSMiquel Raynal /* lane 0 */ 246*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS), 247*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII), 248*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX), 249*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX), 2509695375aSMiquel Raynal /* lane 1 */ 251*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE), 252*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII), 253*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX), 254*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX), 2559695375aSMiquel Raynal /* lane 2 */ 256*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA), 257*93433708SPali Rohár MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS), 258*93433708SPali Rohár }; 259*93433708SPali Rohár 260*93433708SPali Rohár struct mvebu_a3700_comphy_priv { 261*93433708SPali Rohár void __iomem *comphy_regs; 262*93433708SPali Rohár void __iomem *lane0_phy_regs; /* USB3 and GbE1 */ 263*93433708SPali Rohár void __iomem *lane1_phy_regs; /* PCIe and GbE0 */ 264*93433708SPali Rohár void __iomem *lane2_phy_indirect; /* SATA and USB3 */ 265*93433708SPali Rohár spinlock_t lock; /* for PHY selector access */ 266*93433708SPali Rohár bool xtal_is_40m; 2679695375aSMiquel Raynal }; 2689695375aSMiquel Raynal 2699695375aSMiquel Raynal struct mvebu_a3700_comphy_lane { 270*93433708SPali Rohár struct mvebu_a3700_comphy_priv *priv; 2719695375aSMiquel Raynal struct device *dev; 2729695375aSMiquel Raynal unsigned int id; 2739695375aSMiquel Raynal enum phy_mode mode; 2749695375aSMiquel Raynal int submode; 275*93433708SPali Rohár bool invert_tx; 276*93433708SPali Rohár bool invert_rx; 277*93433708SPali Rohár bool needs_reset; 2789695375aSMiquel Raynal }; 2799695375aSMiquel Raynal 280*93433708SPali Rohár struct gbe_phy_init_data_fix { 281*93433708SPali Rohár u16 addr; 282*93433708SPali Rohár u16 value; 283*93433708SPali Rohár }; 284*93433708SPali Rohár 285*93433708SPali Rohár /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 286*93433708SPali Rohár static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = { 287*93433708SPali Rohár { 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 }, 288*93433708SPali Rohár { 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 }, 289*93433708SPali Rohár { 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 }, 290*93433708SPali Rohár { 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC }, 291*93433708SPali Rohár { 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 }, 292*93433708SPali Rohár { 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 }, 293*93433708SPali Rohár { 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 }, 294*93433708SPali Rohár { 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 }, 295*93433708SPali Rohár { 0x104, 0x0C10 } 296*93433708SPali Rohár }; 297*93433708SPali Rohár 298*93433708SPali Rohár /* 40M1G25 mode init data */ 299*93433708SPali Rohár static u16 gbe_phy_init[512] = { 300*93433708SPali Rohár /* 0 1 2 3 4 5 6 7 */ 301*93433708SPali Rohár /*-----------------------------------------------------------*/ 302*93433708SPali Rohár /* 8 9 A B C D E F */ 303*93433708SPali Rohár 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 304*93433708SPali Rohár 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 305*93433708SPali Rohár 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 306*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 307*93433708SPali Rohár 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 308*93433708SPali Rohár 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 309*93433708SPali Rohár 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 310*93433708SPali Rohár 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 311*93433708SPali Rohár 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 312*93433708SPali Rohár 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 313*93433708SPali Rohár 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 314*93433708SPali Rohár 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 315*93433708SPali Rohár 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 316*93433708SPali Rohár 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 317*93433708SPali Rohár 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 318*93433708SPali Rohár 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 319*93433708SPali Rohár 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 320*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 321*93433708SPali Rohár 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 322*93433708SPali Rohár 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 323*93433708SPali Rohár 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 324*93433708SPali Rohár 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 325*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 326*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 327*93433708SPali Rohár 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 328*93433708SPali Rohár 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 329*93433708SPali Rohár 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 330*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 331*93433708SPali Rohár 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 332*93433708SPali Rohár 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 333*93433708SPali Rohár 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 334*93433708SPali Rohár 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 335*93433708SPali Rohár 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 336*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 337*93433708SPali Rohár 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 338*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 339*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 340*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 341*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 342*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 343*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 344*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 345*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 346*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 347*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 348*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 349*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 350*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 351*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 352*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 353*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 354*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 355*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 356*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 357*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 358*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 359*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 360*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 361*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 362*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 363*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 364*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 365*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 366*93433708SPali Rohár 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 367*93433708SPali Rohár }; 368*93433708SPali Rohár 369*93433708SPali Rohár static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask) 3709695375aSMiquel Raynal { 371*93433708SPali Rohár u32 val; 3729695375aSMiquel Raynal 373*93433708SPali Rohár val = readl(addr); 374*93433708SPali Rohár val = (val & ~mask) | (data & mask); 375*93433708SPali Rohár writel(val, addr); 376*93433708SPali Rohár } 3779695375aSMiquel Raynal 378*93433708SPali Rohár static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) 379*93433708SPali Rohár { 380*93433708SPali Rohár u16 val; 381*93433708SPali Rohár 382*93433708SPali Rohár val = readw(addr); 383*93433708SPali Rohár val = (val & ~mask) | (data & mask); 384*93433708SPali Rohár writew(val, addr); 385*93433708SPali Rohár } 386*93433708SPali Rohár 387*93433708SPali Rohár /* Used for accessing lane 2 registers (SATA/USB3 PHY) */ 388*93433708SPali Rohár static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv, 389*93433708SPali Rohár u32 offset, u16 data, u16 mask) 390*93433708SPali Rohár { 391*93433708SPali Rohár writel(offset, 392*93433708SPali Rohár priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); 393*93433708SPali Rohár comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, 394*93433708SPali Rohár data, mask); 395*93433708SPali Rohár } 396*93433708SPali Rohár 397*93433708SPali Rohár static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, 398*93433708SPali Rohár u16 reg, u16 data, u16 mask) 399*93433708SPali Rohár { 400*93433708SPali Rohár if (lane->id == 2) { 401*93433708SPali Rohár /* lane 2 PHY registers are accessed indirectly */ 402*93433708SPali Rohár comphy_set_indirect(lane->priv, 403*93433708SPali Rohár reg + COMPHY_LANE2_REGS_BASE, 404*93433708SPali Rohár data, mask); 405*93433708SPali Rohár } else { 406*93433708SPali Rohár void __iomem *base = lane->id == 1 ? 407*93433708SPali Rohár lane->priv->lane1_phy_regs : 408*93433708SPali Rohár lane->priv->lane0_phy_regs; 409*93433708SPali Rohár 410*93433708SPali Rohár comphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg), 411*93433708SPali Rohár data, mask); 412*93433708SPali Rohár } 413*93433708SPali Rohár } 414*93433708SPali Rohár 415*93433708SPali Rohár static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, 416*93433708SPali Rohár u16 reg, u16 bits, 417*93433708SPali Rohár ulong sleep_us, ulong timeout_us) 418*93433708SPali Rohár { 419*93433708SPali Rohár int ret; 420*93433708SPali Rohár 421*93433708SPali Rohár if (lane->id == 2) { 422*93433708SPali Rohár u32 data; 423*93433708SPali Rohár 424*93433708SPali Rohár /* lane 2 PHY registers are accessed indirectly */ 425*93433708SPali Rohár writel(reg + COMPHY_LANE2_REGS_BASE, 426*93433708SPali Rohár lane->priv->lane2_phy_indirect + 427*93433708SPali Rohár COMPHY_LANE2_INDIR_ADDR); 428*93433708SPali Rohár 429*93433708SPali Rohár ret = readl_poll_timeout(lane->priv->lane2_phy_indirect + 430*93433708SPali Rohár COMPHY_LANE2_INDIR_DATA, 431*93433708SPali Rohár data, (data & bits) == bits, 432*93433708SPali Rohár sleep_us, timeout_us); 433*93433708SPali Rohár } else { 434*93433708SPali Rohár void __iomem *base = lane->id == 1 ? 435*93433708SPali Rohár lane->priv->lane1_phy_regs : 436*93433708SPali Rohár lane->priv->lane0_phy_regs; 437*93433708SPali Rohár u16 data; 438*93433708SPali Rohár 439*93433708SPali Rohár ret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg), 440*93433708SPali Rohár data, (data & bits) == bits, 441*93433708SPali Rohár sleep_us, timeout_us); 442*93433708SPali Rohár } 443*93433708SPali Rohár 444*93433708SPali Rohár return ret; 445*93433708SPali Rohár } 446*93433708SPali Rohár 447*93433708SPali Rohár static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane, 448*93433708SPali Rohár u8 reg, u32 data, u32 mask) 449*93433708SPali Rohár { 450*93433708SPali Rohár comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg), 451*93433708SPali Rohár data, mask); 452*93433708SPali Rohár } 453*93433708SPali Rohár 454*93433708SPali Rohár static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane, 455*93433708SPali Rohár u8 reg, u32 bits, 456*93433708SPali Rohár ulong sleep_us, ulong timeout_us) 457*93433708SPali Rohár { 458*93433708SPali Rohár u32 data; 459*93433708SPali Rohár 460*93433708SPali Rohár return readl_poll_timeout(lane->priv->comphy_regs + 461*93433708SPali Rohár COMPHY_PHY_REG(lane->id, reg), 462*93433708SPali Rohár data, (data & bits) == bits, 463*93433708SPali Rohár sleep_us, timeout_us); 464*93433708SPali Rohár } 465*93433708SPali Rohár 466*93433708SPali Rohár /* PHY selector configures with corresponding modes */ 467*93433708SPali Rohár static int 468*93433708SPali Rohár mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane) 469*93433708SPali Rohár { 470*93433708SPali Rohár u32 old, new, clr = 0, set = 0; 471*93433708SPali Rohár unsigned long flags; 472*93433708SPali Rohár 473*93433708SPali Rohár switch (lane->mode) { 474*93433708SPali Rohár case PHY_MODE_SATA: 475*93433708SPali Rohár /* SATA must be in Lane2 */ 476*93433708SPali Rohár if (lane->id == 2) 477*93433708SPali Rohár clr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 478*93433708SPali Rohár else 479*93433708SPali Rohár goto error; 480*93433708SPali Rohár break; 481*93433708SPali Rohár 482*93433708SPali Rohár case PHY_MODE_ETHERNET: 483*93433708SPali Rohár if (lane->id == 0) 484*93433708SPali Rohár clr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 485*93433708SPali Rohár else if (lane->id == 1) 486*93433708SPali Rohár clr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 487*93433708SPali Rohár else 488*93433708SPali Rohár goto error; 489*93433708SPali Rohár break; 490*93433708SPali Rohár 491*93433708SPali Rohár case PHY_MODE_USB_HOST_SS: 492*93433708SPali Rohár if (lane->id == 2) 493*93433708SPali Rohár set = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 494*93433708SPali Rohár else if (lane->id == 0) 495*93433708SPali Rohár set = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 496*93433708SPali Rohár else 497*93433708SPali Rohár goto error; 498*93433708SPali Rohár break; 499*93433708SPali Rohár 500*93433708SPali Rohár case PHY_MODE_PCIE: 501*93433708SPali Rohár /* PCIE must be in Lane1 */ 502*93433708SPali Rohár if (lane->id == 1) 503*93433708SPali Rohár set = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 504*93433708SPali Rohár else 505*93433708SPali Rohár goto error; 506*93433708SPali Rohár break; 507*93433708SPali Rohár 508ea17a0f1SPali Rohár default: 509*93433708SPali Rohár goto error; 510*93433708SPali Rohár } 511*93433708SPali Rohár 512*93433708SPali Rohár spin_lock_irqsave(&lane->priv->lock, flags); 513*93433708SPali Rohár 514*93433708SPali Rohár old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); 515*93433708SPali Rohár new = (old & ~clr) | set; 516*93433708SPali Rohár writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); 517*93433708SPali Rohár 518*93433708SPali Rohár spin_unlock_irqrestore(&lane->priv->lock, flags); 519*93433708SPali Rohár 520*93433708SPali Rohár dev_dbg(lane->dev, 521*93433708SPali Rohár "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n", 522*93433708SPali Rohár lane->id, lane->mode, old, new); 523*93433708SPali Rohár 524*93433708SPali Rohár return 0; 525*93433708SPali Rohár error: 526*93433708SPali Rohár dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id, 527*93433708SPali Rohár lane->mode); 528ea17a0f1SPali Rohár return -EINVAL; 529ea17a0f1SPali Rohár } 530*93433708SPali Rohár 531*93433708SPali Rohár static int 532*93433708SPali Rohár mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane) 533*93433708SPali Rohár { 534*93433708SPali Rohár u32 mask, data, ref_clk; 535*93433708SPali Rohár int ret; 536*93433708SPali Rohár 537*93433708SPali Rohár /* Configure phy selector for SATA */ 538*93433708SPali Rohár ret = mvebu_a3700_comphy_set_phy_selector(lane); 539*93433708SPali Rohár if (ret) 540*93433708SPali Rohár return ret; 541*93433708SPali Rohár 542*93433708SPali Rohár /* Clear phy isolation mode to make it work in normal mode */ 543*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, 544*93433708SPali Rohár 0x0, PHY_ISOLATE_MODE); 545*93433708SPali Rohár 546*93433708SPali Rohár /* 0. Check the Polarity invert bits */ 547*93433708SPali Rohár data = 0x0; 548*93433708SPali Rohár if (lane->invert_tx) 549*93433708SPali Rohár data |= TXD_INVERT_BIT; 550*93433708SPali Rohár if (lane->invert_rx) 551*93433708SPali Rohár data |= RXD_INVERT_BIT; 552*93433708SPali Rohár mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 553*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 554*93433708SPali Rohár 555*93433708SPali Rohár /* 1. Select 40-bit data width */ 556*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, 557*93433708SPali Rohár DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK); 558*93433708SPali Rohár 559*93433708SPali Rohár /* 2. Select reference clock(25M) and PHY mode (SATA) */ 560*93433708SPali Rohár if (lane->priv->xtal_is_40m) 561*93433708SPali Rohár ref_clk = REF_FREF_SEL_SERDES_40MHZ; 562*93433708SPali Rohár else 563*93433708SPali Rohár ref_clk = REF_FREF_SEL_SERDES_25MHZ; 564*93433708SPali Rohár 565*93433708SPali Rohár data = ref_clk | COMPHY_MODE_SATA; 566*93433708SPali Rohár mask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK; 567*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 568*93433708SPali Rohár 569*93433708SPali Rohár /* 3. Use maximum PLL rate (no power save) */ 570*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, 571*93433708SPali Rohár USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT); 572*93433708SPali Rohár 573*93433708SPali Rohár /* 4. Reset reserved bit */ 574*93433708SPali Rohár comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG, 575*93433708SPali Rohár 0x0, PHYCTRL_FRM_PIN_BIT); 576*93433708SPali Rohár 577*93433708SPali Rohár /* 5. Set vendor-specific configuration (It is done in sata driver) */ 578*93433708SPali Rohár /* XXX: in U-Boot below sequence was executed in this place, in Linux 579*93433708SPali Rohár * not. Now it is done only in U-Boot before this comphy 580*93433708SPali Rohár * initialization - tests shows that it works ok, but in case of any 581*93433708SPali Rohár * future problem it is left for reference. 582*93433708SPali Rohár * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 583*93433708SPali Rohár * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 584*93433708SPali Rohár */ 585*93433708SPali Rohár 586*93433708SPali Rohár /* Wait for > 55 us to allow PLL be enabled */ 587*93433708SPali Rohár udelay(PLL_SET_DELAY_US); 588*93433708SPali Rohár 589*93433708SPali Rohár /* Polling status */ 590*93433708SPali Rohár ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, 591*93433708SPali Rohár PLL_READY_TX_BIT, COMPHY_PLL_SLEEP, 592*93433708SPali Rohár COMPHY_PLL_TIMEOUT); 593*93433708SPali Rohár if (ret) 594*93433708SPali Rohár dev_err(lane->dev, "Failed to lock SATA PLL\n"); 595*93433708SPali Rohár 596*93433708SPali Rohár return ret; 5979695375aSMiquel Raynal } 5989695375aSMiquel Raynal 599*93433708SPali Rohár static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, 600*93433708SPali Rohár bool is_1gbps) 601*93433708SPali Rohár { 602*93433708SPali Rohár int addr, fix_idx; 603*93433708SPali Rohár u16 val; 604*93433708SPali Rohár 605*93433708SPali Rohár fix_idx = 0; 606*93433708SPali Rohár for (addr = 0; addr < 512; addr++) { 607*93433708SPali Rohár /* 608*93433708SPali Rohár * All PHY register values are defined in full for 3.125Gbps 609*93433708SPali Rohár * SERDES speed. The values required for 1.25 Gbps are almost 610*93433708SPali Rohár * the same and only few registers should be "fixed" in 611*93433708SPali Rohár * comparison to 3.125 Gbps values. These register values are 612*93433708SPali Rohár * stored in "gbe_phy_init_fix" array. 613*93433708SPali Rohár */ 614*93433708SPali Rohár if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) { 615*93433708SPali Rohár /* Use new value */ 616*93433708SPali Rohár val = gbe_phy_init_fix[fix_idx].value; 617*93433708SPali Rohár if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix)) 618*93433708SPali Rohár fix_idx++; 619*93433708SPali Rohár } else { 620*93433708SPali Rohár val = gbe_phy_init[addr]; 621*93433708SPali Rohár } 622*93433708SPali Rohár 623*93433708SPali Rohár comphy_lane_reg_set(lane, addr, val, 0xFFFF); 624*93433708SPali Rohár } 625*93433708SPali Rohár } 626*93433708SPali Rohár 627*93433708SPali Rohár static int 628*93433708SPali Rohár mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane) 629*93433708SPali Rohár { 630*93433708SPali Rohár u32 mask, data, speed_sel; 631*93433708SPali Rohár int ret; 632*93433708SPali Rohár 633*93433708SPali Rohár /* Set selector */ 634*93433708SPali Rohár ret = mvebu_a3700_comphy_set_phy_selector(lane); 635*93433708SPali Rohár if (ret) 636*93433708SPali Rohár return ret; 637*93433708SPali Rohár 638*93433708SPali Rohár /* 639*93433708SPali Rohár * 1. Reset PHY by setting PHY input port PIN_RESET=1. 640*93433708SPali Rohár * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 641*93433708SPali Rohár * PHY TXP/TXN output to idle state during PHY initialization 642*93433708SPali Rohár * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 643*93433708SPali Rohár */ 644*93433708SPali Rohár data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 645*93433708SPali Rohár mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 646*93433708SPali Rohár PIN_PU_TX_BIT | PHY_RX_INIT_BIT; 647*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 648*93433708SPali Rohár 649*93433708SPali Rohár /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 650*93433708SPali Rohár data = 0x0; 651*93433708SPali Rohár mask = PIN_RESET_COMPHY_BIT; 652*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 653*93433708SPali Rohár 654*93433708SPali Rohár /* 655*93433708SPali Rohár * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 656*93433708SPali Rohár * bit rate 657*93433708SPali Rohár */ 658*93433708SPali Rohár switch (lane->submode) { 659*93433708SPali Rohár case PHY_INTERFACE_MODE_SGMII: 660*93433708SPali Rohár case PHY_INTERFACE_MODE_1000BASEX: 661*93433708SPali Rohár /* SGMII 1G, SerDes speed 1.25G */ 662*93433708SPali Rohár speed_sel = SERDES_SPEED_1_25_G; 663*93433708SPali Rohár break; 664*93433708SPali Rohár case PHY_INTERFACE_MODE_2500BASEX: 665*93433708SPali Rohár /* 2500Base-X, SerDes speed 3.125G */ 666*93433708SPali Rohár speed_sel = SERDES_SPEED_3_125_G; 667*93433708SPali Rohár break; 668*93433708SPali Rohár default: 669*93433708SPali Rohár /* Other rates are not supported */ 670*93433708SPali Rohár dev_err(lane->dev, 671*93433708SPali Rohár "unsupported phy speed %d on comphy lane%d\n", 672*93433708SPali Rohár lane->submode, lane->id); 673*93433708SPali Rohár return -EINVAL; 674*93433708SPali Rohár } 675*93433708SPali Rohár data = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel); 676*93433708SPali Rohár mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 677*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 678*93433708SPali Rohár 679*93433708SPali Rohár /* 680*93433708SPali Rohár * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 681*93433708SPali Rohár * start SW programming. 682*93433708SPali Rohár */ 683*93433708SPali Rohár mdelay(10); 684*93433708SPali Rohár 685*93433708SPali Rohár /* 7. Program COMPHY register PHY_MODE */ 686*93433708SPali Rohár data = COMPHY_MODE_SERDES; 687*93433708SPali Rohár mask = COMPHY_MODE_MASK; 688*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 689*93433708SPali Rohár 690*93433708SPali Rohár /* 691*93433708SPali Rohár * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 692*93433708SPali Rohár * source 693*93433708SPali Rohár */ 694*93433708SPali Rohár data = 0x0; 695*93433708SPali Rohár mask = PHY_REF_CLK_SEL; 696*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); 697*93433708SPali Rohár 698*93433708SPali Rohár /* 699*93433708SPali Rohár * 9. Set correct reference clock frequency in COMPHY register 700*93433708SPali Rohár * REF_FREF_SEL. 701*93433708SPali Rohár */ 702*93433708SPali Rohár if (lane->priv->xtal_is_40m) 703*93433708SPali Rohár data = REF_FREF_SEL_SERDES_50MHZ; 704*93433708SPali Rohár else 705*93433708SPali Rohár data = REF_FREF_SEL_SERDES_25MHZ; 706*93433708SPali Rohár 707*93433708SPali Rohár mask = REF_FREF_SEL_MASK; 708*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 709*93433708SPali Rohár 710*93433708SPali Rohár /* 711*93433708SPali Rohár * 10. Program COMPHY register PHY_GEN_MAX[1:0] 712*93433708SPali Rohár * This step is mentioned in the flow received from verification team. 713*93433708SPali Rohár * However the PHY_GEN_MAX value is only meaningful for other interfaces 714*93433708SPali Rohár * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or 715*93433708SPali Rohár * PCIe speed 2.5/5 Gbps 716*93433708SPali Rohár */ 717*93433708SPali Rohár 718*93433708SPali Rohár /* 719*93433708SPali Rohár * 11. Program COMPHY register SEL_BITS to set correct parallel data 720*93433708SPali Rohár * bus width 721*93433708SPali Rohár */ 722*93433708SPali Rohár data = DATA_WIDTH_10BIT; 723*93433708SPali Rohár mask = SEL_DATA_WIDTH_MASK; 724*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask); 725*93433708SPali Rohár 726*93433708SPali Rohár /* 727*93433708SPali Rohár * 12. As long as DFE function needs to be enabled in any mode, 728*93433708SPali Rohár * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 729*93433708SPali Rohár * for real chip during COMPHY power on. 730*93433708SPali Rohár * The value of the DFE_UPDATE_EN already is 0x3F, because it is the 731*93433708SPali Rohár * default value after reset of the PHY. 732*93433708SPali Rohár */ 733*93433708SPali Rohár 734*93433708SPali Rohár /* 735*93433708SPali Rohár * 13. Program COMPHY GEN registers. 736*93433708SPali Rohár * These registers should be programmed based on the lab testing result 737*93433708SPali Rohár * to achieve optimal performance. Please contact the CEA group to get 738*93433708SPali Rohár * the related GEN table during real chip bring-up. We only required to 739*93433708SPali Rohár * run though the entire registers programming flow defined by 740*93433708SPali Rohár * "comphy_gbe_phy_init" when the REF clock is 40 MHz. For REF clock 741*93433708SPali Rohár * 25 MHz the default values stored in PHY registers are OK. 742*93433708SPali Rohár */ 743*93433708SPali Rohár dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n", 744*93433708SPali Rohár lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G"); 745*93433708SPali Rohár if (lane->priv->xtal_is_40m) 746*93433708SPali Rohár comphy_gbe_phy_init(lane, 747*93433708SPali Rohár lane->submode != PHY_INTERFACE_MODE_2500BASEX); 748*93433708SPali Rohár 749*93433708SPali Rohár /* 750*93433708SPali Rohár * 14. Check the PHY Polarity invert bit 751*93433708SPali Rohár */ 752*93433708SPali Rohár data = 0x0; 753*93433708SPali Rohár if (lane->invert_tx) 754*93433708SPali Rohár data |= TXD_INVERT_BIT; 755*93433708SPali Rohár if (lane->invert_rx) 756*93433708SPali Rohár data |= RXD_INVERT_BIT; 757*93433708SPali Rohár mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 758*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 759*93433708SPali Rohár 760*93433708SPali Rohár /* 761*93433708SPali Rohár * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 762*93433708SPali Rohár * start PHY power up sequence. All the PHY register programming should 763*93433708SPali Rohár * be done before PIN_PU_PLL=1. There should be no register programming 764*93433708SPali Rohár * for normal PHY operation from this point. 765*93433708SPali Rohár */ 766*93433708SPali Rohár data = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; 767*93433708SPali Rohár mask = data; 768*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 769*93433708SPali Rohár 770*93433708SPali Rohár /* 771*93433708SPali Rohár * 16. Wait for PHY power up sequence to finish by checking output ports 772*93433708SPali Rohár * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 773*93433708SPali Rohár */ 774*93433708SPali Rohár ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 775*93433708SPali Rohár PHY_PLL_READY_TX_BIT | 776*93433708SPali Rohár PHY_PLL_READY_RX_BIT, 777*93433708SPali Rohár COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 778*93433708SPali Rohár if (ret) { 779*93433708SPali Rohár dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", 780*93433708SPali Rohár lane->id); 781*93433708SPali Rohár return ret; 782*93433708SPali Rohár } 783*93433708SPali Rohár 784*93433708SPali Rohár /* 785*93433708SPali Rohár * 17. Set COMPHY input port PIN_TX_IDLE=0 786*93433708SPali Rohár */ 787*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); 788*93433708SPali Rohár 789*93433708SPali Rohár /* 790*93433708SPali Rohár * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 791*93433708SPali Rohár * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 792*93433708SPali Rohár * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 793*93433708SPali Rohár * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 794*93433708SPali Rohár * refer to RX initialization part for details. 795*93433708SPali Rohár */ 796*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 797*93433708SPali Rohár PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 798*93433708SPali Rohár 799*93433708SPali Rohár ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 800*93433708SPali Rohár PHY_PLL_READY_TX_BIT | 801*93433708SPali Rohár PHY_PLL_READY_RX_BIT, 802*93433708SPali Rohár COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 803*93433708SPali Rohár if (ret) { 804*93433708SPali Rohár dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", 805*93433708SPali Rohár lane->id); 806*93433708SPali Rohár return ret; 807*93433708SPali Rohár } 808*93433708SPali Rohár 809*93433708SPali Rohár ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 810*93433708SPali Rohár PHY_RX_INIT_DONE_BIT, 811*93433708SPali Rohár COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 812*93433708SPali Rohár if (ret) 813*93433708SPali Rohár dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", 814*93433708SPali Rohár lane->id); 815*93433708SPali Rohár 816*93433708SPali Rohár return ret; 817*93433708SPali Rohár } 818*93433708SPali Rohár 819*93433708SPali Rohár static int 820*93433708SPali Rohár mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane) 821*93433708SPali Rohár { 822*93433708SPali Rohár u32 mask, data, cfg, ref_clk; 823*93433708SPali Rohár int ret; 824*93433708SPali Rohár 825*93433708SPali Rohár /* Set phy seclector */ 826*93433708SPali Rohár ret = mvebu_a3700_comphy_set_phy_selector(lane); 827*93433708SPali Rohár if (ret) 828*93433708SPali Rohár return ret; 829*93433708SPali Rohár 830*93433708SPali Rohár /* 831*93433708SPali Rohár * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 832*93433708SPali Rohár * register belong to UTMI module, so it is set in UTMI phy driver. 833*93433708SPali Rohár */ 834*93433708SPali Rohár 835*93433708SPali Rohár /* 836*93433708SPali Rohár * 1. Set PRD_TXDEEMPH (3.5db de-emph) 837*93433708SPali Rohár */ 838*93433708SPali Rohár data = PRD_TXDEEMPH0_MASK; 839*93433708SPali Rohár mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 840*93433708SPali Rohár CFG_TX_ALIGN_POS_MASK; 841*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask); 842*93433708SPali Rohár 843*93433708SPali Rohár /* 844*93433708SPali Rohár * 2. Set BIT0: enable transmitter in high impedance mode 845*93433708SPali Rohár * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 846*93433708SPali Rohár * Set BIT6: Tx detect Rx at HiZ mode 847*93433708SPali Rohár * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 848*93433708SPali Rohár * together with bit 0 of COMPHY_PIPE_LANE_CFG0 register 849*93433708SPali Rohár */ 850*93433708SPali Rohár data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 851*93433708SPali Rohár mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 852*93433708SPali Rohár TX_ELEC_IDLE_MODE_EN; 853*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask); 854*93433708SPali Rohár 855*93433708SPali Rohár /* 856*93433708SPali Rohár * 3. Set Spread Spectrum Clock Enabled 857*93433708SPali Rohár */ 858*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4, 859*93433708SPali Rohár SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); 860*93433708SPali Rohár 861*93433708SPali Rohár /* 862*93433708SPali Rohár * 4. Set Override Margining Controls From the MAC: 863*93433708SPali Rohár * Use margining signals from lane configuration 864*93433708SPali Rohár */ 865*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL, 866*93433708SPali Rohár MODE_MARGIN_OVERRIDE, 0xFFFF); 867*93433708SPali Rohár 868*93433708SPali Rohár /* 869*93433708SPali Rohár * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 870*93433708SPali Rohár * set Mode Clock Source = PCLK is generated from REFCLK 871*93433708SPali Rohár */ 872*93433708SPali Rohár data = 0x0; 873*93433708SPali Rohár mask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK | 874*93433708SPali Rohár BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK; 875*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask); 876*93433708SPali Rohár 877*93433708SPali Rohár /* 878*93433708SPali Rohár * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 879*93433708SPali Rohár */ 880*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_GEN2_SET2, 881*93433708SPali Rohár GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK); 882*93433708SPali Rohár 883*93433708SPali Rohár /* 884*93433708SPali Rohár * 7. Unset G3 Spread Spectrum Clock Amplitude 885*93433708SPali Rohár * set G3 TX and RX Register Master Current Select 886*93433708SPali Rohár */ 887*93433708SPali Rohár data = GS2_VREG_RXTX_MAS_ISET_60U; 888*93433708SPali Rohár mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK | 889*93433708SPali Rohár GS2_RSVD_6_0_MASK; 890*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask); 891*93433708SPali Rohár 892*93433708SPali Rohár /* 893*93433708SPali Rohár * 8. Check crystal jumper setting and program the Power and PLL Control 894*93433708SPali Rohár * accordingly Change RX wait 895*93433708SPali Rohár */ 896*93433708SPali Rohár if (lane->priv->xtal_is_40m) { 897*93433708SPali Rohár ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 898*93433708SPali Rohár cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 899*93433708SPali Rohár } else { 900*93433708SPali Rohár ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 901*93433708SPali Rohár cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 902*93433708SPali Rohár } 903*93433708SPali Rohár 904*93433708SPali Rohár data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 905*93433708SPali Rohár PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk; 906*93433708SPali Rohár mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 907*93433708SPali Rohár PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK | 908*93433708SPali Rohár REF_FREF_SEL_MASK; 909*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 910*93433708SPali Rohár 911*93433708SPali Rohár data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 912*93433708SPali Rohár mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 913*93433708SPali Rohár CFG_PM_RXDLOZ_WAIT_MASK; 914*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); 915*93433708SPali Rohár 916*93433708SPali Rohár /* 917*93433708SPali Rohár * 9. Enable idle sync 918*93433708SPali Rohár */ 919*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, 920*93433708SPali Rohár IDLE_SYNC_EN, IDLE_SYNC_EN); 921*93433708SPali Rohár 922*93433708SPali Rohár /* 923*93433708SPali Rohár * 10. Enable the output of 500M clock 924*93433708SPali Rohár */ 925*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN); 926*93433708SPali Rohár 927*93433708SPali Rohár /* 928*93433708SPali Rohár * 11. Set 20-bit data width 929*93433708SPali Rohár */ 930*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, 931*93433708SPali Rohár DATA_WIDTH_20BIT, 0xFFFF); 932*93433708SPali Rohár 933*93433708SPali Rohár /* 934*93433708SPali Rohár * 12. Override Speed_PLL value and use MAC PLL 935*93433708SPali Rohár */ 936*93433708SPali Rohár data = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT; 937*93433708SPali Rohár mask = 0xFFFF; 938*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask); 939*93433708SPali Rohár 940*93433708SPali Rohár /* 941*93433708SPali Rohár * 13. Check the Polarity invert bit 942*93433708SPali Rohár */ 943*93433708SPali Rohár data = 0x0; 944*93433708SPali Rohár if (lane->invert_tx) 945*93433708SPali Rohár data |= TXD_INVERT_BIT; 946*93433708SPali Rohár if (lane->invert_rx) 947*93433708SPali Rohár data |= RXD_INVERT_BIT; 948*93433708SPali Rohár mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 949*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 950*93433708SPali Rohár 951*93433708SPali Rohár /* 952*93433708SPali Rohár * 14. Set max speed generation to USB3.0 5Gbps 953*93433708SPali Rohár */ 954*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN, 955*93433708SPali Rohár PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK); 956*93433708SPali Rohár 957*93433708SPali Rohár /* 958*93433708SPali Rohár * 15. Set capacitor value for FFE gain peaking to 0xF 959*93433708SPali Rohár */ 960*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_GEN2_SET3, 961*93433708SPali Rohár GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK); 962*93433708SPali Rohár 963*93433708SPali Rohár /* 964*93433708SPali Rohár * 16. Release SW reset 965*93433708SPali Rohár */ 966*93433708SPali Rohár data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 967*93433708SPali Rohár mask = 0xFFFF; 968*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); 969*93433708SPali Rohár 970*93433708SPali Rohár /* Wait for > 55 us to allow PCLK be enabled */ 971*93433708SPali Rohár udelay(PLL_SET_DELAY_US); 972*93433708SPali Rohár 973*93433708SPali Rohár ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, 974*93433708SPali Rohár COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 975*93433708SPali Rohár if (ret) 976*93433708SPali Rohár dev_err(lane->dev, "Failed to lock USB3 PLL\n"); 977*93433708SPali Rohár 978*93433708SPali Rohár return ret; 979*93433708SPali Rohár } 980*93433708SPali Rohár 981*93433708SPali Rohár static int 982*93433708SPali Rohár mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane) 983*93433708SPali Rohár { 984*93433708SPali Rohár u32 mask, data, ref_clk; 985*93433708SPali Rohár int ret; 986*93433708SPali Rohár 987*93433708SPali Rohár /* Configure phy selector for PCIe */ 988*93433708SPali Rohár ret = mvebu_a3700_comphy_set_phy_selector(lane); 989*93433708SPali Rohár if (ret) 990*93433708SPali Rohár return ret; 991*93433708SPali Rohár 992*93433708SPali Rohár /* 1. Enable max PLL. */ 993*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, 994*93433708SPali Rohár USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 995*93433708SPali Rohár 996*93433708SPali Rohár /* 2. Select 20 bit SERDES interface. */ 997*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, 998*93433708SPali Rohár CFG_SEL_20B, CFG_SEL_20B); 999*93433708SPali Rohár 1000*93433708SPali Rohár /* 3. Force to use reg setting for PCIe mode */ 1001*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1, 1002*93433708SPali Rohár SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 1003*93433708SPali Rohár 1004*93433708SPali Rohár /* 4. Change RX wait */ 1005*93433708SPali Rohár data = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT; 1006*93433708SPali Rohár mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 1007*93433708SPali Rohár CFG_PM_RXDLOZ_WAIT_MASK; 1008*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); 1009*93433708SPali Rohár 1010*93433708SPali Rohár /* 5. Enable idle sync */ 1011*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, 1012*93433708SPali Rohár IDLE_SYNC_EN, IDLE_SYNC_EN); 1013*93433708SPali Rohár 1014*93433708SPali Rohár /* 6. Enable the output of 100M/125M/500M clock */ 1015*93433708SPali Rohár data = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN; 1016*93433708SPali Rohár mask = data; 1017*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); 1018*93433708SPali Rohár 1019*93433708SPali Rohár /* 1020*93433708SPali Rohár * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 1021*93433708SPali Rohár * PCI-E driver 1022*93433708SPali Rohár */ 1023*93433708SPali Rohár 1024*93433708SPali Rohár /* 1025*93433708SPali Rohár * 8. Check crystal jumper setting and program the Power and PLL 1026*93433708SPali Rohár * Control accordingly 1027*93433708SPali Rohár */ 1028*93433708SPali Rohár 1029*93433708SPali Rohár if (lane->priv->xtal_is_40m) 1030*93433708SPali Rohár ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 1031*93433708SPali Rohár else 1032*93433708SPali Rohár ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 1033*93433708SPali Rohár 1034*93433708SPali Rohár data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 1035*93433708SPali Rohár PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk; 1036*93433708SPali Rohár mask = 0xFFFF; 1037*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 1038*93433708SPali Rohár 1039*93433708SPali Rohár /* 9. Override Speed_PLL value and use MAC PLL */ 1040*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, 1041*93433708SPali Rohár SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, 1042*93433708SPali Rohár 0xFFFF); 1043*93433708SPali Rohár 1044*93433708SPali Rohár /* 10. Check the Polarity invert bit */ 1045*93433708SPali Rohár data = 0x0; 1046*93433708SPali Rohár if (lane->invert_tx) 1047*93433708SPali Rohár data |= TXD_INVERT_BIT; 1048*93433708SPali Rohár if (lane->invert_rx) 1049*93433708SPali Rohár data |= RXD_INVERT_BIT; 1050*93433708SPali Rohár mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 1051*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 1052*93433708SPali Rohár 1053*93433708SPali Rohár /* 11. Release SW reset */ 1054*93433708SPali Rohár data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; 1055*93433708SPali Rohár mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK; 1056*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); 1057*93433708SPali Rohár 1058*93433708SPali Rohár /* Wait for > 55 us to allow PCLK be enabled */ 1059*93433708SPali Rohár udelay(PLL_SET_DELAY_US); 1060*93433708SPali Rohár 1061*93433708SPali Rohár ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, 1062*93433708SPali Rohár COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 1063*93433708SPali Rohár if (ret) 1064*93433708SPali Rohár dev_err(lane->dev, "Failed to lock PCIE PLL\n"); 1065*93433708SPali Rohár 1066*93433708SPali Rohár return ret; 1067*93433708SPali Rohár } 1068*93433708SPali Rohár 1069*93433708SPali Rohár static void 1070*93433708SPali Rohár mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane) 1071*93433708SPali Rohár { 1072*93433708SPali Rohár /* Set phy isolation mode */ 1073*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, 1074*93433708SPali Rohár PHY_ISOLATE_MODE, PHY_ISOLATE_MODE); 1075*93433708SPali Rohár 1076*93433708SPali Rohár /* Power off PLL, Tx, Rx */ 1077*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, 1078*93433708SPali Rohár 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 1079*93433708SPali Rohár } 1080*93433708SPali Rohár 1081*93433708SPali Rohár static void 1082*93433708SPali Rohár mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane) 1083*93433708SPali Rohár { 1084*93433708SPali Rohár u32 mask, data; 1085*93433708SPali Rohár 1086*93433708SPali Rohár data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT | 1087*93433708SPali Rohár PHY_RX_INIT_BIT; 1088*93433708SPali Rohár mask = data; 1089*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 1090*93433708SPali Rohár } 1091*93433708SPali Rohár 1092*93433708SPali Rohár static void 1093*93433708SPali Rohár mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane) 1094*93433708SPali Rohár { 1095*93433708SPali Rohár /* Power off PLL, Tx, Rx */ 1096*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, 1097*93433708SPali Rohár 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 1098*93433708SPali Rohár } 1099*93433708SPali Rohár 1100*93433708SPali Rohár static int mvebu_a3700_comphy_reset(struct phy *phy) 1101*93433708SPali Rohár { 1102*93433708SPali Rohár struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1103*93433708SPali Rohár u16 mask, data; 1104*93433708SPali Rohár 1105*93433708SPali Rohár dev_dbg(lane->dev, "resetting lane %d\n", lane->id); 1106*93433708SPali Rohár 1107*93433708SPali Rohár /* COMPHY reset for internal logic */ 1108*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_SFT_RESET, 1109*93433708SPali Rohár SFT_RST_NO_REG, SFT_RST_NO_REG); 1110*93433708SPali Rohár 1111*93433708SPali Rohár /* COMPHY register reset (cleared automatically) */ 1112*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); 1113*93433708SPali Rohár 1114*93433708SPali Rohár /* PIPE soft and register reset */ 1115*93433708SPali Rohár data = PIPE_SOFT_RESET | PIPE_REG_RESET; 1116*93433708SPali Rohár mask = data; 1117*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); 1118*93433708SPali Rohár 1119*93433708SPali Rohár /* Release PIPE register reset */ 1120*93433708SPali Rohár comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, 1121*93433708SPali Rohár 0x0, PIPE_REG_RESET); 1122*93433708SPali Rohár 1123*93433708SPali Rohár /* Reset SB configuration register (only for lanes 0 and 1) */ 1124*93433708SPali Rohár if (lane->id == 0 || lane->id == 1) { 1125*93433708SPali Rohár u32 mask, data; 1126*93433708SPali Rohár 1127*93433708SPali Rohár data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | 1128*93433708SPali Rohár PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; 1129*93433708SPali Rohár mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT; 1130*93433708SPali Rohár comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 1131*93433708SPali Rohár } 1132*93433708SPali Rohár 1133*93433708SPali Rohár return 0; 1134*93433708SPali Rohár } 1135*93433708SPali Rohár 1136*93433708SPali Rohár static bool mvebu_a3700_comphy_check_mode(int lane, 11379695375aSMiquel Raynal enum phy_mode mode, 11389695375aSMiquel Raynal int submode) 11399695375aSMiquel Raynal { 11409695375aSMiquel Raynal int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes); 11419695375aSMiquel Raynal 11429695375aSMiquel Raynal /* Unused PHY mux value is 0x0 */ 11439695375aSMiquel Raynal if (mode == PHY_MODE_INVALID) 1144*93433708SPali Rohár return false; 11459695375aSMiquel Raynal 11469695375aSMiquel Raynal for (i = 0; i < n; i++) { 11479695375aSMiquel Raynal if (mvebu_a3700_comphy_modes[i].lane == lane && 11489695375aSMiquel Raynal mvebu_a3700_comphy_modes[i].mode == mode && 11499695375aSMiquel Raynal mvebu_a3700_comphy_modes[i].submode == submode) 11509695375aSMiquel Raynal break; 11519695375aSMiquel Raynal } 11529695375aSMiquel Raynal 11539695375aSMiquel Raynal if (i == n) 1154*93433708SPali Rohár return false; 11559695375aSMiquel Raynal 1156*93433708SPali Rohár return true; 11579695375aSMiquel Raynal } 11589695375aSMiquel Raynal 11599695375aSMiquel Raynal static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode, 11609695375aSMiquel Raynal int submode) 11619695375aSMiquel Raynal { 11629695375aSMiquel Raynal struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 11639695375aSMiquel Raynal 1164*93433708SPali Rohár if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) { 11659695375aSMiquel Raynal dev_err(lane->dev, "invalid COMPHY mode\n"); 1166*93433708SPali Rohár return -EINVAL; 11679695375aSMiquel Raynal } 11689695375aSMiquel Raynal 1169*93433708SPali Rohár /* Mode cannot be changed while the PHY is powered on */ 1170*93433708SPali Rohár if (phy->power_count && 1171*93433708SPali Rohár (lane->mode != mode || lane->submode != submode)) 1172*93433708SPali Rohár return -EBUSY; 1173*93433708SPali Rohár 1174*93433708SPali Rohár /* If changing mode, ensure reset is called */ 1175*93433708SPali Rohár if (lane->mode != PHY_MODE_INVALID && lane->mode != mode) 1176*93433708SPali Rohár lane->needs_reset = true; 1177*93433708SPali Rohár 11789695375aSMiquel Raynal /* Just remember the mode, ->power_on() will do the real setup */ 11799695375aSMiquel Raynal lane->mode = mode; 11809695375aSMiquel Raynal lane->submode = submode; 11819695375aSMiquel Raynal 11829695375aSMiquel Raynal return 0; 11839695375aSMiquel Raynal } 11849695375aSMiquel Raynal 11859695375aSMiquel Raynal static int mvebu_a3700_comphy_power_on(struct phy *phy) 11869695375aSMiquel Raynal { 11879695375aSMiquel Raynal struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1188cacc9539SMiquel Raynal int ret; 11899695375aSMiquel Raynal 1190*93433708SPali Rohár if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, 1191*93433708SPali Rohár lane->submode)) { 11929695375aSMiquel Raynal dev_err(lane->dev, "invalid COMPHY mode\n"); 1193*93433708SPali Rohár return -EINVAL; 1194*93433708SPali Rohár } 1195*93433708SPali Rohár 1196*93433708SPali Rohár if (lane->needs_reset) { 1197*93433708SPali Rohár ret = mvebu_a3700_comphy_reset(phy); 1198*93433708SPali Rohár if (ret) 1199*93433708SPali Rohár return ret; 1200*93433708SPali Rohár 1201*93433708SPali Rohár lane->needs_reset = false; 12029695375aSMiquel Raynal } 12039695375aSMiquel Raynal 12049695375aSMiquel Raynal switch (lane->mode) { 12059695375aSMiquel Raynal case PHY_MODE_USB_HOST_SS: 12069695375aSMiquel Raynal dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); 1207*93433708SPali Rohár return mvebu_a3700_comphy_usb3_power_on(lane); 12089695375aSMiquel Raynal case PHY_MODE_SATA: 12099695375aSMiquel Raynal dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); 1210*93433708SPali Rohár return mvebu_a3700_comphy_sata_power_on(lane); 12119695375aSMiquel Raynal case PHY_MODE_ETHERNET: 1212*93433708SPali Rohár dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id); 1213*93433708SPali Rohár return mvebu_a3700_comphy_ethernet_power_on(lane); 12149695375aSMiquel Raynal case PHY_MODE_PCIE: 12159695375aSMiquel Raynal dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); 1216*93433708SPali Rohár return mvebu_a3700_comphy_pcie_power_on(lane); 12179695375aSMiquel Raynal default: 12189695375aSMiquel Raynal dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); 1219*93433708SPali Rohár return -EOPNOTSUPP; 12209695375aSMiquel Raynal } 12219695375aSMiquel Raynal } 12229695375aSMiquel Raynal 12239695375aSMiquel Raynal static int mvebu_a3700_comphy_power_off(struct phy *phy) 12249695375aSMiquel Raynal { 12259695375aSMiquel Raynal struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 12269695375aSMiquel Raynal 1227*93433708SPali Rohár switch (lane->mode) { 1228*93433708SPali Rohár case PHY_MODE_USB_HOST_SS: 1229*93433708SPali Rohár /* 1230*93433708SPali Rohár * The USB3 MAC sets the USB3 PHY to low state, so we do not 1231*93433708SPali Rohár * need to power off USB3 PHY again. 1232*93433708SPali Rohár */ 1233*93433708SPali Rohár break; 1234*93433708SPali Rohár 1235*93433708SPali Rohár case PHY_MODE_SATA: 1236*93433708SPali Rohár mvebu_a3700_comphy_sata_power_off(lane); 1237*93433708SPali Rohár break; 1238*93433708SPali Rohár 1239*93433708SPali Rohár case PHY_MODE_ETHERNET: 1240*93433708SPali Rohár mvebu_a3700_comphy_ethernet_power_off(lane); 1241*93433708SPali Rohár break; 1242*93433708SPali Rohár 1243*93433708SPali Rohár case PHY_MODE_PCIE: 1244*93433708SPali Rohár mvebu_a3700_comphy_pcie_power_off(lane); 1245*93433708SPali Rohár break; 1246*93433708SPali Rohár 1247*93433708SPali Rohár default: 1248*93433708SPali Rohár dev_err(lane->dev, "invalid COMPHY mode\n"); 1249*93433708SPali Rohár return -EINVAL; 1250*93433708SPali Rohár } 1251*93433708SPali Rohár 1252*93433708SPali Rohár return 0; 12539695375aSMiquel Raynal } 12549695375aSMiquel Raynal 12559695375aSMiquel Raynal static const struct phy_ops mvebu_a3700_comphy_ops = { 12569695375aSMiquel Raynal .power_on = mvebu_a3700_comphy_power_on, 12579695375aSMiquel Raynal .power_off = mvebu_a3700_comphy_power_off, 1258*93433708SPali Rohár .reset = mvebu_a3700_comphy_reset, 12599695375aSMiquel Raynal .set_mode = mvebu_a3700_comphy_set_mode, 12609695375aSMiquel Raynal .owner = THIS_MODULE, 12619695375aSMiquel Raynal }; 12629695375aSMiquel Raynal 12639695375aSMiquel Raynal static struct phy *mvebu_a3700_comphy_xlate(struct device *dev, 12649695375aSMiquel Raynal struct of_phandle_args *args) 12659695375aSMiquel Raynal { 12669695375aSMiquel Raynal struct mvebu_a3700_comphy_lane *lane; 12674bf18d5aSPali Rohár unsigned int port; 12689695375aSMiquel Raynal struct phy *phy; 12699695375aSMiquel Raynal 12709695375aSMiquel Raynal phy = of_phy_simple_xlate(dev, args); 12719695375aSMiquel Raynal if (IS_ERR(phy)) 12729695375aSMiquel Raynal return phy; 12739695375aSMiquel Raynal 12749695375aSMiquel Raynal lane = phy_get_drvdata(phy); 12754bf18d5aSPali Rohár 12764bf18d5aSPali Rohár port = args->args[0]; 12774bf18d5aSPali Rohár if (port != 0 && (port != 1 || lane->id != 0)) { 12784bf18d5aSPali Rohár dev_err(lane->dev, "invalid port number %u\n", port); 12794bf18d5aSPali Rohár return ERR_PTR(-EINVAL); 12804bf18d5aSPali Rohár } 12819695375aSMiquel Raynal 1282*93433708SPali Rohár lane->invert_tx = args->args[1] & BIT(0); 1283*93433708SPali Rohár lane->invert_rx = args->args[1] & BIT(1); 1284*93433708SPali Rohár 12859695375aSMiquel Raynal return phy; 12869695375aSMiquel Raynal } 12879695375aSMiquel Raynal 12889695375aSMiquel Raynal static int mvebu_a3700_comphy_probe(struct platform_device *pdev) 12899695375aSMiquel Raynal { 1290*93433708SPali Rohár struct mvebu_a3700_comphy_priv *priv; 12919695375aSMiquel Raynal struct phy_provider *provider; 12929695375aSMiquel Raynal struct device_node *child; 1293*93433708SPali Rohár struct resource *res; 1294*93433708SPali Rohár struct clk *clk; 1295*93433708SPali Rohár int ret; 1296*93433708SPali Rohár 1297*93433708SPali Rohár priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1298*93433708SPali Rohár if (!priv) 1299*93433708SPali Rohár return -ENOMEM; 1300*93433708SPali Rohár 1301*93433708SPali Rohár spin_lock_init(&priv->lock); 1302*93433708SPali Rohár 1303*93433708SPali Rohár res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "comphy"); 1304*93433708SPali Rohár priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res); 1305*93433708SPali Rohár if (IS_ERR(priv->comphy_regs)) 1306*93433708SPali Rohár return PTR_ERR(priv->comphy_regs); 1307*93433708SPali Rohár 1308*93433708SPali Rohár res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1309*93433708SPali Rohár "lane1_pcie_gbe"); 1310*93433708SPali Rohár priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res); 1311*93433708SPali Rohár if (IS_ERR(priv->lane1_phy_regs)) 1312*93433708SPali Rohár return PTR_ERR(priv->lane1_phy_regs); 1313*93433708SPali Rohár 1314*93433708SPali Rohár res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1315*93433708SPali Rohár "lane0_usb3_gbe"); 1316*93433708SPali Rohár priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res); 1317*93433708SPali Rohár if (IS_ERR(priv->lane0_phy_regs)) 1318*93433708SPali Rohár return PTR_ERR(priv->lane0_phy_regs); 1319*93433708SPali Rohár 1320*93433708SPali Rohár res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1321*93433708SPali Rohár "lane2_sata_usb3"); 1322*93433708SPali Rohár priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res); 1323*93433708SPali Rohár if (IS_ERR(priv->lane2_phy_indirect)) 1324*93433708SPali Rohár return PTR_ERR(priv->lane2_phy_indirect); 1325*93433708SPali Rohár 1326*93433708SPali Rohár /* 1327*93433708SPali Rohár * Driver needs to know if reference xtal clock is 40MHz or 25MHz. 1328*93433708SPali Rohár * Old DT bindings do not have xtal clk present. So do not fail here 1329*93433708SPali Rohár * and expects that default 25MHz reference clock is used. 1330*93433708SPali Rohár */ 1331*93433708SPali Rohár clk = clk_get(&pdev->dev, "xtal"); 1332*93433708SPali Rohár if (IS_ERR(clk)) { 1333*93433708SPali Rohár if (PTR_ERR(clk) == -EPROBE_DEFER) 1334*93433708SPali Rohár return -EPROBE_DEFER; 1335*93433708SPali Rohár dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n", 1336*93433708SPali Rohár PTR_ERR(clk)); 1337*93433708SPali Rohár } else { 1338*93433708SPali Rohár ret = clk_prepare_enable(clk); 1339*93433708SPali Rohár if (ret) { 1340*93433708SPali Rohár dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n", 1341*93433708SPali Rohár ret); 1342*93433708SPali Rohár } else { 1343*93433708SPali Rohár if (clk_get_rate(clk) == 40000000) 1344*93433708SPali Rohár priv->xtal_is_40m = true; 1345*93433708SPali Rohár clk_disable_unprepare(clk); 1346*93433708SPali Rohár } 1347*93433708SPali Rohár clk_put(clk); 1348*93433708SPali Rohár } 1349*93433708SPali Rohár 1350*93433708SPali Rohár dev_set_drvdata(&pdev->dev, priv); 13519695375aSMiquel Raynal 13529695375aSMiquel Raynal for_each_available_child_of_node(pdev->dev.of_node, child) { 13539695375aSMiquel Raynal struct mvebu_a3700_comphy_lane *lane; 13549695375aSMiquel Raynal struct phy *phy; 13559695375aSMiquel Raynal int ret; 13569695375aSMiquel Raynal u32 lane_id; 13579695375aSMiquel Raynal 13589695375aSMiquel Raynal ret = of_property_read_u32(child, "reg", &lane_id); 13599695375aSMiquel Raynal if (ret < 0) { 13609695375aSMiquel Raynal dev_err(&pdev->dev, "missing 'reg' property (%d)\n", 13619695375aSMiquel Raynal ret); 13629695375aSMiquel Raynal continue; 13639695375aSMiquel Raynal } 13649695375aSMiquel Raynal 1365*93433708SPali Rohár if (lane_id >= 3) { 13669695375aSMiquel Raynal dev_err(&pdev->dev, "invalid 'reg' property\n"); 13679695375aSMiquel Raynal continue; 13689695375aSMiquel Raynal } 13699695375aSMiquel Raynal 13709695375aSMiquel Raynal lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); 1371beae796dSNishka Dasgupta if (!lane) { 1372beae796dSNishka Dasgupta of_node_put(child); 13739695375aSMiquel Raynal return -ENOMEM; 1374beae796dSNishka Dasgupta } 13759695375aSMiquel Raynal 13769695375aSMiquel Raynal phy = devm_phy_create(&pdev->dev, child, 13779695375aSMiquel Raynal &mvebu_a3700_comphy_ops); 1378beae796dSNishka Dasgupta if (IS_ERR(phy)) { 1379beae796dSNishka Dasgupta of_node_put(child); 13809695375aSMiquel Raynal return PTR_ERR(phy); 1381beae796dSNishka Dasgupta } 13829695375aSMiquel Raynal 1383*93433708SPali Rohár lane->priv = priv; 13849695375aSMiquel Raynal lane->dev = &pdev->dev; 13859695375aSMiquel Raynal lane->mode = PHY_MODE_INVALID; 13869695375aSMiquel Raynal lane->submode = PHY_INTERFACE_MODE_NA; 13879695375aSMiquel Raynal lane->id = lane_id; 1388*93433708SPali Rohár lane->invert_tx = false; 1389*93433708SPali Rohár lane->invert_rx = false; 13909695375aSMiquel Raynal phy_set_drvdata(phy, lane); 1391*93433708SPali Rohár 1392*93433708SPali Rohár /* 1393*93433708SPali Rohár * To avoid relying on the bootloader/firmware configuration, 1394*93433708SPali Rohár * power off all comphys. 1395*93433708SPali Rohár */ 1396*93433708SPali Rohár mvebu_a3700_comphy_reset(phy); 1397*93433708SPali Rohár lane->needs_reset = false; 13989695375aSMiquel Raynal } 13999695375aSMiquel Raynal 14009695375aSMiquel Raynal provider = devm_of_phy_provider_register(&pdev->dev, 14019695375aSMiquel Raynal mvebu_a3700_comphy_xlate); 1402*93433708SPali Rohár 14039695375aSMiquel Raynal return PTR_ERR_OR_ZERO(provider); 14049695375aSMiquel Raynal } 14059695375aSMiquel Raynal 14069695375aSMiquel Raynal static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = { 14079695375aSMiquel Raynal { .compatible = "marvell,comphy-a3700" }, 14089695375aSMiquel Raynal { }, 14099695375aSMiquel Raynal }; 14109695375aSMiquel Raynal MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table); 14119695375aSMiquel Raynal 14129695375aSMiquel Raynal static struct platform_driver mvebu_a3700_comphy_driver = { 14139695375aSMiquel Raynal .probe = mvebu_a3700_comphy_probe, 14149695375aSMiquel Raynal .driver = { 14159695375aSMiquel Raynal .name = "mvebu-a3700-comphy", 14169695375aSMiquel Raynal .of_match_table = mvebu_a3700_comphy_of_match_table, 14179695375aSMiquel Raynal }, 14189695375aSMiquel Raynal }; 14199695375aSMiquel Raynal module_platform_driver(mvebu_a3700_comphy_driver); 14209695375aSMiquel Raynal 14219695375aSMiquel Raynal MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>"); 1422*93433708SPali Rohár MODULE_AUTHOR("Pali Rohár <pali@kernel.org>"); 1423*93433708SPali Rohár MODULE_AUTHOR("Marek Behún <kabel@kernel.org>"); 14249695375aSMiquel Raynal MODULE_DESCRIPTION("Common PHY driver for A3700"); 14259695375aSMiquel Raynal MODULE_LICENSE("GPL v2"); 1426