1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Russell King, Deep Blue Solutions Ltd. 4 * 5 * Partly derived from CP110 comphy driver by Antoine Tenart 6 * <antoine.tenart@bootlin.com> 7 */ 8 #include <linux/delay.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy/phy.h> 13 #include <linux/phy.h> 14 #include <linux/platform_device.h> 15 16 #define MAX_A38X_COMPHY 6 17 #define MAX_A38X_PORTS 3 18 19 #define COMPHY_CFG1 0x00 20 #define COMPHY_CFG1_GEN_TX(x) ((x) << 26) 21 #define COMPHY_CFG1_GEN_TX_MSK COMPHY_CFG1_GEN_TX(15) 22 #define COMPHY_CFG1_GEN_RX(x) ((x) << 22) 23 #define COMPHY_CFG1_GEN_RX_MSK COMPHY_CFG1_GEN_RX(15) 24 #define GEN_SGMII_1_25GBPS 6 25 #define GEN_SGMII_3_125GBPS 8 26 27 #define COMPHY_STAT1 0x18 28 #define COMPHY_STAT1_PLL_RDY_TX BIT(3) 29 #define COMPHY_STAT1_PLL_RDY_RX BIT(2) 30 31 #define COMPHY_SELECTOR 0xfc 32 33 struct a38x_comphy; 34 35 struct a38x_comphy_lane { 36 void __iomem *base; 37 struct a38x_comphy *priv; 38 unsigned int n; 39 40 int port; 41 }; 42 43 struct a38x_comphy { 44 void __iomem *base; 45 void __iomem *conf; 46 struct device *dev; 47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; 48 }; 49 50 static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = { 51 { 0, 0, 0 }, 52 { 4, 5, 0 }, 53 { 0, 4, 0 }, 54 { 0, 0, 4 }, 55 { 0, 3, 0 }, 56 { 0, 0, 3 }, 57 }; 58 59 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) 60 { 61 struct a38x_comphy *priv = lane->priv; 62 u32 conf; 63 64 if (priv->conf) { 65 conf = readl_relaxed(priv->conf); 66 if (enable) 67 conf |= BIT(lane->port); 68 else 69 conf &= ~BIT(lane->port); 70 writel(conf, priv->conf); 71 } 72 } 73 74 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, 75 unsigned int offset, u32 mask, u32 value) 76 { 77 u32 val; 78 79 val = readl_relaxed(lane->base + offset) & ~mask; 80 writel(val | value, lane->base + offset); 81 } 82 83 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, 84 unsigned int gen_tx, unsigned int gen_rx) 85 { 86 a38x_comphy_set_reg(lane, COMPHY_CFG1, 87 COMPHY_CFG1_GEN_TX_MSK | COMPHY_CFG1_GEN_RX_MSK, 88 COMPHY_CFG1_GEN_TX(gen_tx) | 89 COMPHY_CFG1_GEN_RX(gen_rx)); 90 } 91 92 static int a38x_comphy_poll(struct a38x_comphy_lane *lane, 93 unsigned int offset, u32 mask, u32 value) 94 { 95 u32 val; 96 int ret; 97 98 ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val, 99 (val & mask) == value, 100 1000, 150000); 101 102 if (ret) 103 dev_err(lane->priv->dev, 104 "comphy%u: timed out waiting for status\n", lane->n); 105 106 return ret; 107 } 108 109 /* 110 * We only support changing the speed for comphys configured for GBE. 111 * Since that is all we do, we only poll for PLL ready status. 112 */ 113 static int a38x_comphy_set_mode(struct phy *phy, enum phy_mode mode, int sub) 114 { 115 struct a38x_comphy_lane *lane = phy_get_drvdata(phy); 116 unsigned int gen; 117 int ret; 118 119 if (mode != PHY_MODE_ETHERNET) 120 return -EINVAL; 121 122 switch (sub) { 123 case PHY_INTERFACE_MODE_SGMII: 124 case PHY_INTERFACE_MODE_1000BASEX: 125 gen = GEN_SGMII_1_25GBPS; 126 break; 127 128 case PHY_INTERFACE_MODE_2500BASEX: 129 gen = GEN_SGMII_3_125GBPS; 130 break; 131 132 default: 133 return -EINVAL; 134 } 135 136 a38x_set_conf(lane, false); 137 138 a38x_comphy_set_speed(lane, gen, gen); 139 140 ret = a38x_comphy_poll(lane, COMPHY_STAT1, 141 COMPHY_STAT1_PLL_RDY_TX | 142 COMPHY_STAT1_PLL_RDY_RX, 143 COMPHY_STAT1_PLL_RDY_TX | 144 COMPHY_STAT1_PLL_RDY_RX); 145 146 if (ret == 0) 147 a38x_set_conf(lane, true); 148 149 return ret; 150 } 151 152 static const struct phy_ops a38x_comphy_ops = { 153 .set_mode = a38x_comphy_set_mode, 154 .owner = THIS_MODULE, 155 }; 156 157 static struct phy *a38x_comphy_xlate(struct device *dev, 158 struct of_phandle_args *args) 159 { 160 struct a38x_comphy_lane *lane; 161 struct phy *phy; 162 u32 val; 163 164 if (WARN_ON(args->args[0] >= MAX_A38X_PORTS)) 165 return ERR_PTR(-EINVAL); 166 167 phy = of_phy_simple_xlate(dev, args); 168 if (IS_ERR(phy)) 169 return phy; 170 171 lane = phy_get_drvdata(phy); 172 if (lane->port >= 0) 173 return ERR_PTR(-EBUSY); 174 175 lane->port = args->args[0]; 176 177 val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR); 178 val = (val >> (4 * lane->n)) & 0xf; 179 180 if (!gbe_mux[lane->n][lane->port] || 181 val != gbe_mux[lane->n][lane->port]) { 182 dev_warn(lane->priv->dev, 183 "comphy%u: not configured for GBE\n", lane->n); 184 phy = ERR_PTR(-EINVAL); 185 } 186 187 return phy; 188 } 189 190 static int a38x_comphy_probe(struct platform_device *pdev) 191 { 192 struct phy_provider *provider; 193 struct device_node *child; 194 struct a38x_comphy *priv; 195 struct resource *res; 196 void __iomem *base; 197 198 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 199 if (!priv) 200 return -ENOMEM; 201 202 base = devm_platform_ioremap_resource(pdev, 0); 203 if (IS_ERR(base)) 204 return PTR_ERR(base); 205 206 priv->dev = &pdev->dev; 207 priv->base = base; 208 209 /* Optional */ 210 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "conf"); 211 if (res) { 212 priv->conf = devm_ioremap_resource(&pdev->dev, res); 213 if (IS_ERR(priv->conf)) 214 return PTR_ERR(priv->conf); 215 } 216 217 for_each_available_child_of_node(pdev->dev.of_node, child) { 218 struct phy *phy; 219 int ret; 220 u32 val; 221 222 ret = of_property_read_u32(child, "reg", &val); 223 if (ret < 0) { 224 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", 225 ret); 226 continue; 227 } 228 229 if (val >= MAX_A38X_COMPHY || priv->lane[val].base) { 230 dev_err(&pdev->dev, "invalid 'reg' property\n"); 231 continue; 232 } 233 234 phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops); 235 if (IS_ERR(phy)) { 236 of_node_put(child); 237 return PTR_ERR(phy); 238 } 239 240 priv->lane[val].base = base + 0x28 * val; 241 priv->lane[val].priv = priv; 242 priv->lane[val].n = val; 243 priv->lane[val].port = -1; 244 phy_set_drvdata(phy, &priv->lane[val]); 245 } 246 247 dev_set_drvdata(&pdev->dev, priv); 248 249 provider = devm_of_phy_provider_register(&pdev->dev, a38x_comphy_xlate); 250 251 return PTR_ERR_OR_ZERO(provider); 252 } 253 254 static const struct of_device_id a38x_comphy_of_match_table[] = { 255 { .compatible = "marvell,armada-380-comphy" }, 256 { }, 257 }; 258 MODULE_DEVICE_TABLE(of, a38x_comphy_of_match_table); 259 260 static struct platform_driver a38x_comphy_driver = { 261 .probe = a38x_comphy_probe, 262 .driver = { 263 .name = "armada-38x-comphy", 264 .of_match_table = a38x_comphy_of_match_table, 265 }, 266 }; 267 module_platform_driver(a38x_comphy_driver); 268 269 MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>"); 270 MODULE_DESCRIPTION("Common PHY driver for Armada 38x SoCs"); 271 MODULE_LICENSE("GPL v2"); 272