1 /* 2 * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver 3 * 4 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 5 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 25 /* Transmitter HS Pre-Emphasis Enable */ 26 #define RCU_CFG1_TX_PEE BIT(0) 27 /* Disconnect Threshold */ 28 #define RCU_CFG1_DIS_THR_MASK 0x00038000 29 #define RCU_CFG1_DIS_THR_SHIFT 15 30 31 struct ltq_rcu_usb2_bits { 32 u8 hostmode; 33 u8 slave_endianness; 34 u8 host_endianness; 35 bool have_ana_cfg; 36 }; 37 38 struct ltq_rcu_usb2_priv { 39 struct regmap *regmap; 40 unsigned int phy_reg_offset; 41 unsigned int ana_cfg1_reg_offset; 42 const struct ltq_rcu_usb2_bits *reg_bits; 43 struct device *dev; 44 struct phy *phy; 45 struct clk *phy_gate_clk; 46 struct reset_control *ctrl_reset; 47 struct reset_control *phy_reset; 48 }; 49 50 static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = { 51 .hostmode = 11, 52 .slave_endianness = 9, 53 .host_endianness = 10, 54 .have_ana_cfg = false, 55 }; 56 57 static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = { 58 .hostmode = 11, 59 .slave_endianness = 17, 60 .host_endianness = 10, 61 .have_ana_cfg = false, 62 }; 63 64 static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = { 65 .hostmode = 11, 66 .slave_endianness = 9, 67 .host_endianness = 10, 68 .have_ana_cfg = true, 69 }; 70 71 static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = { 72 { 73 .compatible = "lantiq,ase-usb2-phy", 74 .data = &xway_rcu_usb2_reg_bits, 75 }, 76 { 77 .compatible = "lantiq,danube-usb2-phy", 78 .data = &xway_rcu_usb2_reg_bits, 79 }, 80 { 81 .compatible = "lantiq,xrx100-usb2-phy", 82 .data = &xrx100_rcu_usb2_reg_bits, 83 }, 84 { 85 .compatible = "lantiq,xrx200-usb2-phy", 86 .data = &xrx200_rcu_usb2_reg_bits, 87 }, 88 { 89 .compatible = "lantiq,xrx300-usb2-phy", 90 .data = &xrx200_rcu_usb2_reg_bits, 91 }, 92 { }, 93 }; 94 MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match); 95 96 static int ltq_rcu_usb2_phy_init(struct phy *phy) 97 { 98 struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy); 99 100 if (priv->reg_bits->have_ana_cfg) { 101 regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset, 102 RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE); 103 regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset, 104 RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT); 105 } 106 107 /* Configure core to host mode */ 108 regmap_update_bits(priv->regmap, priv->phy_reg_offset, 109 BIT(priv->reg_bits->hostmode), 0); 110 111 /* Select DMA endianness (Host-endian: big-endian) */ 112 regmap_update_bits(priv->regmap, priv->phy_reg_offset, 113 BIT(priv->reg_bits->slave_endianness), 0); 114 regmap_update_bits(priv->regmap, priv->phy_reg_offset, 115 BIT(priv->reg_bits->host_endianness), 116 BIT(priv->reg_bits->host_endianness)); 117 118 return 0; 119 } 120 121 static int ltq_rcu_usb2_phy_power_on(struct phy *phy) 122 { 123 struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy); 124 struct device *dev = priv->dev; 125 int ret; 126 127 reset_control_deassert(priv->phy_reset); 128 129 ret = clk_prepare_enable(priv->phy_gate_clk); 130 if (ret) 131 dev_err(dev, "failed to enable PHY gate\n"); 132 133 return ret; 134 } 135 136 static int ltq_rcu_usb2_phy_power_off(struct phy *phy) 137 { 138 struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy); 139 140 reset_control_assert(priv->phy_reset); 141 142 clk_disable_unprepare(priv->phy_gate_clk); 143 144 return 0; 145 } 146 147 static struct phy_ops ltq_rcu_usb2_phy_ops = { 148 .init = ltq_rcu_usb2_phy_init, 149 .power_on = ltq_rcu_usb2_phy_power_on, 150 .power_off = ltq_rcu_usb2_phy_power_off, 151 .owner = THIS_MODULE, 152 }; 153 154 static int ltq_rcu_usb2_of_parse(struct ltq_rcu_usb2_priv *priv, 155 struct platform_device *pdev) 156 { 157 struct device *dev = priv->dev; 158 const __be32 *offset; 159 160 priv->reg_bits = of_device_get_match_data(dev); 161 162 priv->regmap = syscon_node_to_regmap(dev->of_node->parent); 163 if (IS_ERR(priv->regmap)) { 164 dev_err(dev, "Failed to lookup RCU regmap\n"); 165 return PTR_ERR(priv->regmap); 166 } 167 168 offset = of_get_address(dev->of_node, 0, NULL, NULL); 169 if (!offset) { 170 dev_err(dev, "Failed to get RCU PHY reg offset\n"); 171 return -ENOENT; 172 } 173 priv->phy_reg_offset = __be32_to_cpu(*offset); 174 175 if (priv->reg_bits->have_ana_cfg) { 176 offset = of_get_address(dev->of_node, 1, NULL, NULL); 177 if (!offset) { 178 dev_err(dev, "Failed to get RCU ANA CFG1 reg offset\n"); 179 return -ENOENT; 180 } 181 priv->ana_cfg1_reg_offset = __be32_to_cpu(*offset); 182 } 183 184 priv->phy_gate_clk = devm_clk_get(dev, "phy"); 185 if (IS_ERR(priv->phy_gate_clk)) { 186 dev_err(dev, "Unable to get USB phy gate clk\n"); 187 return PTR_ERR(priv->phy_gate_clk); 188 } 189 190 priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl"); 191 if (IS_ERR(priv->ctrl_reset)) { 192 if (PTR_ERR(priv->ctrl_reset) != -EPROBE_DEFER) 193 dev_err(dev, "failed to get 'ctrl' reset\n"); 194 return PTR_ERR(priv->ctrl_reset); 195 } 196 197 priv->phy_reset = devm_reset_control_get_optional(dev, "phy"); 198 199 return PTR_ERR_OR_ZERO(priv->phy_reset); 200 } 201 202 static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev) 203 { 204 struct device *dev = &pdev->dev; 205 struct ltq_rcu_usb2_priv *priv; 206 struct phy_provider *provider; 207 int ret; 208 209 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 210 if (!priv) 211 return -ENOMEM; 212 213 priv->dev = dev; 214 215 ret = ltq_rcu_usb2_of_parse(priv, pdev); 216 if (ret) 217 return ret; 218 219 /* Reset USB core through reset controller */ 220 reset_control_deassert(priv->ctrl_reset); 221 222 reset_control_assert(priv->phy_reset); 223 224 priv->phy = devm_phy_create(dev, dev->of_node, <q_rcu_usb2_phy_ops); 225 if (IS_ERR(priv->phy)) { 226 dev_err(dev, "failed to create PHY\n"); 227 return PTR_ERR(priv->phy); 228 } 229 230 phy_set_drvdata(priv->phy, priv); 231 232 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 233 if (IS_ERR(provider)) 234 return PTR_ERR(provider); 235 236 dev_set_drvdata(priv->dev, priv); 237 return 0; 238 } 239 240 static struct platform_driver ltq_rcu_usb2_phy_driver = { 241 .probe = ltq_rcu_usb2_phy_probe, 242 .driver = { 243 .name = "lantiq-rcu-usb2-phy", 244 .of_match_table = ltq_rcu_usb2_phy_of_match, 245 } 246 }; 247 module_platform_driver(ltq_rcu_usb2_phy_driver); 248 249 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 250 MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver"); 251 MODULE_LICENSE("GPL v2"); 252