1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Intel Keem Bay eMMC PHY driver
4  * Copyright (C) 2020 Intel Corporation
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 
18 /* eMMC/SD/SDIO core/phy configuration registers */
19 #define PHY_CFG_0		0x24
20 #define  SEL_DLY_TXCLK_MASK	BIT(29)
21 #define  OTAP_DLY_ENA_MASK	BIT(27)
22 #define  OTAP_DLY_SEL_MASK	GENMASK(26, 23)
23 #define  DLL_EN_MASK		BIT(10)
24 #define  PWR_DOWN_MASK		BIT(0)
25 
26 #define PHY_CFG_2		0x2c
27 #define  SEL_FREQ_MASK		GENMASK(12, 10)
28 
29 #define PHY_STAT		0x40
30 #define  CAL_DONE_MASK		BIT(6)
31 #define  IS_CALDONE(x)		((x) & CAL_DONE_MASK)
32 #define  DLL_RDY_MASK		BIT(5)
33 #define  IS_DLLRDY(x)		((x) & DLL_RDY_MASK)
34 
35 /* From ACS_eMMC51_16nFFC_RO1100_Userguide_v1p0.pdf p17 */
36 #define FREQSEL_200M_170M	0x0
37 #define FREQSEL_170M_140M	0x1
38 #define FREQSEL_140M_110M	0x2
39 #define FREQSEL_110M_80M	0x3
40 #define FREQSEL_80M_50M		0x4
41 
42 struct keembay_emmc_phy {
43 	struct regmap *syscfg;
44 	struct clk *emmcclk;
45 };
46 
47 static const struct regmap_config keembay_regmap_config = {
48 	.reg_bits = 32,
49 	.val_bits = 32,
50 	.reg_stride = 4,
51 };
52 
53 static int keembay_emmc_phy_power(struct phy *phy, bool on_off)
54 {
55 	struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
56 	unsigned int caldone;
57 	unsigned int dllrdy;
58 	unsigned int freqsel;
59 	unsigned int mhz;
60 	int ret;
61 
62 	/*
63 	 * Keep phyctrl_pdb and phyctrl_endll low to allow
64 	 * initialization of CALIO state M/C DFFs
65 	 */
66 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
67 				 FIELD_PREP(PWR_DOWN_MASK, 0));
68 	if (ret) {
69 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
70 		return ret;
71 	}
72 
73 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
74 				 FIELD_PREP(DLL_EN_MASK, 0));
75 	if (ret) {
76 		dev_err(&phy->dev, "turn off the dll failed: %d\n", ret);
77 		return ret;
78 	}
79 
80 	/* Already finish power off above */
81 	if (!on_off)
82 		return 0;
83 
84 	mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000);
85 	if (mhz <= 200 && mhz >= 170)
86 		freqsel = FREQSEL_200M_170M;
87 	else if (mhz <= 170 && mhz >= 140)
88 		freqsel = FREQSEL_170M_140M;
89 	else if (mhz <= 140 && mhz >= 110)
90 		freqsel = FREQSEL_140M_110M;
91 	else if (mhz <= 110 && mhz >= 80)
92 		freqsel = FREQSEL_110M_80M;
93 	else if (mhz <= 80 && mhz >= 50)
94 		freqsel = FREQSEL_80M_50M;
95 	else
96 		freqsel = 0x0;
97 
98 	if (mhz < 50 || mhz > 200)
99 		dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);
100 
101 	/*
102 	 * According to the user manual, calpad calibration
103 	 * cycle takes more than 2us without the minimal recommended
104 	 * value, so we may need a little margin here
105 	 */
106 	udelay(5);
107 
108 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
109 				 FIELD_PREP(PWR_DOWN_MASK, 1));
110 	if (ret) {
111 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
112 		return ret;
113 	}
114 
115 	/*
116 	 * According to the user manual, it asks driver to wait 5us for
117 	 * calpad busy trimming. However it is documented that this value is
118 	 * PVT(A.K.A. process, voltage and temperature) relevant, so some
119 	 * failure cases are found which indicates we should be more tolerant
120 	 * to calpad busy trimming.
121 	 */
122 	ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
123 				       caldone, IS_CALDONE(caldone),
124 				       0, 50);
125 	if (ret) {
126 		dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
127 		return ret;
128 	}
129 
130 	/* Set the frequency of the DLL operation */
131 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_2, SEL_FREQ_MASK,
132 				 FIELD_PREP(SEL_FREQ_MASK, freqsel));
133 	if (ret) {
134 		dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
135 		return ret;
136 	}
137 
138 	/* Turn on the DLL */
139 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
140 				 FIELD_PREP(DLL_EN_MASK, 1));
141 	if (ret) {
142 		dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
143 		return ret;
144 	}
145 
146 	/*
147 	 * We turned on the DLL even though the rate was 0 because we the
148 	 * clock might be turned on later.  ...but we can't wait for the DLL
149 	 * to lock when the rate is 0 because it will never lock with no
150 	 * input clock.
151 	 *
152 	 * Technically we should be checking the lock later when the clock
153 	 * is turned on, but for now we won't.
154 	 */
155 	if (mhz == 0)
156 		return 0;
157 
158 	/*
159 	 * After enabling analog DLL circuits docs say that we need 10.2 us if
160 	 * our source clock is at 50 MHz and that lock time scales linearly
161 	 * with clock speed. If we are powering on the PHY and the card clock
162 	 * is super slow (like 100kHz) this could take as long as 5.1 ms as
163 	 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
164 	 * hopefully we won't be running at 100 kHz, but we should still make
165 	 * sure we wait long enough.
166 	 *
167 	 * NOTE: There appear to be corner cases where the DLL seems to take
168 	 * extra long to lock for reasons that aren't understood. In some
169 	 * extreme cases we've seen it take up to over 10ms (!). We'll be
170 	 * generous and give it 50ms.
171 	 */
172 	ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
173 				       dllrdy, IS_DLLRDY(dllrdy),
174 				       0, 50 * USEC_PER_MSEC);
175 	if (ret)
176 		dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);
177 
178 	return ret;
179 }
180 
181 static int keembay_emmc_phy_init(struct phy *phy)
182 {
183 	struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
184 
185 	/*
186 	 * We purposely get the clock here and not in probe to avoid the
187 	 * circular dependency problem. We expect:
188 	 * - PHY driver to probe
189 	 * - SDHCI driver to start probe
190 	 * - SDHCI driver to register it's clock
191 	 * - SDHCI driver to get the PHY
192 	 * - SDHCI driver to init the PHY
193 	 *
194 	 * The clock is optional, so upon any error just return it like
195 	 * any other error to user.
196 	 */
197 	priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
198 
199 	return PTR_ERR_OR_ZERO(priv->emmcclk);
200 }
201 
202 static int keembay_emmc_phy_exit(struct phy *phy)
203 {
204 	struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
205 
206 	clk_put(priv->emmcclk);
207 
208 	return 0;
209 };
210 
211 static int keembay_emmc_phy_power_on(struct phy *phy)
212 {
213 	struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
214 	int ret;
215 
216 	/* Delay chain based txclk: enable */
217 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
218 				 FIELD_PREP(SEL_DLY_TXCLK_MASK, 1));
219 	if (ret) {
220 		dev_err(&phy->dev, "ERROR: delay chain txclk set: %d\n", ret);
221 		return ret;
222 	}
223 
224 	/* Output tap delay: enable */
225 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_ENA_MASK,
226 				 FIELD_PREP(OTAP_DLY_ENA_MASK, 1));
227 	if (ret) {
228 		dev_err(&phy->dev, "ERROR: output tap delay set: %d\n", ret);
229 		return ret;
230 	}
231 
232 	/* Output tap delay */
233 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_SEL_MASK,
234 				 FIELD_PREP(OTAP_DLY_SEL_MASK, 2));
235 	if (ret) {
236 		dev_err(&phy->dev, "ERROR: output tap delay select: %d\n", ret);
237 		return ret;
238 	}
239 
240 	/* Power up eMMC phy analog blocks */
241 	return keembay_emmc_phy_power(phy, true);
242 }
243 
244 static int keembay_emmc_phy_power_off(struct phy *phy)
245 {
246 	/* Power down eMMC phy analog blocks */
247 	return keembay_emmc_phy_power(phy, false);
248 }
249 
250 static const struct phy_ops ops = {
251 	.init		= keembay_emmc_phy_init,
252 	.exit		= keembay_emmc_phy_exit,
253 	.power_on	= keembay_emmc_phy_power_on,
254 	.power_off	= keembay_emmc_phy_power_off,
255 	.owner		= THIS_MODULE,
256 };
257 
258 static int keembay_emmc_phy_probe(struct platform_device *pdev)
259 {
260 	struct device *dev = &pdev->dev;
261 	struct device_node *np = dev->of_node;
262 	struct keembay_emmc_phy *priv;
263 	struct phy *generic_phy;
264 	struct phy_provider *phy_provider;
265 	void __iomem *base;
266 
267 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
268 	if (!priv)
269 		return -ENOMEM;
270 
271 	base = devm_platform_ioremap_resource(pdev, 0);
272 	if (IS_ERR(base))
273 		return PTR_ERR(base);
274 
275 	priv->syscfg = devm_regmap_init_mmio(dev, base, &keembay_regmap_config);
276 	if (IS_ERR(priv->syscfg))
277 		return PTR_ERR(priv->syscfg);
278 
279 	generic_phy = devm_phy_create(dev, np, &ops);
280 	if (IS_ERR(generic_phy))
281 		return dev_err_probe(dev, PTR_ERR(generic_phy),
282 				     "failed to create PHY\n");
283 
284 	phy_set_drvdata(generic_phy, priv);
285 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
286 
287 	return PTR_ERR_OR_ZERO(phy_provider);
288 }
289 
290 static const struct of_device_id keembay_emmc_phy_dt_ids[] = {
291 	{ .compatible = "intel,keembay-emmc-phy" },
292 	{}
293 };
294 MODULE_DEVICE_TABLE(of, keembay_emmc_phy_dt_ids);
295 
296 static struct platform_driver keembay_emmc_phy_driver = {
297 	.probe		= keembay_emmc_phy_probe,
298 	.driver		= {
299 		.name	= "keembay-emmc-phy",
300 		.of_match_table = keembay_emmc_phy_dt_ids,
301 	},
302 };
303 module_platform_driver(keembay_emmc_phy_driver);
304 
305 MODULE_AUTHOR("Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>");
306 MODULE_DESCRIPTION("Intel Keem Bay eMMC PHY driver");
307 MODULE_LICENSE("GPL v2");
308