1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HiSilicon INNO USB2 PHY Driver. 4 * 5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/phy/phy.h> 14 #include <linux/reset.h> 15 16 #define INNO_PHY_PORT_NUM 2 17 #define REF_CLK_STABLE_TIME 100 /* unit:us */ 18 #define UTMI_CLK_STABLE_TIME 200 /* unit:us */ 19 #define TEST_CLK_STABLE_TIME 2 /* unit:ms */ 20 #define PHY_CLK_STABLE_TIME 2 /* unit:ms */ 21 #define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */ 22 #define POR_RST_COMPLETE_TIME 300 /* unit:us */ 23 24 #define PHY_TYPE_0 0 25 #define PHY_TYPE_1 1 26 27 #define PHY_TEST_DATA GENMASK(7, 0) 28 #define PHY_TEST_ADDR_OFFSET 8 29 #define PHY0_TEST_ADDR GENMASK(15, 8) 30 #define PHY0_TEST_PORT_OFFSET 16 31 #define PHY0_TEST_PORT GENMASK(18, 16) 32 #define PHY0_TEST_WREN BIT(21) 33 #define PHY0_TEST_CLK BIT(22) /* rising edge active */ 34 #define PHY0_TEST_RST BIT(23) /* low active */ 35 #define PHY1_TEST_ADDR GENMASK(11, 8) 36 #define PHY1_TEST_PORT_OFFSET 12 37 #define PHY1_TEST_PORT BIT(12) 38 #define PHY1_TEST_WREN BIT(13) 39 #define PHY1_TEST_CLK BIT(14) /* rising edge active */ 40 #define PHY1_TEST_RST BIT(15) /* low active */ 41 42 #define PHY_CLK_ENABLE BIT(2) 43 44 struct hisi_inno_phy_port { 45 struct reset_control *utmi_rst; 46 struct hisi_inno_phy_priv *priv; 47 }; 48 49 struct hisi_inno_phy_priv { 50 void __iomem *mmio; 51 struct clk *ref_clk; 52 struct reset_control *por_rst; 53 unsigned int type; 54 struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM]; 55 }; 56 57 static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv, 58 u8 port, u32 addr, u32 data) 59 { 60 void __iomem *reg = priv->mmio; 61 u32 val; 62 u32 value; 63 64 if (priv->type == PHY_TYPE_0) 65 val = (data & PHY_TEST_DATA) | 66 ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | 67 ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | 68 PHY0_TEST_WREN | PHY0_TEST_RST; 69 else 70 val = (data & PHY_TEST_DATA) | 71 ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | 72 ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | 73 PHY1_TEST_WREN | PHY1_TEST_RST; 74 writel(val, reg); 75 76 value = val; 77 if (priv->type == PHY_TYPE_0) 78 value |= PHY0_TEST_CLK; 79 else 80 value |= PHY1_TEST_CLK; 81 writel(value, reg); 82 83 writel(val, reg); 84 } 85 86 static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) 87 { 88 /* The phy clk is controlled by the port0 register 0x06. */ 89 hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE); 90 msleep(PHY_CLK_STABLE_TIME); 91 } 92 93 static int hisi_inno_phy_init(struct phy *phy) 94 { 95 struct hisi_inno_phy_port *port = phy_get_drvdata(phy); 96 struct hisi_inno_phy_priv *priv = port->priv; 97 int ret; 98 99 ret = clk_prepare_enable(priv->ref_clk); 100 if (ret) 101 return ret; 102 udelay(REF_CLK_STABLE_TIME); 103 104 reset_control_deassert(priv->por_rst); 105 udelay(POR_RST_COMPLETE_TIME); 106 107 /* Set up phy registers */ 108 hisi_inno_phy_setup(priv); 109 110 reset_control_deassert(port->utmi_rst); 111 udelay(UTMI_RST_COMPLETE_TIME); 112 113 return 0; 114 } 115 116 static int hisi_inno_phy_exit(struct phy *phy) 117 { 118 struct hisi_inno_phy_port *port = phy_get_drvdata(phy); 119 struct hisi_inno_phy_priv *priv = port->priv; 120 121 reset_control_assert(port->utmi_rst); 122 reset_control_assert(priv->por_rst); 123 clk_disable_unprepare(priv->ref_clk); 124 125 return 0; 126 } 127 128 static const struct phy_ops hisi_inno_phy_ops = { 129 .init = hisi_inno_phy_init, 130 .exit = hisi_inno_phy_exit, 131 .owner = THIS_MODULE, 132 }; 133 134 static int hisi_inno_phy_probe(struct platform_device *pdev) 135 { 136 struct device *dev = &pdev->dev; 137 struct device_node *np = dev->of_node; 138 struct hisi_inno_phy_priv *priv; 139 struct phy_provider *provider; 140 struct device_node *child; 141 int i = 0; 142 int ret; 143 144 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 145 if (!priv) 146 return -ENOMEM; 147 148 priv->mmio = devm_platform_ioremap_resource(pdev, 0); 149 if (IS_ERR(priv->mmio)) { 150 ret = PTR_ERR(priv->mmio); 151 return ret; 152 } 153 154 priv->ref_clk = devm_clk_get(dev, NULL); 155 if (IS_ERR(priv->ref_clk)) 156 return PTR_ERR(priv->ref_clk); 157 158 priv->por_rst = devm_reset_control_get_exclusive(dev, NULL); 159 if (IS_ERR(priv->por_rst)) 160 return PTR_ERR(priv->por_rst); 161 162 priv->type = (uintptr_t) of_device_get_match_data(dev); 163 164 for_each_child_of_node(np, child) { 165 struct reset_control *rst; 166 struct phy *phy; 167 168 rst = of_reset_control_get_exclusive(child, NULL); 169 if (IS_ERR(rst)) { 170 of_node_put(child); 171 return PTR_ERR(rst); 172 } 173 174 priv->ports[i].utmi_rst = rst; 175 priv->ports[i].priv = priv; 176 177 phy = devm_phy_create(dev, child, &hisi_inno_phy_ops); 178 if (IS_ERR(phy)) { 179 of_node_put(child); 180 return PTR_ERR(phy); 181 } 182 183 phy_set_bus_width(phy, 8); 184 phy_set_drvdata(phy, &priv->ports[i]); 185 i++; 186 187 if (i > INNO_PHY_PORT_NUM) { 188 dev_warn(dev, "Support %d ports in maximum\n", i); 189 of_node_put(child); 190 break; 191 } 192 } 193 194 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 195 return PTR_ERR_OR_ZERO(provider); 196 } 197 198 static const struct of_device_id hisi_inno_phy_of_match[] = { 199 { .compatible = "hisilicon,inno-usb2-phy", 200 .data = (void *) PHY_TYPE_0 }, 201 { .compatible = "hisilicon,hi3798cv200-usb2-phy", 202 .data = (void *) PHY_TYPE_0 }, 203 { .compatible = "hisilicon,hi3798mv100-usb2-phy", 204 .data = (void *) PHY_TYPE_1 }, 205 { }, 206 }; 207 MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match); 208 209 static struct platform_driver hisi_inno_phy_driver = { 210 .probe = hisi_inno_phy_probe, 211 .driver = { 212 .name = "hisi-inno-phy", 213 .of_match_table = hisi_inno_phy_of_match, 214 } 215 }; 216 module_platform_driver(hisi_inno_phy_driver); 217 218 MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver"); 219 MODULE_LICENSE("GPL v2"); 220