1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2021 NXP 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/delay.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 13 #include <linux/module.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 #include <dt-bindings/phy/phy-imx8-pcie.h> 19 20 #define IMX8MM_PCIE_PHY_CMN_REG061 0x184 21 #define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) 22 #define IMX8MM_PCIE_PHY_CMN_REG062 0x188 23 #define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) 24 #define IMX8MM_PCIE_PHY_CMN_REG063 0x18C 25 #define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) 26 #define IMX8MM_PCIE_PHY_CMN_REG064 0x190 27 #define ANA_AUX_RX_TX_SEL_TX BIT(7) 28 #define ANA_AUX_RX_TERM_GND_EN BIT(3) 29 #define ANA_AUX_TX_TERM BIT(2) 30 #define IMX8MM_PCIE_PHY_CMN_REG065 0x194 31 #define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) 32 #define ANA_AUX_TX_LVL GENMASK(3, 0) 33 #define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 34 #define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 35 #define PCIE_PHY_TRSV_REG5 0x414 36 #define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D 37 #define PCIE_PHY_TRSV_REG6 0x418 38 #define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF 39 40 #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) 41 #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) 42 #define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2) 43 #define IMX8MM_GPR_PCIE_AUX_EN BIT(19) 44 #define IMX8MM_GPR_PCIE_CMN_RST BIT(18) 45 #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) 46 #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) 47 #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9) 48 49 struct imx8_pcie_phy { 50 void __iomem *base; 51 struct clk *clk; 52 struct phy *phy; 53 struct regmap *iomuxc_gpr; 54 struct reset_control *reset; 55 u32 refclk_pad_mode; 56 u32 tx_deemph_gen1; 57 u32 tx_deemph_gen2; 58 bool clkreq_unused; 59 }; 60 61 static int imx8_pcie_phy_init(struct phy *phy) 62 { 63 int ret; 64 u32 val, pad_mode; 65 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); 66 67 reset_control_assert(imx8_phy->reset); 68 69 pad_mode = imx8_phy->refclk_pad_mode; 70 /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ 71 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 72 IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, 73 imx8_phy->clkreq_unused ? 74 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); 75 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 76 IMX8MM_GPR_PCIE_AUX_EN, 77 IMX8MM_GPR_PCIE_AUX_EN); 78 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 79 IMX8MM_GPR_PCIE_POWER_OFF, 0); 80 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 81 IMX8MM_GPR_PCIE_SSC_EN, 0); 82 83 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 84 IMX8MM_GPR_PCIE_REF_CLK_SEL, 85 pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ? 86 IMX8MM_GPR_PCIE_REF_CLK_EXT : 87 IMX8MM_GPR_PCIE_REF_CLK_PLL); 88 usleep_range(100, 200); 89 90 /* Do the PHY common block reset */ 91 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 92 IMX8MM_GPR_PCIE_CMN_RST, 93 IMX8MM_GPR_PCIE_CMN_RST); 94 usleep_range(200, 500); 95 96 if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { 97 /* Configure the pad as input */ 98 val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); 99 writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, 100 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); 101 } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { 102 /* Configure the PHY to output the refclock via pad */ 103 writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, 104 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); 105 writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, 106 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); 107 writel(AUX_PLL_REFCLK_SEL_SYS_PLL, 108 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); 109 val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; 110 writel(val | ANA_AUX_RX_TERM_GND_EN, 111 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); 112 writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, 113 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065); 114 } 115 116 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ 117 if (imx8_phy->tx_deemph_gen1) 118 writel(imx8_phy->tx_deemph_gen1, 119 imx8_phy->base + PCIE_PHY_TRSV_REG5); 120 if (imx8_phy->tx_deemph_gen2) 121 writel(imx8_phy->tx_deemph_gen2, 122 imx8_phy->base + PCIE_PHY_TRSV_REG6); 123 124 reset_control_deassert(imx8_phy->reset); 125 126 /* Polling to check the phy is ready or not. */ 127 ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75, 128 val, val == PCIE_PHY_CMN_REG75_PLL_DONE, 129 10, 20000); 130 return ret; 131 } 132 133 static int imx8_pcie_phy_power_on(struct phy *phy) 134 { 135 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); 136 137 return clk_prepare_enable(imx8_phy->clk); 138 } 139 140 static int imx8_pcie_phy_power_off(struct phy *phy) 141 { 142 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); 143 144 clk_disable_unprepare(imx8_phy->clk); 145 146 return 0; 147 } 148 149 static const struct phy_ops imx8_pcie_phy_ops = { 150 .init = imx8_pcie_phy_init, 151 .power_on = imx8_pcie_phy_power_on, 152 .power_off = imx8_pcie_phy_power_off, 153 .owner = THIS_MODULE, 154 }; 155 156 static int imx8_pcie_phy_probe(struct platform_device *pdev) 157 { 158 struct phy_provider *phy_provider; 159 struct device *dev = &pdev->dev; 160 struct device_node *np = dev->of_node; 161 struct imx8_pcie_phy *imx8_phy; 162 struct resource *res; 163 164 imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL); 165 if (!imx8_phy) 166 return -ENOMEM; 167 168 /* get PHY refclk pad mode */ 169 of_property_read_u32(np, "fsl,refclk-pad-mode", 170 &imx8_phy->refclk_pad_mode); 171 172 if (of_property_read_u32(np, "fsl,tx-deemph-gen1", 173 &imx8_phy->tx_deemph_gen1)) 174 imx8_phy->tx_deemph_gen1 = 0; 175 176 if (of_property_read_u32(np, "fsl,tx-deemph-gen2", 177 &imx8_phy->tx_deemph_gen2)) 178 imx8_phy->tx_deemph_gen2 = 0; 179 180 if (of_property_read_bool(np, "fsl,clkreq-unsupported")) 181 imx8_phy->clkreq_unused = true; 182 else 183 imx8_phy->clkreq_unused = false; 184 185 imx8_phy->clk = devm_clk_get(dev, "ref"); 186 if (IS_ERR(imx8_phy->clk)) { 187 dev_err(dev, "failed to get imx pcie phy clock\n"); 188 return PTR_ERR(imx8_phy->clk); 189 } 190 191 /* Grab GPR config register range */ 192 imx8_phy->iomuxc_gpr = 193 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 194 if (IS_ERR(imx8_phy->iomuxc_gpr)) { 195 dev_err(dev, "unable to find iomuxc registers\n"); 196 return PTR_ERR(imx8_phy->iomuxc_gpr); 197 } 198 199 imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy"); 200 if (IS_ERR(imx8_phy->reset)) { 201 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 202 return PTR_ERR(imx8_phy->reset); 203 } 204 205 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 206 imx8_phy->base = devm_ioremap_resource(dev, res); 207 if (IS_ERR(imx8_phy->base)) 208 return PTR_ERR(imx8_phy->base); 209 210 imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops); 211 if (IS_ERR(imx8_phy->phy)) 212 return PTR_ERR(imx8_phy->phy); 213 214 phy_set_drvdata(imx8_phy->phy, imx8_phy); 215 216 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 217 218 return PTR_ERR_OR_ZERO(phy_provider); 219 } 220 221 static const struct of_device_id imx8_pcie_phy_of_match[] = { 222 {.compatible = "fsl,imx8mm-pcie-phy",}, 223 { }, 224 }; 225 MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); 226 227 static struct platform_driver imx8_pcie_phy_driver = { 228 .probe = imx8_pcie_phy_probe, 229 .driver = { 230 .name = "imx8-pcie-phy", 231 .of_match_table = imx8_pcie_phy_of_match, 232 } 233 }; 234 module_platform_driver(imx8_pcie_phy_driver); 235 236 MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver"); 237 MODULE_LICENSE("GPL v2"); 238