1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cadence Torrent SD0801 PHY driver. 4 * 5 * Copyright 2018 Cadence Design Systems, Inc. 6 * 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/reset.h> 23 #include <linux/regmap.h> 24 25 #define REF_CLK_19_2MHz 19200000 26 #define REF_CLK_25MHz 25000000 27 28 #define DEFAULT_NUM_LANES 4 29 #define MAX_NUM_LANES 4 30 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ 31 32 #define POLL_TIMEOUT_US 5000 33 34 #define TORRENT_COMMON_CDB_OFFSET 0x0 35 36 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 37 ((0x4000 << (block_offset)) + \ 38 (((ln) << 9) << (reg_offset))) 39 40 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 41 ((0x8000 << (block_offset)) + \ 42 (((ln) << 9) << (reg_offset))) 43 44 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ 45 (0xC000 << (block_offset)) 46 47 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ 48 (0xE000 << (block_offset)) 49 50 #define TORRENT_DPTX_PHY_OFFSET 0x0 51 52 /* 53 * register offsets from DPTX PHY register block base (i.e MHDP 54 * register base + 0x30a00) 55 */ 56 #define PHY_AUX_CTRL 0x04 57 #define PHY_RESET 0x20 58 #define PMA_TX_ELEC_IDLE_MASK 0xF0U 59 #define PMA_TX_ELEC_IDLE_SHIFT 4 60 #define PHY_L00_RESET_N_MASK 0x01U 61 #define PHY_PMA_XCVR_PLLCLK_EN 0x24 62 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 63 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c 64 #define PHY_POWER_STATE_LN_0 0x0000 65 #define PHY_POWER_STATE_LN_1 0x0008 66 #define PHY_POWER_STATE_LN_2 0x0010 67 #define PHY_POWER_STATE_LN_3 0x0018 68 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU 69 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 70 #define PHY_PMA_CMN_READY 0x34 71 72 /* 73 * register offsets from SD0801 PHY register block base (i.e MHDP 74 * register base + 0x500000) 75 */ 76 #define CMN_SSM_BANDGAP_TMR 0x0021U 77 #define CMN_SSM_BIAS_TMR 0x0022U 78 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU 79 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU 80 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U 81 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U 82 #define CMN_BGCAL_INIT_TMR 0x0064U 83 #define CMN_BGCAL_ITER_TMR 0x0065U 84 #define CMN_IBCAL_INIT_TMR 0x0074U 85 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U 86 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U 87 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U 88 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U 89 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U 90 #define CMN_PLL0_INTDIV_M0 0x0090U 91 #define CMN_PLL0_FRACDIVL_M0 0x0091U 92 #define CMN_PLL0_FRACDIVH_M0 0x0092U 93 #define CMN_PLL0_HIGH_THR_M0 0x0093U 94 #define CMN_PLL0_DSM_DIAG_M0 0x0094U 95 #define CMN_PLL0_SS_CTRL1_M0 0x0098U 96 #define CMN_PLL0_SS_CTRL2_M0 0x0099U 97 #define CMN_PLL0_SS_CTRL3_M0 0x009AU 98 #define CMN_PLL0_SS_CTRL4_M0 0x009BU 99 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU 100 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU 101 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU 102 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U 103 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U 104 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U 105 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U 106 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U 107 #define CMN_PLL1_INTDIV_M0 0x00D0U 108 #define CMN_PLL1_FRACDIVL_M0 0x00D1U 109 #define CMN_PLL1_FRACDIVH_M0 0x00D2U 110 #define CMN_PLL1_HIGH_THR_M0 0x00D3U 111 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U 112 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U 113 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U 114 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU 115 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU 116 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU 117 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU 118 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU 119 #define CMN_TXPUCAL_INIT_TMR 0x0104U 120 #define CMN_TXPUCAL_ITER_TMR 0x0105U 121 #define CMN_TXPDCAL_INIT_TMR 0x010CU 122 #define CMN_TXPDCAL_ITER_TMR 0x010DU 123 #define CMN_RXCAL_INIT_TMR 0x0114U 124 #define CMN_RXCAL_ITER_TMR 0x0115U 125 #define CMN_SD_CAL_INIT_TMR 0x0124U 126 #define CMN_SD_CAL_ITER_TMR 0x0125U 127 #define CMN_SD_CAL_REFTIM_START 0x0126U 128 #define CMN_SD_CAL_PLLCNT_START 0x0128U 129 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U 130 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U 131 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U 132 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U 133 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U 134 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U 135 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U 136 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U 137 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U 138 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U 139 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U 140 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U 141 142 /* PMA TX Lane registers */ 143 #define TX_TXCC_CTRL 0x0040U 144 #define TX_TXCC_CPOST_MULT_00 0x004CU 145 #define TX_TXCC_MGNFS_MULT_000 0x0050U 146 #define DRV_DIAG_TX_DRV 0x00C6U 147 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U 148 #define XCVR_DIAG_HSCLK_SEL 0x00E6U 149 #define XCVR_DIAG_HSCLK_DIV 0x00E7U 150 #define XCVR_DIAG_BIDI_CTRL 0x00EAU 151 #define TX_PSC_A0 0x0100U 152 #define TX_PSC_A2 0x0102U 153 #define TX_PSC_A3 0x0103U 154 #define TX_RCVDET_ST_TMR 0x0123U 155 #define TX_DIAG_ACYA 0x01E7U 156 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U 157 158 /* PMA RX Lane registers */ 159 #define RX_PSC_A0 0x0000U 160 #define RX_PSC_A2 0x0002U 161 #define RX_PSC_A3 0x0003U 162 #define RX_PSC_CAL 0x0006U 163 #define RX_REE_GCSM1_CTRL 0x0108U 164 #define RX_REE_GCSM2_CTRL 0x0110U 165 #define RX_REE_PERGCSM_CTRL 0x0118U 166 167 /* PHY PCS common registers */ 168 #define PHY_PLL_CFG 0x000EU 169 170 /* PHY PMA common registers */ 171 #define PHY_PMA_CMN_CTRL2 0x0001U 172 #define PHY_PMA_PLL_RAW_CTRL 0x0003U 173 174 static const struct reg_field phy_pll_cfg = 175 REG_FIELD(PHY_PLL_CFG, 0, 1); 176 177 static const struct reg_field phy_pma_cmn_ctrl_2 = 178 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); 179 180 static const struct reg_field phy_pma_pll_raw_ctrl = 181 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1); 182 183 static const struct reg_field phy_reset_ctrl = 184 REG_FIELD(PHY_RESET, 8, 8); 185 186 static const struct of_device_id cdns_torrent_phy_of_match[]; 187 188 struct cdns_torrent_inst { 189 struct phy *phy; 190 u32 mlane; 191 u32 phy_type; 192 u32 num_lanes; 193 struct reset_control *lnk_rst; 194 }; 195 196 struct cdns_torrent_phy { 197 void __iomem *base; /* DPTX registers base */ 198 void __iomem *sd_base; /* SD0801 registers base */ 199 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ 200 struct reset_control *phy_rst; 201 struct device *dev; 202 struct clk *clk; 203 unsigned long ref_clk_rate; 204 struct cdns_torrent_inst phys[MAX_NUM_LANES]; 205 int nsubnodes; 206 struct regmap *regmap; 207 struct regmap *regmap_common_cdb; 208 struct regmap *regmap_phy_pcs_common_cdb; 209 struct regmap *regmap_phy_pma_common_cdb; 210 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES]; 211 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; 212 struct regmap *regmap_dptx_phy_reg; 213 struct regmap_field *phy_pll_cfg; 214 struct regmap_field *phy_pma_cmn_ctrl_2; 215 struct regmap_field *phy_pma_pll_raw_ctrl; 216 struct regmap_field *phy_reset_ctrl; 217 }; 218 219 enum phy_powerstate { 220 POWERSTATE_A0 = 0, 221 /* Powerstate A1 is unused */ 222 POWERSTATE_A2 = 2, 223 POWERSTATE_A3 = 3, 224 }; 225 226 static int cdns_torrent_dp_init(struct phy *phy); 227 static int cdns_torrent_dp_exit(struct phy *phy); 228 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, 229 u32 num_lanes); 230 static 231 int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy); 232 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy, 233 struct cdns_torrent_inst *inst); 234 static 235 void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy); 236 static 237 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, 238 u32 rate, bool ssc); 239 static 240 void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy); 241 static 242 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, 243 u32 rate, bool ssc); 244 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, 245 unsigned int lane); 246 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, 247 u32 rate, u32 num_lanes); 248 static int cdns_torrent_dp_configure(struct phy *phy, 249 union phy_configure_opts *opts); 250 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, 251 u32 num_lanes, 252 enum phy_powerstate powerstate); 253 static int cdns_torrent_phy_on(struct phy *phy); 254 static int cdns_torrent_phy_off(struct phy *phy); 255 256 static const struct phy_ops cdns_torrent_phy_ops = { 257 .init = cdns_torrent_dp_init, 258 .exit = cdns_torrent_dp_exit, 259 .configure = cdns_torrent_dp_configure, 260 .power_on = cdns_torrent_phy_on, 261 .power_off = cdns_torrent_phy_off, 262 .owner = THIS_MODULE, 263 }; 264 265 struct cdns_torrent_data { 266 u8 block_offset_shift; 267 u8 reg_offset_shift; 268 }; 269 270 struct cdns_regmap_cdb_context { 271 struct device *dev; 272 void __iomem *base; 273 u8 reg_offset_shift; 274 }; 275 276 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 277 { 278 struct cdns_regmap_cdb_context *ctx = context; 279 u32 offset = reg << ctx->reg_offset_shift; 280 281 writew(val, ctx->base + offset); 282 283 return 0; 284 } 285 286 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 287 { 288 struct cdns_regmap_cdb_context *ctx = context; 289 u32 offset = reg << ctx->reg_offset_shift; 290 291 *val = readw(ctx->base + offset); 292 return 0; 293 } 294 295 static int cdns_regmap_dptx_write(void *context, unsigned int reg, 296 unsigned int val) 297 { 298 struct cdns_regmap_cdb_context *ctx = context; 299 u32 offset = reg; 300 301 writel(val, ctx->base + offset); 302 303 return 0; 304 } 305 306 static int cdns_regmap_dptx_read(void *context, unsigned int reg, 307 unsigned int *val) 308 { 309 struct cdns_regmap_cdb_context *ctx = context; 310 u32 offset = reg; 311 312 *val = readl(ctx->base + offset); 313 return 0; 314 } 315 316 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \ 317 { \ 318 .name = "torrent_tx_lane" n "_cdb", \ 319 .reg_stride = 1, \ 320 .fast_io = true, \ 321 .reg_write = cdns_regmap_write, \ 322 .reg_read = cdns_regmap_read, \ 323 } 324 325 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \ 326 { \ 327 .name = "torrent_rx_lane" n "_cdb", \ 328 .reg_stride = 1, \ 329 .fast_io = true, \ 330 .reg_write = cdns_regmap_write, \ 331 .reg_read = cdns_regmap_read, \ 332 } 333 334 static struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { 335 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), 336 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), 337 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), 338 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), 339 }; 340 341 static struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { 342 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), 343 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), 344 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), 345 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), 346 }; 347 348 static struct regmap_config cdns_torrent_common_cdb_config = { 349 .name = "torrent_common_cdb", 350 .reg_stride = 1, 351 .fast_io = true, 352 .reg_write = cdns_regmap_write, 353 .reg_read = cdns_regmap_read, 354 }; 355 356 static struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { 357 .name = "torrent_phy_pcs_cmn_cdb", 358 .reg_stride = 1, 359 .fast_io = true, 360 .reg_write = cdns_regmap_write, 361 .reg_read = cdns_regmap_read, 362 }; 363 364 static struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { 365 .name = "torrent_phy_pma_cmn_cdb", 366 .reg_stride = 1, 367 .fast_io = true, 368 .reg_write = cdns_regmap_write, 369 .reg_read = cdns_regmap_read, 370 }; 371 372 static struct regmap_config cdns_torrent_dptx_phy_config = { 373 .name = "torrent_dptx_phy", 374 .reg_stride = 1, 375 .fast_io = true, 376 .reg_write = cdns_regmap_dptx_write, 377 .reg_read = cdns_regmap_dptx_read, 378 }; 379 380 /* PHY mmr access functions */ 381 382 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) 383 { 384 regmap_write(regmap, offset, val); 385 } 386 387 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) 388 { 389 unsigned int val; 390 391 regmap_read(regmap, offset, &val); 392 return val; 393 } 394 395 /* DPTX mmr access functions */ 396 397 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val) 398 { 399 regmap_write(regmap, offset, val); 400 } 401 402 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset) 403 { 404 u32 val; 405 406 regmap_read(regmap, offset, &val); 407 return val; 408 } 409 410 /* 411 * Structure used to store values of PHY registers for voltage-related 412 * coefficients, for particular voltage swing and pre-emphasis level. Values 413 * are shared across all physical lanes. 414 */ 415 struct coefficients { 416 /* Value of DRV_DIAG_TX_DRV register to use */ 417 u16 diag_tx_drv; 418 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */ 419 u16 mgnfs_mult; 420 /* Value of TX_TXCC_CPOST_MULT_00 register to use */ 421 u16 cpost_mult; 422 }; 423 424 /* 425 * Array consists of values of voltage-related registers for sd0801 PHY. A value 426 * of 0xFFFF is a placeholder for invalid combination, and will never be used. 427 */ 428 static const struct coefficients vltg_coeff[4][4] = { 429 /* voltage swing 0, pre-emphasis 0->3 */ 430 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A, 431 .cpost_mult = 0x0000}, 432 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 433 .cpost_mult = 0x0014}, 434 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012, 435 .cpost_mult = 0x0020}, 436 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 437 .cpost_mult = 0x002A} 438 }, 439 440 /* voltage swing 1, pre-emphasis 0->3 */ 441 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 442 .cpost_mult = 0x0000}, 443 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 444 .cpost_mult = 0x0012}, 445 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 446 .cpost_mult = 0x001F}, 447 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 448 .cpost_mult = 0xFFFF} 449 }, 450 451 /* voltage swing 2, pre-emphasis 0->3 */ 452 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 453 .cpost_mult = 0x0000}, 454 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 455 .cpost_mult = 0x0013}, 456 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 457 .cpost_mult = 0xFFFF}, 458 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 459 .cpost_mult = 0xFFFF} 460 }, 461 462 /* voltage swing 3, pre-emphasis 0->3 */ 463 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 464 .cpost_mult = 0x0000}, 465 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 466 .cpost_mult = 0xFFFF}, 467 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 468 .cpost_mult = 0xFFFF}, 469 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 470 .cpost_mult = 0xFFFF} 471 } 472 }; 473 474 /* 475 * Enable or disable PLL for selected lanes. 476 */ 477 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, 478 struct phy_configure_opts_dp *dp, 479 bool enable) 480 { 481 u32 rd_val; 482 u32 ret; 483 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 484 485 /* 486 * Used to determine, which bits to check for or enable in 487 * PHY_PMA_XCVR_PLLCLK_EN register. 488 */ 489 u32 pll_bits; 490 /* Used to enable or disable lanes. */ 491 u32 pll_val; 492 493 /* Select values of registers and mask, depending on enabled lane 494 * count. 495 */ 496 switch (dp->lanes) { 497 /* lane 0 */ 498 case (1): 499 pll_bits = 0x00000001; 500 break; 501 /* lanes 0-1 */ 502 case (2): 503 pll_bits = 0x00000003; 504 break; 505 /* lanes 0-3, all */ 506 default: 507 pll_bits = 0x0000000F; 508 break; 509 } 510 511 if (enable) 512 pll_val = pll_bits; 513 else 514 pll_val = 0x00000000; 515 516 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val); 517 518 /* Wait for acknowledgment from PHY. */ 519 ret = regmap_read_poll_timeout(regmap, 520 PHY_PMA_XCVR_PLLCLK_EN_ACK, 521 rd_val, 522 (rd_val & pll_bits) == pll_val, 523 0, POLL_TIMEOUT_US); 524 ndelay(100); 525 return ret; 526 } 527 528 /* 529 * Perform register operations related to setting link rate, once powerstate is 530 * set and PLL disable request was processed. 531 */ 532 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, 533 struct phy_configure_opts_dp *dp) 534 { 535 u32 ret; 536 u32 read_val; 537 538 /* Disable the cmn_pll0_en before re-programming the new data rate. */ 539 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0); 540 541 /* 542 * Wait for PLL ready de-assertion. 543 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 544 */ 545 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 546 read_val, 547 ((read_val >> 2) & 0x01) != 0, 548 0, POLL_TIMEOUT_US); 549 if (ret) 550 return ret; 551 ndelay(200); 552 553 /* DP Rate Change - VCO Output settings. */ 554 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) { 555 /* PMA common configuration 19.2MHz */ 556 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, 557 dp->ssc); 558 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy); 559 } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) { 560 /* PMA common configuration 25MHz */ 561 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, 562 dp->ssc); 563 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy); 564 } 565 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes); 566 567 /* Enable the cmn_pll0_en. */ 568 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3); 569 570 /* 571 * Wait for PLL ready assertion. 572 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 573 */ 574 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 575 read_val, 576 (read_val & 0x01) != 0, 577 0, POLL_TIMEOUT_US); 578 return ret; 579 } 580 581 /* 582 * Verify, that parameters to configure PHY with are correct. 583 */ 584 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst, 585 struct phy_configure_opts_dp *dp) 586 { 587 u8 i; 588 589 /* If changing link rate was required, verify it's supported. */ 590 if (dp->set_rate) { 591 switch (dp->link_rate) { 592 case 1620: 593 case 2160: 594 case 2430: 595 case 2700: 596 case 3240: 597 case 4320: 598 case 5400: 599 case 8100: 600 /* valid bit rate */ 601 break; 602 default: 603 return -EINVAL; 604 } 605 } 606 607 /* Verify lane count. */ 608 switch (dp->lanes) { 609 case 1: 610 case 2: 611 case 4: 612 /* valid lane count. */ 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 /* Check against actual number of PHY's lanes. */ 619 if (dp->lanes > inst->num_lanes) 620 return -EINVAL; 621 622 /* 623 * If changing voltages is required, check swing and pre-emphasis 624 * levels, per-lane. 625 */ 626 if (dp->set_voltages) { 627 /* Lane count verified previously. */ 628 for (i = 0; i < dp->lanes; i++) { 629 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 630 return -EINVAL; 631 632 /* Sum of voltage swing and pre-emphasis levels cannot 633 * exceed 3. 634 */ 635 if (dp->voltage[i] + dp->pre[i] > 3) 636 return -EINVAL; 637 } 638 } 639 640 return 0; 641 } 642 643 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ 644 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, 645 u32 num_lanes) 646 { 647 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 648 u32 pwr_state = cdns_torrent_dp_read(regmap, 649 PHY_PMA_XCVR_POWER_STATE_REQ); 650 u32 pll_clk_en = cdns_torrent_dp_read(regmap, 651 PHY_PMA_XCVR_PLLCLK_EN); 652 653 /* Lane 0 is always enabled. */ 654 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 655 PHY_POWER_STATE_LN_0); 656 pll_clk_en &= ~0x01U; 657 658 if (num_lanes > 1) { 659 /* lane 1 */ 660 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 661 PHY_POWER_STATE_LN_1); 662 pll_clk_en &= ~(0x01U << 1); 663 } 664 665 if (num_lanes > 2) { 666 /* lanes 2 and 3 */ 667 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 668 PHY_POWER_STATE_LN_2); 669 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 670 PHY_POWER_STATE_LN_3); 671 pll_clk_en &= ~(0x01U << 2); 672 pll_clk_en &= ~(0x01U << 3); 673 } 674 675 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state); 676 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en); 677 } 678 679 /* Configure lane count as required. */ 680 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, 681 struct phy_configure_opts_dp *dp) 682 { 683 u32 value; 684 u32 ret; 685 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 686 u8 lane_mask = (1 << dp->lanes) - 1; 687 688 value = cdns_torrent_dp_read(regmap, PHY_RESET); 689 /* clear pma_tx_elec_idle_ln_* bits. */ 690 value &= ~PMA_TX_ELEC_IDLE_MASK; 691 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */ 692 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & 693 PMA_TX_ELEC_IDLE_MASK; 694 cdns_torrent_dp_write(regmap, PHY_RESET, value); 695 696 /* reset the link by asserting phy_l00_reset_n low */ 697 cdns_torrent_dp_write(regmap, PHY_RESET, 698 value & (~PHY_L00_RESET_N_MASK)); 699 700 /* 701 * Assert lane reset on unused lanes and lane 0 so they remain in reset 702 * and powered down when re-enabling the link 703 */ 704 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask); 705 cdns_torrent_dp_write(regmap, PHY_RESET, value); 706 707 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes); 708 709 /* release phy_l0*_reset_n based on used laneCount */ 710 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask); 711 cdns_torrent_dp_write(regmap, PHY_RESET, value); 712 713 /* Wait, until PHY gets ready after releasing PHY reset signal. */ 714 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 715 if (ret) 716 return ret; 717 718 ndelay(100); 719 720 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 721 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); 722 723 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes); 724 725 return ret; 726 } 727 728 /* Configure link rate as required. */ 729 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, 730 struct phy_configure_opts_dp *dp) 731 { 732 u32 ret; 733 734 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 735 POWERSTATE_A3); 736 if (ret) 737 return ret; 738 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false); 739 if (ret) 740 return ret; 741 ndelay(200); 742 743 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp); 744 if (ret) 745 return ret; 746 ndelay(200); 747 748 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true); 749 if (ret) 750 return ret; 751 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 752 POWERSTATE_A2); 753 if (ret) 754 return ret; 755 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 756 POWERSTATE_A0); 757 if (ret) 758 return ret; 759 ndelay(900); 760 761 return ret; 762 } 763 764 /* Configure voltage swing and pre-emphasis for all enabled lanes. */ 765 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, 766 struct phy_configure_opts_dp *dp) 767 { 768 u8 lane; 769 u16 val; 770 771 for (lane = 0; lane < dp->lanes; lane++) { 772 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], 773 TX_DIAG_ACYA); 774 /* 775 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the 776 * current state of the analog TX driver. 777 */ 778 val |= TX_DIAG_ACYA_HBDC_MASK; 779 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 780 TX_DIAG_ACYA, val); 781 782 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 783 TX_TXCC_CTRL, 0x08A4); 784 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; 785 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 786 DRV_DIAG_TX_DRV, val); 787 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; 788 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 789 TX_TXCC_MGNFS_MULT_000, 790 val); 791 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; 792 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 793 TX_TXCC_CPOST_MULT_00, 794 val); 795 796 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], 797 TX_DIAG_ACYA); 798 /* 799 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of 800 * analog TX driver to reflect the new programmed one. 801 */ 802 val &= ~TX_DIAG_ACYA_HBDC_MASK; 803 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 804 TX_DIAG_ACYA, val); 805 } 806 }; 807 808 static int cdns_torrent_dp_configure(struct phy *phy, 809 union phy_configure_opts *opts) 810 { 811 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 812 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 813 int ret; 814 815 ret = cdns_torrent_dp_verify_config(inst, &opts->dp); 816 if (ret) { 817 dev_err(&phy->dev, "invalid params for phy configure\n"); 818 return ret; 819 } 820 821 if (opts->dp.set_lanes) { 822 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp); 823 if (ret) { 824 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n"); 825 return ret; 826 } 827 } 828 829 if (opts->dp.set_rate) { 830 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp); 831 if (ret) { 832 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n"); 833 return ret; 834 } 835 } 836 837 if (opts->dp.set_voltages) 838 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp); 839 840 return ret; 841 } 842 843 static int cdns_torrent_dp_init(struct phy *phy) 844 { 845 unsigned char lane_bits; 846 int ret; 847 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 848 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 849 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 850 851 ret = clk_prepare_enable(cdns_phy->clk); 852 if (ret) { 853 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); 854 return ret; 855 } 856 857 cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); 858 if (!(cdns_phy->ref_clk_rate)) { 859 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); 860 clk_disable_unprepare(cdns_phy->clk); 861 return -EINVAL; 862 } 863 864 switch (cdns_phy->ref_clk_rate) { 865 case REF_CLK_19_2MHz: 866 case REF_CLK_25MHz: 867 /* Valid Ref Clock Rate */ 868 break; 869 default: 870 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); 871 return -EINVAL; 872 } 873 874 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */ 875 876 /* PHY PMA registers configuration function */ 877 cdns_torrent_dp_pma_cfg(cdns_phy, inst); 878 879 /* 880 * Set lines power state to A0 881 * Set lines pll clk enable to 0 882 */ 883 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes); 884 885 /* 886 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on 887 * used lanes 888 */ 889 lane_bits = (1 << inst->num_lanes) - 1; 890 cdns_torrent_dp_write(regmap, PHY_RESET, 891 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits)); 892 893 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 894 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); 895 896 /* PHY PMA registers configuration functions */ 897 /* Initialize PHY with max supported link rate, without SSC. */ 898 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) 899 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, 900 cdns_phy->max_bit_rate, 901 false); 902 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) 903 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, 904 cdns_phy->max_bit_rate, 905 false); 906 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate, 907 inst->num_lanes); 908 909 /* take out of reset */ 910 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1); 911 912 cdns_torrent_phy_on(phy); 913 914 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 915 if (ret) 916 return ret; 917 918 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes); 919 920 return ret; 921 } 922 923 static int cdns_torrent_dp_exit(struct phy *phy) 924 { 925 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 926 927 clk_disable_unprepare(cdns_phy->clk); 928 return 0; 929 } 930 931 static 932 int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) 933 { 934 unsigned int reg; 935 int ret; 936 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 937 938 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg, 939 reg & 1, 0, POLL_TIMEOUT_US); 940 if (ret == -ETIMEDOUT) { 941 dev_err(cdns_phy->dev, 942 "timeout waiting for PMA common ready\n"); 943 return -ETIMEDOUT; 944 } 945 946 return 0; 947 } 948 949 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy, 950 struct cdns_torrent_inst *inst) 951 { 952 unsigned int i; 953 954 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) 955 /* PMA common configuration 19.2MHz */ 956 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy); 957 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) 958 /* PMA common configuration 25MHz */ 959 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy); 960 961 /* PMA lane configuration to deal with multi-link operation */ 962 for (i = 0; i < inst->num_lanes; i++) 963 cdns_torrent_dp_pma_lane_cfg(cdns_phy, i); 964 } 965 966 static 967 void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy) 968 { 969 struct regmap *regmap = cdns_phy->regmap_common_cdb; 970 971 /* refclock registers - assumes 19.2 MHz refclock */ 972 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014); 973 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027); 974 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1); 975 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027); 976 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1); 977 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060); 978 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060); 979 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014); 980 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018); 981 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005); 982 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018); 983 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005); 984 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240); 985 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005); 986 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002); 987 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002); 988 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B); 989 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137); 990 991 /* PLL registers */ 992 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 993 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 994 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 995 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 996 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 997 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 998 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 999 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 1000 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0); 1001 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); 1002 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0); 1003 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); 1004 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260); 1005 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003); 1006 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260); 1007 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003); 1008 } 1009 1010 /* 1011 * Set registers responsible for enabling and configuring SSC, with second and 1012 * third register values provided by parameters. 1013 */ 1014 static 1015 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, 1016 u32 ctrl2_val, u32 ctrl3_val) 1017 { 1018 struct regmap *regmap = cdns_phy->regmap_common_cdb; 1019 1020 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 1021 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 1022 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); 1023 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 1024 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 1025 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 1026 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); 1027 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 1028 } 1029 1030 static 1031 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, 1032 u32 rate, bool ssc) 1033 { 1034 struct regmap *regmap = cdns_phy->regmap_common_cdb; 1035 1036 /* Assumes 19.2 MHz refclock */ 1037 switch (rate) { 1038 /* Setting VCO for 10.8GHz */ 1039 case 2700: 1040 case 5400: 1041 cdns_torrent_phy_write(regmap, 1042 CMN_PLL0_INTDIV_M0, 0x0119); 1043 cdns_torrent_phy_write(regmap, 1044 CMN_PLL0_FRACDIVL_M0, 0x4000); 1045 cdns_torrent_phy_write(regmap, 1046 CMN_PLL0_FRACDIVH_M0, 0x0002); 1047 cdns_torrent_phy_write(regmap, 1048 CMN_PLL0_HIGH_THR_M0, 0x00BC); 1049 cdns_torrent_phy_write(regmap, 1050 CMN_PDIAG_PLL0_CTRL_M0, 0x0012); 1051 cdns_torrent_phy_write(regmap, 1052 CMN_PLL1_INTDIV_M0, 0x0119); 1053 cdns_torrent_phy_write(regmap, 1054 CMN_PLL1_FRACDIVL_M0, 0x4000); 1055 cdns_torrent_phy_write(regmap, 1056 CMN_PLL1_FRACDIVH_M0, 0x0002); 1057 cdns_torrent_phy_write(regmap, 1058 CMN_PLL1_HIGH_THR_M0, 0x00BC); 1059 cdns_torrent_phy_write(regmap, 1060 CMN_PDIAG_PLL1_CTRL_M0, 0x0012); 1061 if (ssc) 1062 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 1063 0x006A); 1064 break; 1065 /* Setting VCO for 9.72GHz */ 1066 case 1620: 1067 case 2430: 1068 case 3240: 1069 cdns_torrent_phy_write(regmap, 1070 CMN_PLL0_INTDIV_M0, 0x01FA); 1071 cdns_torrent_phy_write(regmap, 1072 CMN_PLL0_FRACDIVL_M0, 0x4000); 1073 cdns_torrent_phy_write(regmap, 1074 CMN_PLL0_FRACDIVH_M0, 0x0002); 1075 cdns_torrent_phy_write(regmap, 1076 CMN_PLL0_HIGH_THR_M0, 0x0152); 1077 cdns_torrent_phy_write(regmap, 1078 CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1079 cdns_torrent_phy_write(regmap, 1080 CMN_PLL1_INTDIV_M0, 0x01FA); 1081 cdns_torrent_phy_write(regmap, 1082 CMN_PLL1_FRACDIVL_M0, 0x4000); 1083 cdns_torrent_phy_write(regmap, 1084 CMN_PLL1_FRACDIVH_M0, 0x0002); 1085 cdns_torrent_phy_write(regmap, 1086 CMN_PLL1_HIGH_THR_M0, 0x0152); 1087 cdns_torrent_phy_write(regmap, 1088 CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1089 if (ssc) 1090 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 1091 0x0069); 1092 break; 1093 /* Setting VCO for 8.64GHz */ 1094 case 2160: 1095 case 4320: 1096 cdns_torrent_phy_write(regmap, 1097 CMN_PLL0_INTDIV_M0, 0x01C2); 1098 cdns_torrent_phy_write(regmap, 1099 CMN_PLL0_FRACDIVL_M0, 0x0000); 1100 cdns_torrent_phy_write(regmap, 1101 CMN_PLL0_FRACDIVH_M0, 0x0002); 1102 cdns_torrent_phy_write(regmap, 1103 CMN_PLL0_HIGH_THR_M0, 0x012C); 1104 cdns_torrent_phy_write(regmap, 1105 CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1106 cdns_torrent_phy_write(regmap, 1107 CMN_PLL1_INTDIV_M0, 0x01C2); 1108 cdns_torrent_phy_write(regmap, 1109 CMN_PLL1_FRACDIVL_M0, 0x0000); 1110 cdns_torrent_phy_write(regmap, 1111 CMN_PLL1_FRACDIVH_M0, 0x0002); 1112 cdns_torrent_phy_write(regmap, 1113 CMN_PLL1_HIGH_THR_M0, 0x012C); 1114 cdns_torrent_phy_write(regmap, 1115 CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1116 if (ssc) 1117 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 1118 0x0069); 1119 break; 1120 /* Setting VCO for 8.1GHz */ 1121 case 8100: 1122 cdns_torrent_phy_write(regmap, 1123 CMN_PLL0_INTDIV_M0, 0x01A5); 1124 cdns_torrent_phy_write(regmap, 1125 CMN_PLL0_FRACDIVL_M0, 0xE000); 1126 cdns_torrent_phy_write(regmap, 1127 CMN_PLL0_FRACDIVH_M0, 0x0002); 1128 cdns_torrent_phy_write(regmap, 1129 CMN_PLL0_HIGH_THR_M0, 0x011A); 1130 cdns_torrent_phy_write(regmap, 1131 CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1132 cdns_torrent_phy_write(regmap, 1133 CMN_PLL1_INTDIV_M0, 0x01A5); 1134 cdns_torrent_phy_write(regmap, 1135 CMN_PLL1_FRACDIVL_M0, 0xE000); 1136 cdns_torrent_phy_write(regmap, 1137 CMN_PLL1_FRACDIVH_M0, 0x0002); 1138 cdns_torrent_phy_write(regmap, 1139 CMN_PLL1_HIGH_THR_M0, 0x011A); 1140 cdns_torrent_phy_write(regmap, 1141 CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1142 if (ssc) 1143 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 1144 0x006A); 1145 break; 1146 } 1147 1148 if (ssc) { 1149 cdns_torrent_phy_write(regmap, 1150 CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); 1151 cdns_torrent_phy_write(regmap, 1152 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 1153 cdns_torrent_phy_write(regmap, 1154 CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); 1155 cdns_torrent_phy_write(regmap, 1156 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 1157 } else { 1158 cdns_torrent_phy_write(regmap, 1159 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); 1160 cdns_torrent_phy_write(regmap, 1161 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); 1162 /* Set reset register values to disable SSC */ 1163 cdns_torrent_phy_write(regmap, 1164 CMN_PLL0_SS_CTRL1_M0, 0x0002); 1165 cdns_torrent_phy_write(regmap, 1166 CMN_PLL0_SS_CTRL2_M0, 0x0000); 1167 cdns_torrent_phy_write(regmap, 1168 CMN_PLL0_SS_CTRL3_M0, 0x0000); 1169 cdns_torrent_phy_write(regmap, 1170 CMN_PLL0_SS_CTRL4_M0, 0x0000); 1171 cdns_torrent_phy_write(regmap, 1172 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 1173 cdns_torrent_phy_write(regmap, 1174 CMN_PLL1_SS_CTRL1_M0, 0x0002); 1175 cdns_torrent_phy_write(regmap, 1176 CMN_PLL1_SS_CTRL2_M0, 0x0000); 1177 cdns_torrent_phy_write(regmap, 1178 CMN_PLL1_SS_CTRL3_M0, 0x0000); 1179 cdns_torrent_phy_write(regmap, 1180 CMN_PLL1_SS_CTRL4_M0, 0x0000); 1181 cdns_torrent_phy_write(regmap, 1182 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 1183 } 1184 1185 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099); 1186 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); 1187 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099); 1188 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); 1189 } 1190 1191 static 1192 void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) 1193 { 1194 struct regmap *regmap = cdns_phy->regmap_common_cdb; 1195 1196 /* refclock registers - assumes 25 MHz refclock */ 1197 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019); 1198 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032); 1199 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1); 1200 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032); 1201 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1); 1202 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D); 1203 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D); 1204 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019); 1205 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E); 1206 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006); 1207 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E); 1208 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006); 1209 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE); 1210 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006); 1211 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002); 1212 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002); 1213 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E); 1214 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B); 1215 1216 /* PLL registers */ 1217 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 1218 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 1219 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 1220 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 1221 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 1222 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 1223 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 1224 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 1225 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA); 1226 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); 1227 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA); 1228 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); 1229 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317); 1230 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003); 1231 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317); 1232 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003); 1233 } 1234 1235 /* 1236 * Set registers responsible for enabling and configuring SSC, with second 1237 * register value provided by a parameter. 1238 */ 1239 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, 1240 u32 ctrl2_val) 1241 { 1242 struct regmap *regmap = cdns_phy->regmap_common_cdb; 1243 1244 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 1245 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 1246 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F); 1247 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 1248 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 1249 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 1250 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F); 1251 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 1252 } 1253 1254 static 1255 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, 1256 u32 rate, bool ssc) 1257 { 1258 struct regmap *regmap = cdns_phy->regmap_common_cdb; 1259 1260 /* Assumes 25 MHz refclock */ 1261 switch (rate) { 1262 /* Setting VCO for 10.8GHz */ 1263 case 2700: 1264 case 5400: 1265 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0); 1266 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 1267 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1268 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120); 1269 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0); 1270 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 1271 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1272 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120); 1273 if (ssc) 1274 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); 1275 break; 1276 /* Setting VCO for 9.72GHz */ 1277 case 1620: 1278 case 2430: 1279 case 3240: 1280 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184); 1281 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD); 1282 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1283 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104); 1284 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184); 1285 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD); 1286 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1287 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104); 1288 if (ssc) 1289 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); 1290 break; 1291 /* Setting VCO for 8.64GHz */ 1292 case 2160: 1293 case 4320: 1294 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159); 1295 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A); 1296 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1297 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7); 1298 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159); 1299 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A); 1300 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1301 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7); 1302 if (ssc) 1303 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); 1304 break; 1305 /* Setting VCO for 8.1GHz */ 1306 case 8100: 1307 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144); 1308 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 1309 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1310 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8); 1311 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144); 1312 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 1313 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1314 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8); 1315 if (ssc) 1316 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); 1317 break; 1318 } 1319 1320 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1321 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1322 1323 if (ssc) { 1324 cdns_torrent_phy_write(regmap, 1325 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); 1326 cdns_torrent_phy_write(regmap, 1327 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 1328 cdns_torrent_phy_write(regmap, 1329 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); 1330 cdns_torrent_phy_write(regmap, 1331 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 1332 } else { 1333 cdns_torrent_phy_write(regmap, 1334 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); 1335 cdns_torrent_phy_write(regmap, 1336 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); 1337 /* Set reset register values to disable SSC */ 1338 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 1339 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 1340 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 1341 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 1342 cdns_torrent_phy_write(regmap, 1343 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 1344 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 1345 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 1346 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 1347 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 1348 cdns_torrent_phy_write(regmap, 1349 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 1350 } 1351 1352 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); 1353 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); 1354 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); 1355 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); 1356 } 1357 1358 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, 1359 u32 rate, u32 num_lanes) 1360 { 1361 unsigned int clk_sel_val = 0; 1362 unsigned int hsclk_div_val = 0; 1363 unsigned int i; 1364 1365 /* 16'h0000 for single DP link configuration */ 1366 regmap_field_write(cdns_phy->phy_pll_cfg, 0x0); 1367 1368 switch (rate) { 1369 case 1620: 1370 clk_sel_val = 0x0f01; 1371 hsclk_div_val = 2; 1372 break; 1373 case 2160: 1374 case 2430: 1375 case 2700: 1376 clk_sel_val = 0x0701; 1377 hsclk_div_val = 1; 1378 break; 1379 case 3240: 1380 clk_sel_val = 0x0b00; 1381 hsclk_div_val = 2; 1382 break; 1383 case 4320: 1384 case 5400: 1385 clk_sel_val = 0x0301; 1386 hsclk_div_val = 0; 1387 break; 1388 case 8100: 1389 clk_sel_val = 0x0200; 1390 hsclk_div_val = 0; 1391 break; 1392 } 1393 1394 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1395 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); 1396 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1397 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); 1398 1399 /* PMA lane configuration to deal with multi-link operation */ 1400 for (i = 0; i < num_lanes; i++) 1401 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i], 1402 XCVR_DIAG_HSCLK_DIV, hsclk_div_val); 1403 } 1404 1405 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, 1406 unsigned int lane) 1407 { 1408 /* Per lane, refclock-dependent receiver detection setting */ 1409 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) 1410 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1411 TX_RCVDET_ST_TMR, 0x0780); 1412 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) 1413 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1414 TX_RCVDET_ST_TMR, 0x09C4); 1415 1416 /* Writing Tx/Rx Power State Controllers registers */ 1417 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1418 TX_PSC_A0, 0x00FB); 1419 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1420 TX_PSC_A2, 0x04AA); 1421 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1422 TX_PSC_A3, 0x04AA); 1423 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], 1424 RX_PSC_A0, 0x0000); 1425 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], 1426 RX_PSC_A2, 0x0000); 1427 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], 1428 RX_PSC_A3, 0x0000); 1429 1430 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], 1431 RX_PSC_CAL, 0x0000); 1432 1433 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], 1434 RX_REE_GCSM1_CTRL, 0x0000); 1435 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], 1436 RX_REE_GCSM2_CTRL, 0x0000); 1437 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], 1438 RX_REE_PERGCSM_CTRL, 0x0000); 1439 1440 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1441 XCVR_DIAG_BIDI_CTRL, 0x000F); 1442 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1443 XCVR_DIAG_PLLDRC_CTRL, 0x0001); 1444 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1445 XCVR_DIAG_HSCLK_SEL, 0x0000); 1446 } 1447 1448 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, 1449 u32 num_lanes, 1450 enum phy_powerstate powerstate) 1451 { 1452 /* Register value for power state for a single byte. */ 1453 u32 value_part; 1454 u32 value; 1455 u32 mask; 1456 u32 read_val; 1457 u32 ret; 1458 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1459 1460 switch (powerstate) { 1461 case (POWERSTATE_A0): 1462 value_part = 0x01U; 1463 break; 1464 case (POWERSTATE_A2): 1465 value_part = 0x04U; 1466 break; 1467 default: 1468 /* Powerstate A3 */ 1469 value_part = 0x08U; 1470 break; 1471 } 1472 1473 /* Select values of registers and mask, depending on enabled 1474 * lane count. 1475 */ 1476 switch (num_lanes) { 1477 /* lane 0 */ 1478 case (1): 1479 value = value_part; 1480 mask = 0x0000003FU; 1481 break; 1482 /* lanes 0-1 */ 1483 case (2): 1484 value = (value_part 1485 | (value_part << 8)); 1486 mask = 0x00003F3FU; 1487 break; 1488 /* lanes 0-3, all */ 1489 default: 1490 value = (value_part 1491 | (value_part << 8) 1492 | (value_part << 16) 1493 | (value_part << 24)); 1494 mask = 0x3F3F3F3FU; 1495 break; 1496 } 1497 1498 /* Set power state A<n>. */ 1499 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value); 1500 /* Wait, until PHY acknowledges power state completion. */ 1501 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK, 1502 read_val, (read_val & mask) == value, 0, 1503 POLL_TIMEOUT_US); 1504 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000); 1505 ndelay(100); 1506 1507 return ret; 1508 } 1509 1510 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) 1511 { 1512 unsigned int read_val; 1513 int ret; 1514 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1515 1516 /* 1517 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the 1518 * master lane 1519 */ 1520 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK, 1521 read_val, read_val & 1, 1522 0, POLL_TIMEOUT_US); 1523 if (ret == -ETIMEDOUT) { 1524 dev_err(cdns_phy->dev, 1525 "timeout waiting for link PLL clock enable ack\n"); 1526 return ret; 1527 } 1528 1529 ndelay(100); 1530 1531 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, 1532 POWERSTATE_A2); 1533 if (ret) 1534 return ret; 1535 1536 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, 1537 POWERSTATE_A0); 1538 1539 return ret; 1540 } 1541 1542 static int cdns_torrent_phy_on(struct phy *phy) 1543 { 1544 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1545 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1546 int ret; 1547 1548 /* Take the PHY out of reset */ 1549 ret = reset_control_deassert(cdns_phy->phy_rst); 1550 if (ret) 1551 return ret; 1552 1553 /* Take the PHY lane group out of reset */ 1554 return reset_control_deassert(inst->lnk_rst); 1555 } 1556 1557 static int cdns_torrent_phy_off(struct phy *phy) 1558 { 1559 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1560 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1561 int ret; 1562 1563 ret = reset_control_assert(cdns_phy->phy_rst); 1564 if (ret) 1565 return ret; 1566 1567 return reset_control_assert(inst->lnk_rst); 1568 } 1569 1570 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 1571 u32 block_offset, 1572 u8 reg_offset_shift, 1573 const struct regmap_config *config) 1574 { 1575 struct cdns_regmap_cdb_context *ctx; 1576 1577 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1578 if (!ctx) 1579 return ERR_PTR(-ENOMEM); 1580 1581 ctx->dev = dev; 1582 ctx->base = base + block_offset; 1583 ctx->reg_offset_shift = reg_offset_shift; 1584 1585 return devm_regmap_init(dev, NULL, ctx, config); 1586 } 1587 1588 static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy) 1589 { 1590 struct device *dev = cdns_phy->dev; 1591 struct regmap_field *field; 1592 struct regmap *regmap; 1593 1594 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 1595 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg); 1596 if (IS_ERR(field)) { 1597 dev_err(dev, "PHY_PLL_CFG reg field init failed\n"); 1598 return PTR_ERR(field); 1599 } 1600 cdns_phy->phy_pll_cfg = field; 1601 1602 regmap = cdns_phy->regmap_phy_pma_common_cdb; 1603 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); 1604 if (IS_ERR(field)) { 1605 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); 1606 return PTR_ERR(field); 1607 } 1608 cdns_phy->phy_pma_cmn_ctrl_2 = field; 1609 1610 regmap = cdns_phy->regmap_phy_pma_common_cdb; 1611 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl); 1612 if (IS_ERR(field)) { 1613 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n"); 1614 return PTR_ERR(field); 1615 } 1616 cdns_phy->phy_pma_pll_raw_ctrl = field; 1617 1618 regmap = cdns_phy->regmap_dptx_phy_reg; 1619 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); 1620 if (IS_ERR(field)) { 1621 dev_err(dev, "PHY_RESET reg field init failed\n"); 1622 return PTR_ERR(field); 1623 } 1624 cdns_phy->phy_reset_ctrl = field; 1625 1626 return 0; 1627 } 1628 1629 static int cdns_regmap_init_torrent_dp(struct cdns_torrent_phy *cdns_phy, 1630 void __iomem *sd_base, 1631 void __iomem *base, 1632 u8 block_offset_shift, 1633 u8 reg_offset_shift) 1634 { 1635 struct device *dev = cdns_phy->dev; 1636 struct regmap *regmap; 1637 u32 block_offset; 1638 int i; 1639 1640 for (i = 0; i < MAX_NUM_LANES; i++) { 1641 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift, 1642 reg_offset_shift); 1643 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1644 reg_offset_shift, 1645 &cdns_torrent_tx_lane_cdb_config[i]); 1646 if (IS_ERR(regmap)) { 1647 dev_err(dev, "Failed to init tx lane CDB regmap\n"); 1648 return PTR_ERR(regmap); 1649 } 1650 cdns_phy->regmap_tx_lane_cdb[i] = regmap; 1651 1652 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift, 1653 reg_offset_shift); 1654 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1655 reg_offset_shift, 1656 &cdns_torrent_rx_lane_cdb_config[i]); 1657 if (IS_ERR(regmap)) { 1658 dev_err(dev, "Failed to init rx lane CDB regmap\n"); 1659 return PTR_ERR(regmap); 1660 } 1661 cdns_phy->regmap_rx_lane_cdb[i] = regmap; 1662 } 1663 1664 block_offset = TORRENT_COMMON_CDB_OFFSET; 1665 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1666 reg_offset_shift, 1667 &cdns_torrent_common_cdb_config); 1668 if (IS_ERR(regmap)) { 1669 dev_err(dev, "Failed to init common CDB regmap\n"); 1670 return PTR_ERR(regmap); 1671 } 1672 cdns_phy->regmap_common_cdb = regmap; 1673 1674 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift); 1675 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1676 reg_offset_shift, 1677 &cdns_torrent_phy_pcs_cmn_cdb_config); 1678 if (IS_ERR(regmap)) { 1679 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 1680 return PTR_ERR(regmap); 1681 } 1682 cdns_phy->regmap_phy_pcs_common_cdb = regmap; 1683 1684 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift); 1685 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1686 reg_offset_shift, 1687 &cdns_torrent_phy_pma_cmn_cdb_config); 1688 if (IS_ERR(regmap)) { 1689 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 1690 return PTR_ERR(regmap); 1691 } 1692 cdns_phy->regmap_phy_pma_common_cdb = regmap; 1693 1694 block_offset = TORRENT_DPTX_PHY_OFFSET; 1695 regmap = cdns_regmap_init(dev, base, block_offset, 1696 reg_offset_shift, 1697 &cdns_torrent_dptx_phy_config); 1698 if (IS_ERR(regmap)) { 1699 dev_err(dev, "Failed to init DPTX PHY regmap\n"); 1700 return PTR_ERR(regmap); 1701 } 1702 cdns_phy->regmap_dptx_phy_reg = regmap; 1703 1704 return 0; 1705 } 1706 1707 static int cdns_torrent_phy_probe(struct platform_device *pdev) 1708 { 1709 struct resource *regs; 1710 struct cdns_torrent_phy *cdns_phy; 1711 struct device *dev = &pdev->dev; 1712 struct phy_provider *phy_provider; 1713 const struct of_device_id *match; 1714 struct cdns_torrent_data *data; 1715 struct device_node *child; 1716 int ret, subnodes, node = 0, i; 1717 1718 /* Get init data for this PHY */ 1719 match = of_match_device(cdns_torrent_phy_of_match, dev); 1720 if (!match) 1721 return -EINVAL; 1722 1723 data = (struct cdns_torrent_data *)match->data; 1724 1725 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); 1726 if (!cdns_phy) 1727 return -ENOMEM; 1728 1729 dev_set_drvdata(dev, cdns_phy); 1730 cdns_phy->dev = dev; 1731 1732 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); 1733 if (IS_ERR(cdns_phy->phy_rst)) { 1734 dev_err(dev, "%s: failed to get reset\n", 1735 dev->of_node->full_name); 1736 return PTR_ERR(cdns_phy->phy_rst); 1737 } 1738 1739 cdns_phy->clk = devm_clk_get(dev, "refclk"); 1740 if (IS_ERR(cdns_phy->clk)) { 1741 dev_err(dev, "phy ref clock not found\n"); 1742 return PTR_ERR(cdns_phy->clk); 1743 } 1744 1745 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1746 cdns_phy->sd_base = devm_ioremap_resource(&pdev->dev, regs); 1747 if (IS_ERR(cdns_phy->sd_base)) 1748 return PTR_ERR(cdns_phy->sd_base); 1749 1750 subnodes = of_get_available_child_count(dev->of_node); 1751 if (subnodes == 0) { 1752 dev_err(dev, "No available link subnodes found\n"); 1753 return -EINVAL; 1754 } else if (subnodes != 1) { 1755 dev_err(dev, "Driver supports only one link subnode.\n"); 1756 return -EINVAL; 1757 } 1758 1759 for_each_available_child_of_node(dev->of_node, child) { 1760 struct phy *gphy; 1761 1762 cdns_phy->phys[node].lnk_rst = 1763 of_reset_control_array_get_exclusive(child); 1764 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) { 1765 dev_err(dev, "%s: failed to get reset\n", 1766 child->full_name); 1767 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst); 1768 goto put_lnk_rst; 1769 } 1770 1771 if (of_property_read_u32(child, "reg", 1772 &cdns_phy->phys[node].mlane)) { 1773 dev_err(dev, "%s: No \"reg\"-property.\n", 1774 child->full_name); 1775 ret = -EINVAL; 1776 goto put_child; 1777 } 1778 1779 if (cdns_phy->phys[node].mlane != 0) { 1780 dev_err(dev, 1781 "%s: Driver supports only lane-0 as master lane.\n", 1782 child->full_name); 1783 ret = -EINVAL; 1784 goto put_child; 1785 } 1786 1787 if (of_property_read_u32(child, "cdns,phy-type", 1788 &cdns_phy->phys[node].phy_type)) { 1789 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n", 1790 child->full_name); 1791 ret = -EINVAL; 1792 goto put_child; 1793 } 1794 1795 cdns_phy->phys[node].num_lanes = DEFAULT_NUM_LANES; 1796 of_property_read_u32(child, "cdns,num-lanes", 1797 &cdns_phy->phys[node].num_lanes); 1798 1799 if (cdns_phy->phys[node].phy_type == PHY_TYPE_DP) { 1800 switch (cdns_phy->phys[node].num_lanes) { 1801 case 1: 1802 case 2: 1803 case 4: 1804 /* valid number of lanes */ 1805 break; 1806 default: 1807 dev_err(dev, "unsupported number of lanes: %d\n", 1808 cdns_phy->phys[node].num_lanes); 1809 ret = -EINVAL; 1810 goto put_child; 1811 } 1812 1813 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; 1814 of_property_read_u32(child, "cdns,max-bit-rate", 1815 &cdns_phy->max_bit_rate); 1816 1817 switch (cdns_phy->max_bit_rate) { 1818 case 1620: 1819 case 2160: 1820 case 2430: 1821 case 2700: 1822 case 3240: 1823 case 4320: 1824 case 5400: 1825 case 8100: 1826 /* valid bit rate */ 1827 break; 1828 default: 1829 dev_err(dev, "unsupported max bit rate: %dMbps\n", 1830 cdns_phy->max_bit_rate); 1831 ret = -EINVAL; 1832 goto put_child; 1833 } 1834 1835 /* DPTX registers */ 1836 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1837 cdns_phy->base = devm_ioremap_resource(&pdev->dev, 1838 regs); 1839 if (IS_ERR(cdns_phy->base)) { 1840 ret = PTR_ERR(cdns_phy->base); 1841 goto put_child; 1842 } 1843 1844 gphy = devm_phy_create(dev, child, 1845 &cdns_torrent_phy_ops); 1846 if (IS_ERR(gphy)) { 1847 ret = PTR_ERR(gphy); 1848 goto put_child; 1849 } 1850 1851 dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n", 1852 cdns_phy->phys[node].num_lanes, 1853 cdns_phy->max_bit_rate / 1000, 1854 cdns_phy->max_bit_rate % 1000); 1855 } else { 1856 dev_err(dev, "Driver supports only PHY_TYPE_DP\n"); 1857 ret = -ENOTSUPP; 1858 goto put_child; 1859 } 1860 cdns_phy->phys[node].phy = gphy; 1861 phy_set_drvdata(gphy, &cdns_phy->phys[node]); 1862 1863 node++; 1864 } 1865 cdns_phy->nsubnodes = node; 1866 1867 ret = cdns_regmap_init_torrent_dp(cdns_phy, cdns_phy->sd_base, 1868 cdns_phy->base, 1869 data->block_offset_shift, 1870 data->reg_offset_shift); 1871 if (ret) 1872 goto put_lnk_rst; 1873 1874 ret = cdns_regfield_init(cdns_phy); 1875 if (ret) 1876 goto put_lnk_rst; 1877 1878 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1879 if (IS_ERR(phy_provider)) { 1880 ret = PTR_ERR(phy_provider); 1881 goto put_lnk_rst; 1882 } 1883 1884 return 0; 1885 1886 put_child: 1887 node++; 1888 put_lnk_rst: 1889 for (i = 0; i < node; i++) 1890 reset_control_put(cdns_phy->phys[i].lnk_rst); 1891 of_node_put(child); 1892 return ret; 1893 } 1894 1895 static int cdns_torrent_phy_remove(struct platform_device *pdev) 1896 { 1897 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev); 1898 int i; 1899 1900 reset_control_assert(cdns_phy->phy_rst); 1901 for (i = 0; i < cdns_phy->nsubnodes; i++) { 1902 reset_control_assert(cdns_phy->phys[i].lnk_rst); 1903 reset_control_put(cdns_phy->phys[i].lnk_rst); 1904 } 1905 1906 return 0; 1907 } 1908 1909 static const struct cdns_torrent_data cdns_map_torrent = { 1910 .block_offset_shift = 0x2, 1911 .reg_offset_shift = 0x2, 1912 }; 1913 1914 static const struct cdns_torrent_data ti_j721e_map_torrent = { 1915 .block_offset_shift = 0x0, 1916 .reg_offset_shift = 0x1, 1917 }; 1918 1919 static const struct of_device_id cdns_torrent_phy_of_match[] = { 1920 { 1921 .compatible = "cdns,torrent-phy", 1922 .data = &cdns_map_torrent, 1923 }, 1924 { 1925 .compatible = "ti,j721e-serdes-10g", 1926 .data = &ti_j721e_map_torrent, 1927 }, 1928 {} 1929 }; 1930 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); 1931 1932 static struct platform_driver cdns_torrent_phy_driver = { 1933 .probe = cdns_torrent_phy_probe, 1934 .remove = cdns_torrent_phy_remove, 1935 .driver = { 1936 .name = "cdns-torrent-phy", 1937 .of_match_table = cdns_torrent_phy_of_match, 1938 } 1939 }; 1940 module_platform_driver(cdns_torrent_phy_driver); 1941 1942 MODULE_AUTHOR("Cadence Design Systems, Inc."); 1943 MODULE_DESCRIPTION("Cadence Torrent PHY driver"); 1944 MODULE_LICENSE("GPL v2"); 1945