1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cadence Torrent SD0801 PHY driver. 4 * 5 * Copyright 2018 Cadence Design Systems, Inc. 6 * 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-cadence.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/reset.h> 23 #include <linux/regmap.h> 24 25 #define REF_CLK_19_2MHZ 19200000 26 #define REF_CLK_25MHZ 25000000 27 #define REF_CLK_100MHZ 100000000 28 #define REF_CLK_156_25MHZ 156250000 29 30 #define MAX_NUM_LANES 4 31 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ 32 33 #define POLL_TIMEOUT_US 5000 34 #define PLL_LOCK_TIMEOUT 100000 35 36 #define DP_PLL0 BIT(0) 37 #define DP_PLL1 BIT(1) 38 39 #define TORRENT_COMMON_CDB_OFFSET 0x0 40 41 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 42 ((0x4000 << (block_offset)) + \ 43 (((ln) << 9) << (reg_offset))) 44 45 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 46 ((0x8000 << (block_offset)) + \ 47 (((ln) << 9) << (reg_offset))) 48 49 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ 50 (0xC000 << (block_offset)) 51 52 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 53 ((0xD000 << (block_offset)) + \ 54 (((ln) << 8) << (reg_offset))) 55 56 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ 57 (0xE000 << (block_offset)) 58 59 #define TORRENT_DPTX_PHY_OFFSET 0x0 60 61 /* 62 * register offsets from DPTX PHY register block base (i.e MHDP 63 * register base + 0x30a00) 64 */ 65 #define PHY_AUX_CTRL 0x04 66 #define PHY_RESET 0x20 67 #define PMA_TX_ELEC_IDLE_SHIFT 4 68 #define PHY_PMA_XCVR_PLLCLK_EN 0x24 69 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 70 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c 71 #define PHY_POWER_STATE_LN(ln) ((ln) * 8) 72 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU 73 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 74 #define PHY_PMA_CMN_READY 0x34 75 76 /* 77 * register offsets from SD0801 PHY register block base (i.e MHDP 78 * register base + 0x500000) 79 */ 80 #define CMN_SSM_BANDGAP_TMR 0x0021U 81 #define CMN_SSM_BIAS_TMR 0x0022U 82 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU 83 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU 84 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U 85 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U 86 #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U 87 #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U 88 #define CMN_CDIAG_REFCLK_OVRD 0x004CU 89 #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U 90 #define CMN_BGCAL_INIT_TMR 0x0064U 91 #define CMN_BGCAL_ITER_TMR 0x0065U 92 #define CMN_IBCAL_INIT_TMR 0x0074U 93 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U 94 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U 95 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U 96 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U 97 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U 98 #define CMN_PLL0_INTDIV_M0 0x0090U 99 #define CMN_PLL0_FRACDIVL_M0 0x0091U 100 #define CMN_PLL0_FRACDIVH_M0 0x0092U 101 #define CMN_PLL0_HIGH_THR_M0 0x0093U 102 #define CMN_PLL0_DSM_DIAG_M0 0x0094U 103 #define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U 104 #define CMN_PLL0_DSM_FBL_OVRD_M0 0x0096U 105 #define CMN_PLL0_SS_CTRL1_M0 0x0098U 106 #define CMN_PLL0_SS_CTRL2_M0 0x0099U 107 #define CMN_PLL0_SS_CTRL3_M0 0x009AU 108 #define CMN_PLL0_SS_CTRL4_M0 0x009BU 109 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU 110 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU 111 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU 112 #define CMN_PLL0_INTDIV_M1 0x00A0U 113 #define CMN_PLL0_FRACDIVH_M1 0x00A2U 114 #define CMN_PLL0_HIGH_THR_M1 0x00A3U 115 #define CMN_PLL0_DSM_DIAG_M1 0x00A4U 116 #define CMN_PLL0_SS_CTRL1_M1 0x00A8U 117 #define CMN_PLL0_SS_CTRL2_M1 0x00A9U 118 #define CMN_PLL0_SS_CTRL3_M1 0x00AAU 119 #define CMN_PLL0_SS_CTRL4_M1 0x00ABU 120 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U 121 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U 122 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U 123 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U 124 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U 125 #define CMN_PLL1_INTDIV_M0 0x00D0U 126 #define CMN_PLL1_FRACDIVL_M0 0x00D1U 127 #define CMN_PLL1_FRACDIVH_M0 0x00D2U 128 #define CMN_PLL1_HIGH_THR_M0 0x00D3U 129 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U 130 #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U 131 #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U 132 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U 133 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U 134 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU 135 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU 136 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU 137 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU 138 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU 139 #define CMN_TXPUCAL_TUNE 0x0103U 140 #define CMN_TXPUCAL_INIT_TMR 0x0104U 141 #define CMN_TXPUCAL_ITER_TMR 0x0105U 142 #define CMN_TXPDCAL_TUNE 0x010BU 143 #define CMN_TXPDCAL_INIT_TMR 0x010CU 144 #define CMN_TXPDCAL_ITER_TMR 0x010DU 145 #define CMN_RXCAL_INIT_TMR 0x0114U 146 #define CMN_RXCAL_ITER_TMR 0x0115U 147 #define CMN_SD_CAL_INIT_TMR 0x0124U 148 #define CMN_SD_CAL_ITER_TMR 0x0125U 149 #define CMN_SD_CAL_REFTIM_START 0x0126U 150 #define CMN_SD_CAL_PLLCNT_START 0x0128U 151 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U 152 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U 153 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U 154 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U 155 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U 156 #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U 157 #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U 158 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U 159 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U 160 #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U 161 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U 162 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U 163 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U 164 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U 165 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U 166 #define CMN_DIAG_BIAS_OVRD1 0x01E1U 167 168 /* PMA TX Lane registers */ 169 #define TX_TXCC_CTRL 0x0040U 170 #define TX_TXCC_CPOST_MULT_00 0x004CU 171 #define TX_TXCC_CPOST_MULT_01 0x004DU 172 #define TX_TXCC_MGNFS_MULT_000 0x0050U 173 #define TX_TXCC_MGNFS_MULT_100 0x0054U 174 #define DRV_DIAG_TX_DRV 0x00C6U 175 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U 176 #define XCVR_DIAG_HSCLK_SEL 0x00E6U 177 #define XCVR_DIAG_HSCLK_DIV 0x00E7U 178 #define XCVR_DIAG_RXCLK_CTRL 0x00E9U 179 #define XCVR_DIAG_BIDI_CTRL 0x00EAU 180 #define XCVR_DIAG_PSC_OVRD 0x00EBU 181 #define TX_PSC_A0 0x0100U 182 #define TX_PSC_A1 0x0101U 183 #define TX_PSC_A2 0x0102U 184 #define TX_PSC_A3 0x0103U 185 #define TX_RCVDET_ST_TMR 0x0123U 186 #define TX_DIAG_ACYA 0x01E7U 187 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U 188 189 /* PMA RX Lane registers */ 190 #define RX_PSC_A0 0x0000U 191 #define RX_PSC_A1 0x0001U 192 #define RX_PSC_A2 0x0002U 193 #define RX_PSC_A3 0x0003U 194 #define RX_PSC_CAL 0x0006U 195 #define RX_SDCAL0_INIT_TMR 0x0044U 196 #define RX_SDCAL0_ITER_TMR 0x0045U 197 #define RX_SDCAL1_INIT_TMR 0x004CU 198 #define RX_SDCAL1_ITER_TMR 0x004DU 199 #define RX_CDRLF_CNFG 0x0080U 200 #define RX_CDRLF_CNFG3 0x0082U 201 #define RX_SIGDET_HL_FILT_TMR 0x0090U 202 #define RX_REE_GCSM1_CTRL 0x0108U 203 #define RX_REE_GCSM1_EQENM_PH1 0x0109U 204 #define RX_REE_GCSM1_EQENM_PH2 0x010AU 205 #define RX_REE_GCSM2_CTRL 0x0110U 206 #define RX_REE_PERGCSM_CTRL 0x0118U 207 #define RX_REE_ATTEN_THR 0x0149U 208 #define RX_REE_TAP1_CLIP 0x0171U 209 #define RX_REE_TAP2TON_CLIP 0x0172U 210 #define RX_REE_SMGM_CTRL1 0x0177U 211 #define RX_REE_SMGM_CTRL2 0x0178U 212 #define RX_DIAG_DFE_CTRL 0x01E0U 213 #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U 214 #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U 215 #define RX_DIAG_NQST_CTRL 0x01E5U 216 #define RX_DIAG_SIGDET_TUNE 0x01E8U 217 #define RX_DIAG_PI_RATE 0x01F4U 218 #define RX_DIAG_PI_CAP 0x01F5U 219 #define RX_DIAG_ACYA 0x01FFU 220 221 /* PHY PCS common registers */ 222 #define PHY_PIPE_CMN_CTRL1 0x0000U 223 #define PHY_PLL_CFG 0x000EU 224 #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U 225 #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U 226 #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U 227 228 /* PHY PCS lane registers */ 229 #define PHY_PCS_ISO_LINK_CTRL 0x000BU 230 231 /* PHY PMA common registers */ 232 #define PHY_PMA_CMN_CTRL1 0x0000U 233 #define PHY_PMA_CMN_CTRL2 0x0001U 234 #define PHY_PMA_PLL_RAW_CTRL 0x0003U 235 236 #define CDNS_TORRENT_OUTPUT_CLOCKS 3 237 238 static const char * const clk_names[] = { 239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver", 240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der", 241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec", 242 }; 243 244 static const struct reg_field phy_pll_cfg = 245 REG_FIELD(PHY_PLL_CFG, 0, 1); 246 247 static const struct reg_field phy_pma_cmn_ctrl_1 = 248 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0); 249 250 static const struct reg_field phy_pma_cmn_ctrl_2 = 251 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); 252 253 static const struct reg_field phy_pma_pll_raw_ctrl = 254 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1); 255 256 static const struct reg_field phy_reset_ctrl = 257 REG_FIELD(PHY_RESET, 8, 8); 258 259 static const struct reg_field phy_pcs_iso_link_ctrl_1 = 260 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1); 261 262 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0); 263 264 static const struct reg_field cmn_cdiag_refclk_ovrd_4 = 265 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4); 266 267 #define REFCLK_OUT_NUM_CMN_CONFIG 4 268 269 enum cdns_torrent_refclk_out_cmn { 270 CMN_CDIAG_REFCLK_DRV0_CTRL_1, 271 CMN_CDIAG_REFCLK_DRV0_CTRL_4, 272 CMN_CDIAG_REFCLK_DRV0_CTRL_5, 273 CMN_CDIAG_REFCLK_DRV0_CTRL_6, 274 }; 275 276 static const struct reg_field refclk_out_cmn_cfg[] = { 277 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1), 278 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4), 279 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5), 280 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6), 281 }; 282 283 static const int refclk_driver_parent_index[] = { 284 CDNS_TORRENT_DERIVED_REFCLK, 285 CDNS_TORRENT_RECEIVED_REFCLK 286 }; 287 288 static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 }; 289 290 enum cdns_torrent_phy_type { 291 TYPE_NONE, 292 TYPE_DP, 293 TYPE_PCIE, 294 TYPE_SGMII, 295 TYPE_QSGMII, 296 TYPE_USB, 297 TYPE_USXGMII, 298 }; 299 300 enum cdns_torrent_ref_clk { 301 CLK_19_2_MHZ, 302 CLK_25_MHZ, 303 CLK_100_MHZ, 304 CLK_156_25_MHZ, 305 CLK_ANY, 306 }; 307 308 enum cdns_torrent_ssc_mode { 309 NO_SSC, 310 EXTERNAL_SSC, 311 INTERNAL_SSC, 312 ANY_SSC, 313 }; 314 315 /* Unique key id for vals table entry 316 * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE 317 */ 318 #define REFCLK0_SHIFT 12 319 #define REFCLK0_MASK GENMASK(14, 12) 320 #define REFCLK1_SHIFT 9 321 #define REFCLK1_MASK GENMASK(11, 9) 322 #define LINK0_SHIFT 6 323 #define LINK0_MASK GENMASK(8, 6) 324 #define LINK1_SHIFT 3 325 #define LINK1_MASK GENMASK(5, 3) 326 #define SSC_SHIFT 0 327 #define SSC_MASK GENMASK(2, 0) 328 329 #define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \ 330 ((((refclk0) << REFCLK0_SHIFT) & REFCLK0_MASK) | \ 331 (((refclk1) << REFCLK1_SHIFT) & REFCLK1_MASK) | \ 332 (((link0) << LINK0_SHIFT) & LINK0_MASK) | \ 333 (((link1) << LINK1_SHIFT) & LINK1_MASK) | \ 334 (((ssc) << SSC_SHIFT) & SSC_MASK)) 335 336 #define CDNS_TORRENT_KEY_ANYCLK(link0, link1) \ 337 CDNS_TORRENT_KEY(CLK_ANY, CLK_ANY, \ 338 (link0), (link1), ANY_SSC) 339 340 struct cdns_torrent_inst { 341 struct phy *phy; 342 u32 mlane; 343 enum cdns_torrent_phy_type phy_type; 344 u32 num_lanes; 345 struct reset_control *lnk_rst; 346 enum cdns_torrent_ssc_mode ssc_mode; 347 }; 348 349 struct cdns_torrent_phy { 350 void __iomem *base; /* DPTX registers base */ 351 void __iomem *sd_base; /* SD0801 registers base */ 352 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ 353 u32 dp_pll; 354 struct reset_control *phy_rst; 355 struct reset_control *apb_rst; 356 struct device *dev; 357 struct clk *clk; 358 enum cdns_torrent_ref_clk ref_clk_rate; 359 struct cdns_torrent_inst phys[MAX_NUM_LANES]; 360 int nsubnodes; 361 const struct cdns_torrent_data *init_data; 362 struct regmap *regmap_common_cdb; 363 struct regmap *regmap_phy_pcs_common_cdb; 364 struct regmap *regmap_phy_pma_common_cdb; 365 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES]; 366 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; 367 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES]; 368 struct regmap *regmap_dptx_phy_reg; 369 struct regmap_field *phy_pll_cfg; 370 struct regmap_field *phy_pipe_cmn_ctrl1_0; 371 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 372 struct regmap_field *phy_pma_cmn_ctrl_1; 373 struct regmap_field *phy_pma_cmn_ctrl_2; 374 struct regmap_field *phy_pma_pll_raw_ctrl; 375 struct regmap_field *phy_reset_ctrl; 376 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES]; 377 struct clk_hw_onecell_data *clk_hw_data; 378 }; 379 380 enum phy_powerstate { 381 POWERSTATE_A0 = 0, 382 /* Powerstate A1 is unused */ 383 POWERSTATE_A2 = 2, 384 POWERSTATE_A3 = 3, 385 }; 386 387 struct cdns_torrent_refclk_driver { 388 struct clk_hw hw; 389 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG]; 390 struct clk_init_data clk_data; 391 }; 392 393 #define to_cdns_torrent_refclk_driver(_hw) \ 394 container_of(_hw, struct cdns_torrent_refclk_driver, hw) 395 396 struct cdns_torrent_derived_refclk { 397 struct clk_hw hw; 398 struct regmap_field *phy_pipe_cmn_ctrl1_0; 399 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 400 struct clk_init_data clk_data; 401 }; 402 403 #define to_cdns_torrent_derived_refclk(_hw) \ 404 container_of(_hw, struct cdns_torrent_derived_refclk, hw) 405 406 struct cdns_torrent_received_refclk { 407 struct clk_hw hw; 408 struct regmap_field *phy_pipe_cmn_ctrl1_0; 409 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 410 struct clk_init_data clk_data; 411 }; 412 413 #define to_cdns_torrent_received_refclk(_hw) \ 414 container_of(_hw, struct cdns_torrent_received_refclk, hw) 415 416 struct cdns_reg_pairs { 417 u32 val; 418 u32 off; 419 }; 420 421 struct cdns_torrent_vals { 422 struct cdns_reg_pairs *reg_pairs; 423 u32 num_regs; 424 }; 425 426 struct cdns_torrent_vals_entry { 427 u32 key; 428 struct cdns_torrent_vals *vals; 429 }; 430 431 struct cdns_torrent_vals_table { 432 struct cdns_torrent_vals_entry *entries; 433 u32 num_entries; 434 }; 435 436 struct cdns_torrent_data { 437 u8 block_offset_shift; 438 u8 reg_offset_shift; 439 struct cdns_torrent_vals_table link_cmn_vals_tbl; 440 struct cdns_torrent_vals_table xcvr_diag_vals_tbl; 441 struct cdns_torrent_vals_table pcs_cmn_vals_tbl; 442 struct cdns_torrent_vals_table phy_pma_cmn_vals_tbl; 443 struct cdns_torrent_vals_table cmn_vals_tbl; 444 struct cdns_torrent_vals_table tx_ln_vals_tbl; 445 struct cdns_torrent_vals_table rx_ln_vals_tbl; 446 }; 447 448 struct cdns_regmap_cdb_context { 449 struct device *dev; 450 void __iomem *base; 451 u8 reg_offset_shift; 452 }; 453 454 static struct cdns_torrent_vals *cdns_torrent_get_tbl_vals(const struct cdns_torrent_vals_table *tbl, 455 enum cdns_torrent_ref_clk refclk0, 456 enum cdns_torrent_ref_clk refclk1, 457 enum cdns_torrent_phy_type link0, 458 enum cdns_torrent_phy_type link1, 459 enum cdns_torrent_ssc_mode ssc) 460 { 461 int i; 462 u32 key = CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc); 463 464 for (i = 0; i < tbl->num_entries; i++) { 465 if (tbl->entries[i].key == key) 466 return tbl->entries[i].vals; 467 } 468 469 return NULL; 470 } 471 472 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 473 { 474 struct cdns_regmap_cdb_context *ctx = context; 475 u32 offset = reg << ctx->reg_offset_shift; 476 477 writew(val, ctx->base + offset); 478 479 return 0; 480 } 481 482 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 483 { 484 struct cdns_regmap_cdb_context *ctx = context; 485 u32 offset = reg << ctx->reg_offset_shift; 486 487 *val = readw(ctx->base + offset); 488 return 0; 489 } 490 491 static int cdns_regmap_dptx_write(void *context, unsigned int reg, 492 unsigned int val) 493 { 494 struct cdns_regmap_cdb_context *ctx = context; 495 u32 offset = reg; 496 497 writel(val, ctx->base + offset); 498 499 return 0; 500 } 501 502 static int cdns_regmap_dptx_read(void *context, unsigned int reg, 503 unsigned int *val) 504 { 505 struct cdns_regmap_cdb_context *ctx = context; 506 u32 offset = reg; 507 508 *val = readl(ctx->base + offset); 509 return 0; 510 } 511 512 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \ 513 { \ 514 .name = "torrent_tx_lane" n "_cdb", \ 515 .reg_stride = 1, \ 516 .fast_io = true, \ 517 .reg_write = cdns_regmap_write, \ 518 .reg_read = cdns_regmap_read, \ 519 } 520 521 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \ 522 { \ 523 .name = "torrent_rx_lane" n "_cdb", \ 524 .reg_stride = 1, \ 525 .fast_io = true, \ 526 .reg_write = cdns_regmap_write, \ 527 .reg_read = cdns_regmap_read, \ 528 } 529 530 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { 531 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), 532 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), 533 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), 534 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), 535 }; 536 537 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { 538 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), 539 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), 540 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), 541 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), 542 }; 543 544 static const struct regmap_config cdns_torrent_common_cdb_config = { 545 .name = "torrent_common_cdb", 546 .reg_stride = 1, 547 .fast_io = true, 548 .reg_write = cdns_regmap_write, 549 .reg_read = cdns_regmap_read, 550 }; 551 552 #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ 553 { \ 554 .name = "torrent_phy_pcs_lane" n "_cdb", \ 555 .reg_stride = 1, \ 556 .fast_io = true, \ 557 .reg_write = cdns_regmap_write, \ 558 .reg_read = cdns_regmap_read, \ 559 } 560 561 static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = { 562 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), 563 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), 564 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), 565 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), 566 }; 567 568 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { 569 .name = "torrent_phy_pcs_cmn_cdb", 570 .reg_stride = 1, 571 .fast_io = true, 572 .reg_write = cdns_regmap_write, 573 .reg_read = cdns_regmap_read, 574 }; 575 576 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { 577 .name = "torrent_phy_pma_cmn_cdb", 578 .reg_stride = 1, 579 .fast_io = true, 580 .reg_write = cdns_regmap_write, 581 .reg_read = cdns_regmap_read, 582 }; 583 584 static const struct regmap_config cdns_torrent_dptx_phy_config = { 585 .name = "torrent_dptx_phy", 586 .reg_stride = 1, 587 .fast_io = true, 588 .reg_write = cdns_regmap_dptx_write, 589 .reg_read = cdns_regmap_dptx_read, 590 }; 591 592 /* PHY mmr access functions */ 593 594 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) 595 { 596 regmap_write(regmap, offset, val); 597 } 598 599 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) 600 { 601 unsigned int val; 602 603 regmap_read(regmap, offset, &val); 604 return val; 605 } 606 607 /* DPTX mmr access functions */ 608 609 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val) 610 { 611 regmap_write(regmap, offset, val); 612 } 613 614 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset) 615 { 616 u32 val; 617 618 regmap_read(regmap, offset, &val); 619 return val; 620 } 621 622 /* 623 * Structure used to store values of PHY registers for voltage-related 624 * coefficients, for particular voltage swing and pre-emphasis level. Values 625 * are shared across all physical lanes. 626 */ 627 struct coefficients { 628 /* Value of DRV_DIAG_TX_DRV register to use */ 629 u16 diag_tx_drv; 630 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */ 631 u16 mgnfs_mult; 632 /* Value of TX_TXCC_CPOST_MULT_00 register to use */ 633 u16 cpost_mult; 634 }; 635 636 /* 637 * Array consists of values of voltage-related registers for sd0801 PHY. A value 638 * of 0xFFFF is a placeholder for invalid combination, and will never be used. 639 */ 640 static const struct coefficients vltg_coeff[4][4] = { 641 /* voltage swing 0, pre-emphasis 0->3 */ 642 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A, 643 .cpost_mult = 0x0000}, 644 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 645 .cpost_mult = 0x0014}, 646 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012, 647 .cpost_mult = 0x0020}, 648 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 649 .cpost_mult = 0x002A} 650 }, 651 652 /* voltage swing 1, pre-emphasis 0->3 */ 653 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 654 .cpost_mult = 0x0000}, 655 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 656 .cpost_mult = 0x0012}, 657 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 658 .cpost_mult = 0x001F}, 659 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 660 .cpost_mult = 0xFFFF} 661 }, 662 663 /* voltage swing 2, pre-emphasis 0->3 */ 664 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 665 .cpost_mult = 0x0000}, 666 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 667 .cpost_mult = 0x0013}, 668 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 669 .cpost_mult = 0xFFFF}, 670 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 671 .cpost_mult = 0xFFFF} 672 }, 673 674 /* voltage swing 3, pre-emphasis 0->3 */ 675 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 676 .cpost_mult = 0x0000}, 677 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 678 .cpost_mult = 0xFFFF}, 679 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 680 .cpost_mult = 0xFFFF}, 681 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 682 .cpost_mult = 0xFFFF} 683 } 684 }; 685 686 static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type) 687 { 688 switch (phy_type) { 689 case TYPE_DP: 690 return "DisplayPort"; 691 case TYPE_PCIE: 692 return "PCIe"; 693 case TYPE_SGMII: 694 return "SGMII"; 695 case TYPE_QSGMII: 696 return "QSGMII"; 697 case TYPE_USB: 698 return "USB"; 699 case TYPE_USXGMII: 700 return "USXGMII"; 701 default: 702 return "None"; 703 } 704 } 705 706 /* 707 * Set registers responsible for enabling and configuring SSC, with second and 708 * third register values provided by parameters. 709 */ 710 static 711 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, 712 u32 ctrl2_val, u32 ctrl3_val) 713 { 714 struct regmap *regmap = cdns_phy->regmap_common_cdb; 715 716 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 717 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 718 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); 719 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 720 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 721 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 722 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); 723 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 724 } 725 726 static 727 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, 728 u32 rate, bool ssc) 729 { 730 struct regmap *regmap = cdns_phy->regmap_common_cdb; 731 732 /* Assumes 19.2 MHz refclock */ 733 switch (rate) { 734 /* Setting VCO for 10.8GHz */ 735 case 2700: 736 case 5400: 737 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119); 738 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 739 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 740 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC); 741 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012); 742 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119); 743 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 744 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 745 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC); 746 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012); 747 if (ssc) 748 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A); 749 break; 750 /* Setting VCO for 9.72GHz */ 751 case 1620: 752 case 2430: 753 case 3240: 754 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA); 755 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 756 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 757 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152); 758 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 759 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA); 760 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 761 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 762 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152); 763 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 764 if (ssc) 765 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069); 766 break; 767 /* Setting VCO for 8.64GHz */ 768 case 2160: 769 case 4320: 770 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2); 771 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 772 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 773 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C); 774 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 775 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2); 776 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 777 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 778 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C); 779 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 780 if (ssc) 781 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069); 782 break; 783 /* Setting VCO for 8.1GHz */ 784 case 8100: 785 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5); 786 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000); 787 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 788 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A); 789 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 790 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5); 791 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000); 792 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 793 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A); 794 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 795 if (ssc) 796 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A); 797 break; 798 } 799 800 if (ssc) { 801 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); 802 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 803 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); 804 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 805 } else { 806 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); 807 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); 808 /* Set reset register values to disable SSC */ 809 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 810 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 811 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 812 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 813 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 814 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 815 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 816 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 817 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 818 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 819 } 820 821 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099); 822 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); 823 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099); 824 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); 825 } 826 827 /* 828 * Set registers responsible for enabling and configuring SSC, with second 829 * register value provided by a parameter. 830 */ 831 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, 832 u32 ctrl2_val) 833 { 834 struct regmap *regmap = cdns_phy->regmap_common_cdb; 835 836 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 837 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 838 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F); 839 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 840 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 841 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 842 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F); 843 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 844 } 845 846 static 847 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, 848 u32 rate, bool ssc) 849 { 850 struct regmap *regmap = cdns_phy->regmap_common_cdb; 851 852 /* Assumes 25 MHz refclock */ 853 switch (rate) { 854 /* Setting VCO for 10.8GHz */ 855 case 2700: 856 case 5400: 857 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0); 858 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 859 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 860 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120); 861 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0); 862 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 863 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 864 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120); 865 if (ssc) 866 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); 867 break; 868 /* Setting VCO for 9.72GHz */ 869 case 1620: 870 case 2430: 871 case 3240: 872 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184); 873 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD); 874 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 875 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104); 876 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184); 877 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD); 878 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 879 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104); 880 if (ssc) 881 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); 882 break; 883 /* Setting VCO for 8.64GHz */ 884 case 2160: 885 case 4320: 886 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159); 887 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A); 888 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 889 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7); 890 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159); 891 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A); 892 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 893 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7); 894 if (ssc) 895 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); 896 break; 897 /* Setting VCO for 8.1GHz */ 898 case 8100: 899 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144); 900 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 901 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 902 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8); 903 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144); 904 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 905 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 906 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8); 907 if (ssc) 908 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); 909 break; 910 } 911 912 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 913 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 914 915 if (ssc) { 916 cdns_torrent_phy_write(regmap, 917 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); 918 cdns_torrent_phy_write(regmap, 919 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 920 cdns_torrent_phy_write(regmap, 921 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); 922 cdns_torrent_phy_write(regmap, 923 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 924 } else { 925 cdns_torrent_phy_write(regmap, 926 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); 927 cdns_torrent_phy_write(regmap, 928 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); 929 /* Set reset register values to disable SSC */ 930 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 931 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 932 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 933 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 934 cdns_torrent_phy_write(regmap, 935 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 936 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 937 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 938 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 939 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 940 cdns_torrent_phy_write(regmap, 941 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 942 } 943 944 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); 945 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); 946 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); 947 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); 948 } 949 950 static 951 void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy, 952 u32 rate, bool ssc) 953 { 954 struct regmap *regmap = cdns_phy->regmap_common_cdb; 955 956 /* Assumes 100 MHz refclock */ 957 switch (rate) { 958 /* Setting VCO for 10.8GHz */ 959 case 2700: 960 case 5400: 961 if (cdns_phy->dp_pll & DP_PLL0) 962 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022); 963 964 if (cdns_phy->dp_pll & DP_PLL1) { 965 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028); 966 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022); 967 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C); 968 } 969 break; 970 /* Setting VCO for 9.72GHz */ 971 case 1620: 972 case 2430: 973 case 3240: 974 if (cdns_phy->dp_pll & DP_PLL0) { 975 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 976 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 977 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 978 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 979 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061); 980 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333); 981 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 982 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042); 983 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 984 } 985 if (cdns_phy->dp_pll & DP_PLL1) { 986 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 987 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 988 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 989 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 990 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061); 991 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333); 992 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 993 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042); 994 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 995 } 996 break; 997 /* Setting VCO for 8.64GHz */ 998 case 2160: 999 case 4320: 1000 if (cdns_phy->dp_pll & DP_PLL0) { 1001 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 1002 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 1003 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 1004 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 1005 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056); 1006 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666); 1007 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1008 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A); 1009 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1010 } 1011 if (cdns_phy->dp_pll & DP_PLL1) { 1012 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 1013 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 1014 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 1015 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 1016 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056); 1017 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666); 1018 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1019 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A); 1020 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1021 } 1022 break; 1023 /* Setting VCO for 8.1GHz */ 1024 case 8100: 1025 if (cdns_phy->dp_pll & DP_PLL0) { 1026 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 1027 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 1028 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 1029 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 1030 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051); 1031 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1032 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036); 1033 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1034 } 1035 if (cdns_phy->dp_pll & DP_PLL1) { 1036 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 1037 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 1038 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 1039 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 1040 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051); 1041 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1042 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036); 1043 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1044 } 1045 break; 1046 } 1047 } 1048 1049 /* Set PLL used for DP configuration */ 1050 static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy, 1051 enum cdns_torrent_phy_type phy_t2) 1052 { 1053 switch (phy_t2) { 1054 case TYPE_PCIE: 1055 case TYPE_USB: 1056 cdns_phy->dp_pll = DP_PLL1; 1057 break; 1058 case TYPE_SGMII: 1059 case TYPE_QSGMII: 1060 cdns_phy->dp_pll = DP_PLL0; 1061 break; 1062 case TYPE_NONE: 1063 cdns_phy->dp_pll = DP_PLL0 | DP_PLL1; 1064 break; 1065 default: 1066 dev_err(cdns_phy->dev, "Unsupported PHY configuration\n"); 1067 return -EINVAL; 1068 } 1069 1070 return 0; 1071 } 1072 1073 /* 1074 * Enable or disable PLL for selected lanes. 1075 */ 1076 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, 1077 struct cdns_torrent_inst *inst, 1078 struct phy_configure_opts_dp *dp, 1079 bool enable) 1080 { 1081 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1082 u32 rd_val, pll_ack_val; 1083 int ret; 1084 1085 /* 1086 * Used to determine, which bits to check for or enable in 1087 * PHY_PMA_XCVR_PLLCLK_EN register. 1088 */ 1089 u32 pll_bits; 1090 /* Used to enable or disable lanes. */ 1091 u32 pll_val; 1092 1093 /* Select values of registers and mask, depending on enabled lane count. */ 1094 pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN); 1095 1096 if (enable) { 1097 pll_bits = ((1 << dp->lanes) - 1); 1098 pll_val |= pll_bits; 1099 pll_ack_val = pll_bits; 1100 } else { 1101 pll_bits = ((1 << inst->num_lanes) - 1); 1102 pll_val &= (~pll_bits); 1103 pll_ack_val = 0; 1104 } 1105 1106 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val); 1107 1108 /* Wait for acknowledgment from PHY. */ 1109 ret = regmap_read_poll_timeout(regmap, 1110 PHY_PMA_XCVR_PLLCLK_EN_ACK, 1111 rd_val, 1112 (rd_val & pll_bits) == pll_ack_val, 1113 0, POLL_TIMEOUT_US); 1114 ndelay(100); 1115 return ret; 1116 } 1117 1118 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, 1119 struct cdns_torrent_inst *inst, 1120 u32 num_lanes, 1121 enum phy_powerstate powerstate) 1122 { 1123 /* Register value for power state for a single byte. */ 1124 u32 value_part, i; 1125 u32 value = 0; 1126 u32 mask = 0; 1127 u32 read_val; 1128 int ret; 1129 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1130 1131 switch (powerstate) { 1132 case (POWERSTATE_A0): 1133 value_part = 0x01U; 1134 break; 1135 case (POWERSTATE_A2): 1136 value_part = 0x04U; 1137 break; 1138 default: 1139 /* Powerstate A3 */ 1140 value_part = 0x08U; 1141 break; 1142 } 1143 1144 /* Select values of registers and mask, depending on enabled lane count. */ 1145 1146 for (i = 0; i < num_lanes; i++) { 1147 value |= (value_part << PHY_POWER_STATE_LN(i)); 1148 mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(i)); 1149 } 1150 1151 /* Set power state A<n>. */ 1152 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value); 1153 /* Wait, until PHY acknowledges power state completion. */ 1154 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK, 1155 read_val, (read_val & mask) == value, 0, 1156 POLL_TIMEOUT_US); 1157 if (ret) 1158 return ret; 1159 1160 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000); 1161 ndelay(100); 1162 1163 return ret; 1164 } 1165 1166 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, 1167 struct cdns_torrent_inst *inst, u32 num_lanes) 1168 { 1169 unsigned int read_val; 1170 int ret; 1171 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1172 1173 /* 1174 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the 1175 * master lane 1176 */ 1177 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK, 1178 read_val, read_val & 1, 1179 0, POLL_TIMEOUT_US); 1180 if (ret == -ETIMEDOUT) { 1181 dev_err(cdns_phy->dev, 1182 "timeout waiting for link PLL clock enable ack\n"); 1183 return ret; 1184 } 1185 1186 ndelay(100); 1187 1188 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, 1189 POWERSTATE_A2); 1190 if (ret) 1191 return ret; 1192 1193 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, 1194 POWERSTATE_A0); 1195 1196 return ret; 1197 } 1198 1199 static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) 1200 { 1201 unsigned int reg; 1202 int ret; 1203 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1204 1205 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg, 1206 reg & 1, 0, POLL_TIMEOUT_US); 1207 if (ret == -ETIMEDOUT) { 1208 dev_err(cdns_phy->dev, 1209 "timeout waiting for PMA common ready\n"); 1210 return -ETIMEDOUT; 1211 } 1212 1213 return 0; 1214 } 1215 1216 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, 1217 struct cdns_torrent_inst *inst, 1218 u32 rate, u32 num_lanes) 1219 { 1220 unsigned int clk_sel_val = 0; 1221 unsigned int hsclk_div_val = 0; 1222 unsigned int i; 1223 1224 switch (rate) { 1225 case 1620: 1226 clk_sel_val = 0x0f01; 1227 hsclk_div_val = 2; 1228 break; 1229 case 2160: 1230 case 2430: 1231 case 2700: 1232 clk_sel_val = 0x0701; 1233 hsclk_div_val = 1; 1234 break; 1235 case 3240: 1236 clk_sel_val = 0x0b00; 1237 hsclk_div_val = 2; 1238 break; 1239 case 4320: 1240 case 5400: 1241 clk_sel_val = 0x0301; 1242 hsclk_div_val = 0; 1243 break; 1244 case 8100: 1245 clk_sel_val = 0x0200; 1246 hsclk_div_val = 0; 1247 break; 1248 } 1249 1250 if (cdns_phy->dp_pll & DP_PLL0) 1251 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1252 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); 1253 1254 if (cdns_phy->dp_pll & DP_PLL1) 1255 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1256 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); 1257 1258 /* PMA lane configuration to deal with multi-link operation */ 1259 for (i = 0; i < num_lanes; i++) 1260 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i], 1261 XCVR_DIAG_HSCLK_DIV, hsclk_div_val); 1262 } 1263 1264 /* 1265 * Perform register operations related to setting link rate, once powerstate is 1266 * set and PLL disable request was processed. 1267 */ 1268 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, 1269 struct cdns_torrent_inst *inst, 1270 struct phy_configure_opts_dp *dp) 1271 { 1272 u32 read_val, field_val; 1273 int ret; 1274 1275 /* 1276 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before 1277 * re-programming the new data rate. 1278 */ 1279 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); 1280 if (ret) 1281 return ret; 1282 field_val &= ~(cdns_phy->dp_pll); 1283 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); 1284 1285 /* 1286 * Wait for PLL ready de-assertion. 1287 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 1288 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1 1289 */ 1290 if (cdns_phy->dp_pll & DP_PLL0) { 1291 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1292 read_val, 1293 ((read_val >> 2) & 0x01) != 0, 1294 0, POLL_TIMEOUT_US); 1295 if (ret) 1296 return ret; 1297 } 1298 1299 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) { 1300 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1301 read_val, 1302 ((read_val >> 3) & 0x01) != 0, 1303 0, POLL_TIMEOUT_US); 1304 if (ret) 1305 return ret; 1306 } 1307 ndelay(200); 1308 1309 /* DP Rate Change - VCO Output settings. */ 1310 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1311 /* PMA common configuration 19.2MHz */ 1312 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc); 1313 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1314 /* PMA common configuration 25MHz */ 1315 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc); 1316 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1317 /* PMA common configuration 100MHz */ 1318 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc); 1319 1320 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes); 1321 1322 /* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */ 1323 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); 1324 if (ret) 1325 return ret; 1326 field_val |= cdns_phy->dp_pll; 1327 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); 1328 1329 /* 1330 * Wait for PLL ready assertion. 1331 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 1332 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1 1333 */ 1334 if (cdns_phy->dp_pll & DP_PLL0) { 1335 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1336 read_val, 1337 (read_val & 0x01) != 0, 1338 0, POLL_TIMEOUT_US); 1339 if (ret) 1340 return ret; 1341 } 1342 1343 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) 1344 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1345 read_val, 1346 ((read_val >> 1) & 0x01) != 0, 1347 0, POLL_TIMEOUT_US); 1348 1349 return ret; 1350 } 1351 1352 /* 1353 * Verify, that parameters to configure PHY with are correct. 1354 */ 1355 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst, 1356 struct phy_configure_opts_dp *dp) 1357 { 1358 u8 i; 1359 1360 /* If changing link rate was required, verify it's supported. */ 1361 if (dp->set_rate) { 1362 switch (dp->link_rate) { 1363 case 1620: 1364 case 2160: 1365 case 2430: 1366 case 2700: 1367 case 3240: 1368 case 4320: 1369 case 5400: 1370 case 8100: 1371 /* valid bit rate */ 1372 break; 1373 default: 1374 return -EINVAL; 1375 } 1376 } 1377 1378 /* Verify lane count. */ 1379 switch (dp->lanes) { 1380 case 1: 1381 case 2: 1382 case 4: 1383 /* valid lane count. */ 1384 break; 1385 default: 1386 return -EINVAL; 1387 } 1388 1389 /* Check against actual number of PHY's lanes. */ 1390 if (dp->lanes > inst->num_lanes) 1391 return -EINVAL; 1392 1393 /* 1394 * If changing voltages is required, check swing and pre-emphasis 1395 * levels, per-lane. 1396 */ 1397 if (dp->set_voltages) { 1398 /* Lane count verified previously. */ 1399 for (i = 0; i < dp->lanes; i++) { 1400 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1401 return -EINVAL; 1402 1403 /* Sum of voltage swing and pre-emphasis levels cannot 1404 * exceed 3. 1405 */ 1406 if (dp->voltage[i] + dp->pre[i] > 3) 1407 return -EINVAL; 1408 } 1409 } 1410 1411 return 0; 1412 } 1413 1414 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ 1415 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, 1416 struct cdns_torrent_inst *inst, 1417 u32 num_lanes) 1418 { 1419 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1420 u32 pwr_state = cdns_torrent_dp_read(regmap, 1421 PHY_PMA_XCVR_POWER_STATE_REQ); 1422 u32 pll_clk_en = cdns_torrent_dp_read(regmap, 1423 PHY_PMA_XCVR_PLLCLK_EN); 1424 u32 i; 1425 1426 for (i = 0; i < num_lanes; i++) { 1427 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK 1428 << PHY_POWER_STATE_LN(inst->mlane + i)); 1429 1430 pll_clk_en &= ~(0x01U << (inst->mlane + i)); 1431 } 1432 1433 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state); 1434 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en); 1435 } 1436 1437 /* Configure lane count as required. */ 1438 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, 1439 struct cdns_torrent_inst *inst, 1440 struct phy_configure_opts_dp *dp) 1441 { 1442 u32 value, i; 1443 int ret; 1444 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1445 u8 lane_mask = (1 << dp->lanes) - 1; 1446 u8 pma_tx_elec_idle_mask = 0; 1447 u32 clane = inst->mlane; 1448 1449 lane_mask <<= clane; 1450 1451 value = cdns_torrent_dp_read(regmap, PHY_RESET); 1452 /* clear pma_tx_elec_idle_ln_* bits. */ 1453 pma_tx_elec_idle_mask = ((1 << inst->num_lanes) - 1) << clane; 1454 1455 pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT; 1456 1457 value &= ~pma_tx_elec_idle_mask; 1458 1459 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */ 1460 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & 1461 pma_tx_elec_idle_mask; 1462 1463 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1464 1465 /* reset the link by asserting master lane phy_l0*_reset_n low */ 1466 cdns_torrent_dp_write(regmap, PHY_RESET, 1467 value & (~(1 << clane))); 1468 1469 /* 1470 * Assert lane reset on unused lanes and master lane so they remain in reset 1471 * and powered down when re-enabling the link 1472 */ 1473 for (i = 0; i < inst->num_lanes; i++) 1474 value &= (~(1 << (clane + i))); 1475 1476 for (i = 1; i < inst->num_lanes; i++) 1477 value |= ((1 << (clane + i)) & lane_mask); 1478 1479 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1480 1481 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, dp->lanes); 1482 1483 /* release phy_l0*_reset_n based on used laneCount */ 1484 for (i = 0; i < inst->num_lanes; i++) 1485 value &= (~(1 << (clane + i))); 1486 1487 for (i = 0; i < inst->num_lanes; i++) 1488 value |= ((1 << (clane + i)) & lane_mask); 1489 1490 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1491 1492 /* Wait, until PHY gets ready after releasing PHY reset signal. */ 1493 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1494 if (ret) 1495 return ret; 1496 1497 ndelay(100); 1498 1499 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1500 value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN); 1501 value |= (1 << clane); 1502 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value); 1503 1504 ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes); 1505 1506 return ret; 1507 } 1508 1509 /* Configure link rate as required. */ 1510 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, 1511 struct cdns_torrent_inst *inst, 1512 struct phy_configure_opts_dp *dp) 1513 { 1514 int ret; 1515 1516 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes, 1517 POWERSTATE_A3); 1518 if (ret) 1519 return ret; 1520 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false); 1521 if (ret) 1522 return ret; 1523 ndelay(200); 1524 1525 ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp); 1526 if (ret) 1527 return ret; 1528 ndelay(200); 1529 1530 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true); 1531 if (ret) 1532 return ret; 1533 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes, 1534 POWERSTATE_A2); 1535 if (ret) 1536 return ret; 1537 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes, 1538 POWERSTATE_A0); 1539 if (ret) 1540 return ret; 1541 ndelay(900); 1542 1543 return ret; 1544 } 1545 1546 /* Configure voltage swing and pre-emphasis for all enabled lanes. */ 1547 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, 1548 struct cdns_torrent_inst *inst, 1549 struct phy_configure_opts_dp *dp) 1550 { 1551 u8 lane; 1552 u16 val; 1553 1554 for (lane = 0; lane < dp->lanes; lane++) { 1555 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1556 TX_DIAG_ACYA); 1557 /* 1558 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the 1559 * current state of the analog TX driver. 1560 */ 1561 val |= TX_DIAG_ACYA_HBDC_MASK; 1562 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1563 TX_DIAG_ACYA, val); 1564 1565 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1566 TX_TXCC_CTRL, 0x08A4); 1567 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; 1568 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1569 DRV_DIAG_TX_DRV, val); 1570 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; 1571 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1572 TX_TXCC_MGNFS_MULT_000, 1573 val); 1574 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; 1575 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1576 TX_TXCC_CPOST_MULT_00, 1577 val); 1578 1579 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1580 TX_DIAG_ACYA); 1581 /* 1582 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of 1583 * analog TX driver to reflect the new programmed one. 1584 */ 1585 val &= ~TX_DIAG_ACYA_HBDC_MASK; 1586 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1587 TX_DIAG_ACYA, val); 1588 } 1589 }; 1590 1591 static int cdns_torrent_dp_configure(struct phy *phy, 1592 union phy_configure_opts *opts) 1593 { 1594 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1595 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1596 int ret; 1597 1598 ret = cdns_torrent_dp_verify_config(inst, &opts->dp); 1599 if (ret) { 1600 dev_err(&phy->dev, "invalid params for phy configure\n"); 1601 return ret; 1602 } 1603 1604 if (opts->dp.set_lanes) { 1605 ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp); 1606 if (ret) { 1607 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n"); 1608 return ret; 1609 } 1610 } 1611 1612 if (opts->dp.set_rate) { 1613 ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp); 1614 if (ret) { 1615 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n"); 1616 return ret; 1617 } 1618 } 1619 1620 if (opts->dp.set_voltages) 1621 cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp); 1622 1623 return ret; 1624 } 1625 1626 static int cdns_torrent_phy_on(struct phy *phy) 1627 { 1628 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1629 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1630 u32 read_val; 1631 int ret; 1632 1633 if (cdns_phy->nsubnodes == 1) { 1634 /* Take the PHY lane group out of reset */ 1635 reset_control_deassert(inst->lnk_rst); 1636 1637 /* Take the PHY out of reset */ 1638 ret = reset_control_deassert(cdns_phy->phy_rst); 1639 if (ret) 1640 return ret; 1641 } 1642 1643 /* 1644 * Wait for cmn_ready assertion 1645 * PHY_PMA_CMN_CTRL1[0] == 1 1646 */ 1647 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1, 1648 read_val, read_val, 1000, 1649 PLL_LOCK_TIMEOUT); 1650 if (ret) { 1651 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n"); 1652 return ret; 1653 } 1654 1655 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) { 1656 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane], 1657 read_val, !read_val, 1000, 1658 PLL_LOCK_TIMEOUT); 1659 if (ret == -ETIMEDOUT) { 1660 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n"); 1661 return ret; 1662 } 1663 } 1664 1665 return 0; 1666 } 1667 1668 static int cdns_torrent_phy_off(struct phy *phy) 1669 { 1670 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1671 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1672 int ret; 1673 1674 if (cdns_phy->nsubnodes != 1) 1675 return 0; 1676 1677 ret = reset_control_assert(cdns_phy->phy_rst); 1678 if (ret) 1679 return ret; 1680 1681 return reset_control_assert(inst->lnk_rst); 1682 } 1683 1684 static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy, 1685 struct cdns_torrent_inst *inst) 1686 { 1687 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1688 unsigned char lane_bits; 1689 u32 val; 1690 1691 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */ 1692 1693 /* 1694 * Set lines power state to A0 1695 * Set lines pll clk enable to 0 1696 */ 1697 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes); 1698 1699 /* 1700 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on 1701 * used lanes 1702 */ 1703 lane_bits = (1 << inst->num_lanes) - 1; 1704 1705 val = cdns_torrent_dp_read(regmap, PHY_RESET); 1706 val |= (0xF & lane_bits); 1707 val &= ~(lane_bits << 4); 1708 cdns_torrent_dp_write(regmap, PHY_RESET, val); 1709 1710 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1711 val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN); 1712 val |= 1; 1713 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val); 1714 1715 /* 1716 * PHY PMA registers configuration functions 1717 * Initialize PHY with max supported link rate, without SSC. 1718 */ 1719 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1720 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, 1721 cdns_phy->max_bit_rate, 1722 false); 1723 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1724 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, 1725 cdns_phy->max_bit_rate, 1726 false); 1727 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1728 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, 1729 cdns_phy->max_bit_rate, 1730 false); 1731 1732 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate, 1733 inst->num_lanes); 1734 1735 /* take out of reset */ 1736 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1); 1737 } 1738 1739 static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy, 1740 struct cdns_torrent_inst *inst, 1741 struct phy *phy) 1742 { 1743 int ret; 1744 1745 ret = cdns_torrent_phy_on(phy); 1746 if (ret) 1747 return ret; 1748 1749 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1750 if (ret) 1751 return ret; 1752 1753 ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes); 1754 1755 return ret; 1756 } 1757 1758 static int cdns_torrent_dp_init(struct phy *phy) 1759 { 1760 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1761 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1762 int ret; 1763 1764 switch (cdns_phy->ref_clk_rate) { 1765 case CLK_19_2_MHZ: 1766 case CLK_25_MHZ: 1767 case CLK_100_MHZ: 1768 /* Valid Ref Clock Rate */ 1769 break; 1770 default: 1771 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); 1772 return -EINVAL; 1773 } 1774 1775 ret = cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE); 1776 if (ret) 1777 return ret; 1778 1779 cdns_torrent_dp_common_init(cdns_phy, inst); 1780 1781 return cdns_torrent_dp_start(cdns_phy, inst, phy); 1782 } 1783 1784 static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy, 1785 struct cdns_torrent_inst *inst, 1786 struct phy *phy) 1787 { 1788 if (cdns_phy->ref_clk_rate != CLK_100_MHZ) { 1789 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); 1790 return -EINVAL; 1791 } 1792 1793 cdns_torrent_dp_common_init(cdns_phy, inst); 1794 1795 return cdns_torrent_dp_start(cdns_phy, inst, phy); 1796 } 1797 1798 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) 1799 { 1800 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1801 1802 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1); 1803 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1); 1804 1805 return 0; 1806 } 1807 1808 static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) 1809 { 1810 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1811 1812 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0); 1813 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0); 1814 } 1815 1816 static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) 1817 { 1818 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1819 int val; 1820 1821 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val); 1822 1823 return !!val; 1824 } 1825 1826 static const struct clk_ops cdns_torrent_derived_refclk_ops = { 1827 .enable = cdns_torrent_derived_refclk_enable, 1828 .disable = cdns_torrent_derived_refclk_disable, 1829 .is_enabled = cdns_torrent_derived_refclk_is_enabled, 1830 }; 1831 1832 static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy) 1833 { 1834 struct cdns_torrent_derived_refclk *derived_refclk; 1835 struct device *dev = cdns_phy->dev; 1836 struct clk_init_data *init; 1837 const char *parent_name; 1838 char clk_name[100]; 1839 struct clk_hw *hw; 1840 struct clk *clk; 1841 int ret; 1842 1843 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); 1844 if (!derived_refclk) 1845 return -ENOMEM; 1846 1847 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1848 clk_names[CDNS_TORRENT_DERIVED_REFCLK]); 1849 1850 clk = devm_clk_get_optional(dev, "phy_en_refclk"); 1851 if (IS_ERR(clk)) { 1852 dev_err(dev, "No parent clock for derived_refclk\n"); 1853 return PTR_ERR(clk); 1854 } 1855 1856 init = &derived_refclk->clk_data; 1857 1858 if (clk) { 1859 parent_name = __clk_get_name(clk); 1860 init->parent_names = &parent_name; 1861 init->num_parents = 1; 1862 } 1863 init->ops = &cdns_torrent_derived_refclk_ops; 1864 init->flags = 0; 1865 init->name = clk_name; 1866 1867 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; 1868 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; 1869 1870 derived_refclk->hw.init = init; 1871 1872 hw = &derived_refclk->hw; 1873 ret = devm_clk_hw_register(dev, hw); 1874 if (ret) 1875 return ret; 1876 1877 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw; 1878 1879 return 0; 1880 } 1881 1882 static int cdns_torrent_received_refclk_enable(struct clk_hw *hw) 1883 { 1884 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1885 1886 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1); 1887 1888 return 0; 1889 } 1890 1891 static void cdns_torrent_received_refclk_disable(struct clk_hw *hw) 1892 { 1893 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1894 1895 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0); 1896 } 1897 1898 static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw) 1899 { 1900 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1901 int val, cmn_val; 1902 1903 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val); 1904 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val); 1905 1906 return val && !cmn_val; 1907 } 1908 1909 static const struct clk_ops cdns_torrent_received_refclk_ops = { 1910 .enable = cdns_torrent_received_refclk_enable, 1911 .disable = cdns_torrent_received_refclk_disable, 1912 .is_enabled = cdns_torrent_received_refclk_is_enabled, 1913 }; 1914 1915 static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy) 1916 { 1917 struct cdns_torrent_received_refclk *received_refclk; 1918 struct device *dev = cdns_phy->dev; 1919 struct clk_init_data *init; 1920 const char *parent_name; 1921 char clk_name[100]; 1922 struct clk_hw *hw; 1923 struct clk *clk; 1924 int ret; 1925 1926 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL); 1927 if (!received_refclk) 1928 return -ENOMEM; 1929 1930 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1931 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]); 1932 1933 clk = devm_clk_get_optional(dev, "phy_en_refclk"); 1934 if (IS_ERR(clk)) { 1935 dev_err(dev, "No parent clock for received_refclk\n"); 1936 return PTR_ERR(clk); 1937 } 1938 1939 init = &received_refclk->clk_data; 1940 1941 if (clk) { 1942 parent_name = __clk_get_name(clk); 1943 init->parent_names = &parent_name; 1944 init->num_parents = 1; 1945 } 1946 init->ops = &cdns_torrent_received_refclk_ops; 1947 init->flags = 0; 1948 init->name = clk_name; 1949 1950 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; 1951 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; 1952 1953 received_refclk->hw.init = init; 1954 1955 hw = &received_refclk->hw; 1956 ret = devm_clk_hw_register(dev, hw); 1957 if (ret) 1958 return ret; 1959 1960 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw; 1961 1962 return 0; 1963 } 1964 1965 static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw) 1966 { 1967 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1968 1969 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0); 1970 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1); 1971 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0); 1972 1973 return 0; 1974 } 1975 1976 static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw) 1977 { 1978 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1979 1980 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1); 1981 } 1982 1983 static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw) 1984 { 1985 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1986 int val; 1987 1988 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val); 1989 1990 return !val; 1991 } 1992 1993 static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw) 1994 { 1995 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1996 unsigned int val; 1997 1998 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val); 1999 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val); 2000 } 2001 2002 static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index) 2003 { 2004 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 2005 unsigned int val; 2006 2007 val = cdns_torrent_refclk_driver_mux_table[index]; 2008 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val); 2009 } 2010 2011 static const struct clk_ops cdns_torrent_refclk_driver_ops = { 2012 .enable = cdns_torrent_refclk_driver_enable, 2013 .disable = cdns_torrent_refclk_driver_disable, 2014 .is_enabled = cdns_torrent_refclk_driver_is_enabled, 2015 .determine_rate = __clk_mux_determine_rate, 2016 .set_parent = cdns_torrent_refclk_driver_set_parent, 2017 .get_parent = cdns_torrent_refclk_driver_get_parent, 2018 }; 2019 2020 static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy) 2021 { 2022 struct cdns_torrent_refclk_driver *refclk_driver; 2023 struct device *dev = cdns_phy->dev; 2024 struct regmap_field *field; 2025 struct clk_init_data *init; 2026 const char **parent_names; 2027 unsigned int num_parents; 2028 struct regmap *regmap; 2029 char clk_name[100]; 2030 struct clk_hw *hw; 2031 int i, ret; 2032 2033 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL); 2034 if (!refclk_driver) 2035 return -ENOMEM; 2036 2037 num_parents = ARRAY_SIZE(refclk_driver_parent_index); 2038 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL); 2039 if (!parent_names) 2040 return -ENOMEM; 2041 2042 for (i = 0; i < num_parents; i++) { 2043 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]]; 2044 if (IS_ERR_OR_NULL(hw)) { 2045 dev_err(dev, "No parent clock for refclk driver clock\n"); 2046 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT; 2047 } 2048 parent_names[i] = clk_hw_get_name(hw); 2049 } 2050 2051 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 2052 clk_names[CDNS_TORRENT_REFCLK_DRIVER]); 2053 2054 init = &refclk_driver->clk_data; 2055 2056 init->ops = &cdns_torrent_refclk_driver_ops; 2057 init->flags = CLK_SET_RATE_NO_REPARENT; 2058 init->parent_names = parent_names; 2059 init->num_parents = num_parents; 2060 init->name = clk_name; 2061 2062 regmap = cdns_phy->regmap_common_cdb; 2063 2064 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) { 2065 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]); 2066 if (IS_ERR(field)) { 2067 dev_err(dev, "Refclk driver CMN reg field init failed\n"); 2068 return PTR_ERR(field); 2069 } 2070 refclk_driver->cmn_fields[i] = field; 2071 } 2072 2073 /* Enable Derived reference clock as default */ 2074 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1); 2075 2076 refclk_driver->hw.init = init; 2077 2078 hw = &refclk_driver->hw; 2079 ret = devm_clk_hw_register(dev, hw); 2080 if (ret) 2081 return ret; 2082 2083 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw; 2084 2085 return 0; 2086 } 2087 2088 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 2089 u32 block_offset, 2090 u8 reg_offset_shift, 2091 const struct regmap_config *config) 2092 { 2093 struct cdns_regmap_cdb_context *ctx; 2094 2095 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2096 if (!ctx) 2097 return ERR_PTR(-ENOMEM); 2098 2099 ctx->dev = dev; 2100 ctx->base = base + block_offset; 2101 ctx->reg_offset_shift = reg_offset_shift; 2102 2103 return devm_regmap_init(dev, NULL, ctx, config); 2104 } 2105 2106 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy) 2107 { 2108 struct device *dev = cdns_phy->dev; 2109 struct regmap_field *field; 2110 struct regmap *regmap; 2111 2112 regmap = cdns_phy->regmap_dptx_phy_reg; 2113 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); 2114 if (IS_ERR(field)) { 2115 dev_err(dev, "PHY_RESET reg field init failed\n"); 2116 return PTR_ERR(field); 2117 } 2118 cdns_phy->phy_reset_ctrl = field; 2119 2120 return 0; 2121 } 2122 2123 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy) 2124 { 2125 struct device *dev = cdns_phy->dev; 2126 struct regmap_field *field; 2127 struct regmap *regmap; 2128 int i; 2129 2130 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2131 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg); 2132 if (IS_ERR(field)) { 2133 dev_err(dev, "PHY_PLL_CFG reg field init failed\n"); 2134 return PTR_ERR(field); 2135 } 2136 cdns_phy->phy_pll_cfg = field; 2137 2138 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2139 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0); 2140 if (IS_ERR(field)) { 2141 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n"); 2142 return PTR_ERR(field); 2143 } 2144 cdns_phy->phy_pipe_cmn_ctrl1_0 = field; 2145 2146 regmap = cdns_phy->regmap_common_cdb; 2147 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4); 2148 if (IS_ERR(field)) { 2149 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n"); 2150 return PTR_ERR(field); 2151 } 2152 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field; 2153 2154 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2155 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1); 2156 if (IS_ERR(field)) { 2157 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n"); 2158 return PTR_ERR(field); 2159 } 2160 cdns_phy->phy_pma_cmn_ctrl_1 = field; 2161 2162 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2163 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); 2164 if (IS_ERR(field)) { 2165 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); 2166 return PTR_ERR(field); 2167 } 2168 cdns_phy->phy_pma_cmn_ctrl_2 = field; 2169 2170 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2171 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl); 2172 if (IS_ERR(field)) { 2173 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n"); 2174 return PTR_ERR(field); 2175 } 2176 cdns_phy->phy_pma_pll_raw_ctrl = field; 2177 2178 for (i = 0; i < MAX_NUM_LANES; i++) { 2179 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i]; 2180 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1); 2181 if (IS_ERR(field)) { 2182 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i); 2183 return PTR_ERR(field); 2184 } 2185 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field; 2186 } 2187 2188 return 0; 2189 } 2190 2191 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy) 2192 { 2193 void __iomem *base = cdns_phy->base; 2194 struct device *dev = cdns_phy->dev; 2195 struct regmap *regmap; 2196 u8 reg_offset_shift; 2197 u32 block_offset; 2198 2199 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 2200 2201 block_offset = TORRENT_DPTX_PHY_OFFSET; 2202 regmap = cdns_regmap_init(dev, base, block_offset, 2203 reg_offset_shift, 2204 &cdns_torrent_dptx_phy_config); 2205 if (IS_ERR(regmap)) { 2206 dev_err(dev, "Failed to init DPTX PHY regmap\n"); 2207 return PTR_ERR(regmap); 2208 } 2209 cdns_phy->regmap_dptx_phy_reg = regmap; 2210 2211 return 0; 2212 } 2213 2214 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) 2215 { 2216 void __iomem *sd_base = cdns_phy->sd_base; 2217 u8 block_offset_shift, reg_offset_shift; 2218 struct device *dev = cdns_phy->dev; 2219 struct regmap *regmap; 2220 u32 block_offset; 2221 int i; 2222 2223 block_offset_shift = cdns_phy->init_data->block_offset_shift; 2224 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 2225 2226 for (i = 0; i < MAX_NUM_LANES; i++) { 2227 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift, 2228 reg_offset_shift); 2229 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2230 reg_offset_shift, 2231 &cdns_torrent_tx_lane_cdb_config[i]); 2232 if (IS_ERR(regmap)) { 2233 dev_err(dev, "Failed to init tx lane CDB regmap\n"); 2234 return PTR_ERR(regmap); 2235 } 2236 cdns_phy->regmap_tx_lane_cdb[i] = regmap; 2237 2238 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift, 2239 reg_offset_shift); 2240 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2241 reg_offset_shift, 2242 &cdns_torrent_rx_lane_cdb_config[i]); 2243 if (IS_ERR(regmap)) { 2244 dev_err(dev, "Failed to init rx lane CDB regmap\n"); 2245 return PTR_ERR(regmap); 2246 } 2247 cdns_phy->regmap_rx_lane_cdb[i] = regmap; 2248 2249 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, 2250 reg_offset_shift); 2251 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2252 reg_offset_shift, 2253 &cdns_torrent_phy_pcs_lane_cdb_config[i]); 2254 if (IS_ERR(regmap)) { 2255 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 2256 return PTR_ERR(regmap); 2257 } 2258 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap; 2259 } 2260 2261 block_offset = TORRENT_COMMON_CDB_OFFSET; 2262 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2263 reg_offset_shift, 2264 &cdns_torrent_common_cdb_config); 2265 if (IS_ERR(regmap)) { 2266 dev_err(dev, "Failed to init common CDB regmap\n"); 2267 return PTR_ERR(regmap); 2268 } 2269 cdns_phy->regmap_common_cdb = regmap; 2270 2271 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift); 2272 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2273 reg_offset_shift, 2274 &cdns_torrent_phy_pcs_cmn_cdb_config); 2275 if (IS_ERR(regmap)) { 2276 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 2277 return PTR_ERR(regmap); 2278 } 2279 cdns_phy->regmap_phy_pcs_common_cdb = regmap; 2280 2281 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift); 2282 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2283 reg_offset_shift, 2284 &cdns_torrent_phy_pma_cmn_cdb_config); 2285 if (IS_ERR(regmap)) { 2286 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 2287 return PTR_ERR(regmap); 2288 } 2289 cdns_phy->regmap_phy_pma_common_cdb = regmap; 2290 2291 return 0; 2292 } 2293 2294 static int cdns_torrent_phy_init(struct phy *phy) 2295 { 2296 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 2297 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 2298 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 2299 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 2300 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 2301 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 2302 enum cdns_torrent_phy_type phy_type = inst->phy_type; 2303 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; 2304 struct cdns_torrent_vals *phy_pma_cmn_vals; 2305 struct cdns_torrent_vals *pcs_cmn_vals; 2306 struct cdns_reg_pairs *reg_pairs; 2307 struct regmap *regmap; 2308 u32 num_regs; 2309 int i, j; 2310 2311 if (cdns_phy->nsubnodes > 1) { 2312 if (phy_type == TYPE_DP) 2313 return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy); 2314 return 0; 2315 } 2316 2317 /** 2318 * Spread spectrum generation is not required or supported 2319 * for SGMII/QSGMII/USXGMII 2320 */ 2321 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII || phy_type == TYPE_USXGMII) 2322 ssc = NO_SSC; 2323 2324 /* PHY configuration specific registers for single link */ 2325 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl, 2326 CLK_ANY, CLK_ANY, 2327 phy_type, TYPE_NONE, 2328 ANY_SSC); 2329 if (link_cmn_vals) { 2330 reg_pairs = link_cmn_vals->reg_pairs; 2331 num_regs = link_cmn_vals->num_regs; 2332 regmap = cdns_phy->regmap_common_cdb; 2333 2334 /** 2335 * First array value in link_cmn_vals must be of 2336 * PHY_PLL_CFG register 2337 */ 2338 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val); 2339 2340 for (i = 1; i < num_regs; i++) 2341 regmap_write(regmap, reg_pairs[i].off, 2342 reg_pairs[i].val); 2343 } 2344 2345 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl, 2346 CLK_ANY, CLK_ANY, 2347 phy_type, TYPE_NONE, 2348 ANY_SSC); 2349 if (xcvr_diag_vals) { 2350 reg_pairs = xcvr_diag_vals->reg_pairs; 2351 num_regs = xcvr_diag_vals->num_regs; 2352 for (i = 0; i < inst->num_lanes; i++) { 2353 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 2354 for (j = 0; j < num_regs; j++) 2355 regmap_write(regmap, reg_pairs[j].off, 2356 reg_pairs[j].val); 2357 } 2358 } 2359 2360 /* PHY PCS common registers configurations */ 2361 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl, 2362 CLK_ANY, CLK_ANY, 2363 phy_type, TYPE_NONE, 2364 ANY_SSC); 2365 if (pcs_cmn_vals) { 2366 reg_pairs = pcs_cmn_vals->reg_pairs; 2367 num_regs = pcs_cmn_vals->num_regs; 2368 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2369 for (i = 0; i < num_regs; i++) 2370 regmap_write(regmap, reg_pairs[i].off, 2371 reg_pairs[i].val); 2372 } 2373 2374 /* PHY PMA common registers configurations */ 2375 phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl, 2376 CLK_ANY, CLK_ANY, 2377 phy_type, TYPE_NONE, 2378 ANY_SSC); 2379 if (phy_pma_cmn_vals) { 2380 reg_pairs = phy_pma_cmn_vals->reg_pairs; 2381 num_regs = phy_pma_cmn_vals->num_regs; 2382 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2383 for (i = 0; i < num_regs; i++) 2384 regmap_write(regmap, reg_pairs[i].off, 2385 reg_pairs[i].val); 2386 } 2387 2388 /* PMA common registers configurations */ 2389 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl, 2390 ref_clk, ref_clk, 2391 phy_type, TYPE_NONE, 2392 ssc); 2393 if (cmn_vals) { 2394 reg_pairs = cmn_vals->reg_pairs; 2395 num_regs = cmn_vals->num_regs; 2396 regmap = cdns_phy->regmap_common_cdb; 2397 for (i = 0; i < num_regs; i++) 2398 regmap_write(regmap, reg_pairs[i].off, 2399 reg_pairs[i].val); 2400 } 2401 2402 /* PMA TX lane registers configurations */ 2403 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl, 2404 ref_clk, ref_clk, 2405 phy_type, TYPE_NONE, 2406 ssc); 2407 if (tx_ln_vals) { 2408 reg_pairs = tx_ln_vals->reg_pairs; 2409 num_regs = tx_ln_vals->num_regs; 2410 for (i = 0; i < inst->num_lanes; i++) { 2411 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 2412 for (j = 0; j < num_regs; j++) 2413 regmap_write(regmap, reg_pairs[j].off, 2414 reg_pairs[j].val); 2415 } 2416 } 2417 2418 /* PMA RX lane registers configurations */ 2419 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl, 2420 ref_clk, ref_clk, 2421 phy_type, TYPE_NONE, 2422 ssc); 2423 if (rx_ln_vals) { 2424 reg_pairs = rx_ln_vals->reg_pairs; 2425 num_regs = rx_ln_vals->num_regs; 2426 for (i = 0; i < inst->num_lanes; i++) { 2427 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane]; 2428 for (j = 0; j < num_regs; j++) 2429 regmap_write(regmap, reg_pairs[j].off, 2430 reg_pairs[j].val); 2431 } 2432 } 2433 2434 if (phy_type == TYPE_DP) 2435 return cdns_torrent_dp_init(phy); 2436 2437 return 0; 2438 } 2439 2440 static const struct phy_ops cdns_torrent_phy_ops = { 2441 .init = cdns_torrent_phy_init, 2442 .configure = cdns_torrent_dp_configure, 2443 .power_on = cdns_torrent_phy_on, 2444 .power_off = cdns_torrent_phy_off, 2445 .owner = THIS_MODULE, 2446 }; 2447 2448 static int cdns_torrent_noop_phy_on(struct phy *phy) 2449 { 2450 /* Give 5ms to 10ms delay for the PIPE clock to be stable */ 2451 usleep_range(5000, 10000); 2452 2453 return 0; 2454 } 2455 2456 static const struct phy_ops noop_ops = { 2457 .power_on = cdns_torrent_noop_phy_on, 2458 .owner = THIS_MODULE, 2459 }; 2460 2461 static 2462 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) 2463 { 2464 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 2465 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 2466 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 2467 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 2468 enum cdns_torrent_phy_type phy_t1, phy_t2; 2469 struct cdns_torrent_vals *pcs_cmn_vals; 2470 int i, j, node, mlane, num_lanes, ret; 2471 struct cdns_reg_pairs *reg_pairs; 2472 enum cdns_torrent_ssc_mode ssc; 2473 struct regmap *regmap; 2474 u32 num_regs; 2475 2476 /* Maximum 2 links (subnodes) are supported */ 2477 if (cdns_phy->nsubnodes != 2) 2478 return -EINVAL; 2479 2480 phy_t1 = cdns_phy->phys[0].phy_type; 2481 phy_t2 = cdns_phy->phys[1].phy_type; 2482 2483 /** 2484 * First configure the PHY for first link with phy_t1. Get the array 2485 * values as [phy_t1][phy_t2][ssc]. 2486 */ 2487 for (node = 0; node < cdns_phy->nsubnodes; node++) { 2488 if (node == 1) { 2489 /** 2490 * If first link with phy_t1 is configured, then 2491 * configure the PHY for second link with phy_t2. 2492 * Get the array values as [phy_t2][phy_t1][ssc]. 2493 */ 2494 swap(phy_t1, phy_t2); 2495 } 2496 2497 mlane = cdns_phy->phys[node].mlane; 2498 ssc = cdns_phy->phys[node].ssc_mode; 2499 num_lanes = cdns_phy->phys[node].num_lanes; 2500 2501 /** 2502 * PHY configuration specific registers: 2503 * link_cmn_vals depend on combination of PHY types being 2504 * configured and are common for both PHY types, so array 2505 * values should be same for [phy_t1][phy_t2][ssc] and 2506 * [phy_t2][phy_t1][ssc]. 2507 * xcvr_diag_vals also depend on combination of PHY types 2508 * being configured, but these can be different for particular 2509 * PHY type and are per lane. 2510 */ 2511 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl, 2512 CLK_ANY, CLK_ANY, 2513 phy_t1, phy_t2, ANY_SSC); 2514 if (link_cmn_vals) { 2515 reg_pairs = link_cmn_vals->reg_pairs; 2516 num_regs = link_cmn_vals->num_regs; 2517 regmap = cdns_phy->regmap_common_cdb; 2518 2519 /** 2520 * First array value in link_cmn_vals must be of 2521 * PHY_PLL_CFG register 2522 */ 2523 regmap_field_write(cdns_phy->phy_pll_cfg, 2524 reg_pairs[0].val); 2525 2526 for (i = 1; i < num_regs; i++) 2527 regmap_write(regmap, reg_pairs[i].off, 2528 reg_pairs[i].val); 2529 } 2530 2531 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl, 2532 CLK_ANY, CLK_ANY, 2533 phy_t1, phy_t2, ANY_SSC); 2534 if (xcvr_diag_vals) { 2535 reg_pairs = xcvr_diag_vals->reg_pairs; 2536 num_regs = xcvr_diag_vals->num_regs; 2537 for (i = 0; i < num_lanes; i++) { 2538 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2539 for (j = 0; j < num_regs; j++) 2540 regmap_write(regmap, reg_pairs[j].off, 2541 reg_pairs[j].val); 2542 } 2543 } 2544 2545 /* PHY PCS common registers configurations */ 2546 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl, 2547 CLK_ANY, CLK_ANY, 2548 phy_t1, phy_t2, ANY_SSC); 2549 if (pcs_cmn_vals) { 2550 reg_pairs = pcs_cmn_vals->reg_pairs; 2551 num_regs = pcs_cmn_vals->num_regs; 2552 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2553 for (i = 0; i < num_regs; i++) 2554 regmap_write(regmap, reg_pairs[i].off, 2555 reg_pairs[i].val); 2556 } 2557 2558 /* PMA common registers configurations */ 2559 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl, 2560 ref_clk, ref_clk, 2561 phy_t1, phy_t2, ssc); 2562 if (cmn_vals) { 2563 reg_pairs = cmn_vals->reg_pairs; 2564 num_regs = cmn_vals->num_regs; 2565 regmap = cdns_phy->regmap_common_cdb; 2566 for (i = 0; i < num_regs; i++) 2567 regmap_write(regmap, reg_pairs[i].off, 2568 reg_pairs[i].val); 2569 } 2570 2571 /* PMA TX lane registers configurations */ 2572 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl, 2573 ref_clk, ref_clk, 2574 phy_t1, phy_t2, ssc); 2575 if (tx_ln_vals) { 2576 reg_pairs = tx_ln_vals->reg_pairs; 2577 num_regs = tx_ln_vals->num_regs; 2578 for (i = 0; i < num_lanes; i++) { 2579 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2580 for (j = 0; j < num_regs; j++) 2581 regmap_write(regmap, reg_pairs[j].off, 2582 reg_pairs[j].val); 2583 } 2584 } 2585 2586 /* PMA RX lane registers configurations */ 2587 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl, 2588 ref_clk, ref_clk, 2589 phy_t1, phy_t2, ssc); 2590 if (rx_ln_vals) { 2591 reg_pairs = rx_ln_vals->reg_pairs; 2592 num_regs = rx_ln_vals->num_regs; 2593 for (i = 0; i < num_lanes; i++) { 2594 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane]; 2595 for (j = 0; j < num_regs; j++) 2596 regmap_write(regmap, reg_pairs[j].off, 2597 reg_pairs[j].val); 2598 } 2599 } 2600 2601 if (phy_t1 == TYPE_DP) { 2602 ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2); 2603 if (ret) 2604 return ret; 2605 } 2606 2607 reset_control_deassert(cdns_phy->phys[node].lnk_rst); 2608 } 2609 2610 /* Take the PHY out of reset */ 2611 ret = reset_control_deassert(cdns_phy->phy_rst); 2612 if (ret) 2613 return ret; 2614 2615 return 0; 2616 } 2617 2618 static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy) 2619 { 2620 struct device *dev = cdns_phy->dev; 2621 2622 of_clk_del_provider(dev->of_node); 2623 } 2624 2625 static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy) 2626 { 2627 struct device *dev = cdns_phy->dev; 2628 struct device_node *node = dev->of_node; 2629 struct clk_hw_onecell_data *data; 2630 int ret; 2631 2632 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL); 2633 if (!data) 2634 return -ENOMEM; 2635 2636 data->num = CDNS_TORRENT_OUTPUT_CLOCKS; 2637 cdns_phy->clk_hw_data = data; 2638 2639 ret = cdns_torrent_derived_refclk_register(cdns_phy); 2640 if (ret) { 2641 dev_err(dev, "failed to register derived refclk\n"); 2642 return ret; 2643 } 2644 2645 ret = cdns_torrent_received_refclk_register(cdns_phy); 2646 if (ret) { 2647 dev_err(dev, "failed to register received refclk\n"); 2648 return ret; 2649 } 2650 2651 ret = cdns_torrent_refclk_driver_register(cdns_phy); 2652 if (ret) { 2653 dev_err(dev, "failed to register refclk driver\n"); 2654 return ret; 2655 } 2656 2657 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data); 2658 if (ret) { 2659 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 2660 return ret; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy) 2667 { 2668 struct device *dev = cdns_phy->dev; 2669 2670 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); 2671 if (IS_ERR(cdns_phy->phy_rst)) { 2672 dev_err(dev, "%s: failed to get reset\n", 2673 dev->of_node->full_name); 2674 return PTR_ERR(cdns_phy->phy_rst); 2675 } 2676 2677 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb"); 2678 if (IS_ERR(cdns_phy->apb_rst)) { 2679 dev_err(dev, "%s: failed to get apb reset\n", 2680 dev->of_node->full_name); 2681 return PTR_ERR(cdns_phy->apb_rst); 2682 } 2683 2684 return 0; 2685 } 2686 2687 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy) 2688 { 2689 struct device *dev = cdns_phy->dev; 2690 unsigned long ref_clk_rate; 2691 int ret; 2692 2693 cdns_phy->clk = devm_clk_get(dev, "refclk"); 2694 if (IS_ERR(cdns_phy->clk)) { 2695 dev_err(dev, "phy ref clock not found\n"); 2696 return PTR_ERR(cdns_phy->clk); 2697 } 2698 2699 ret = clk_prepare_enable(cdns_phy->clk); 2700 if (ret) { 2701 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); 2702 return ret; 2703 } 2704 2705 ref_clk_rate = clk_get_rate(cdns_phy->clk); 2706 if (!ref_clk_rate) { 2707 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); 2708 clk_disable_unprepare(cdns_phy->clk); 2709 return -EINVAL; 2710 } 2711 2712 switch (ref_clk_rate) { 2713 case REF_CLK_19_2MHZ: 2714 cdns_phy->ref_clk_rate = CLK_19_2_MHZ; 2715 break; 2716 case REF_CLK_25MHZ: 2717 cdns_phy->ref_clk_rate = CLK_25_MHZ; 2718 break; 2719 case REF_CLK_100MHZ: 2720 cdns_phy->ref_clk_rate = CLK_100_MHZ; 2721 break; 2722 case REF_CLK_156_25MHZ: 2723 cdns_phy->ref_clk_rate = CLK_156_25_MHZ; 2724 break; 2725 default: 2726 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n"); 2727 clk_disable_unprepare(cdns_phy->clk); 2728 return -EINVAL; 2729 } 2730 2731 return 0; 2732 } 2733 2734 static int cdns_torrent_phy_probe(struct platform_device *pdev) 2735 { 2736 struct cdns_torrent_phy *cdns_phy; 2737 struct device *dev = &pdev->dev; 2738 struct phy_provider *phy_provider; 2739 const struct cdns_torrent_data *data; 2740 struct device_node *child; 2741 int ret, subnodes, node = 0, i; 2742 u32 total_num_lanes = 0; 2743 int already_configured; 2744 u8 init_dp_regmap = 0; 2745 u32 phy_type; 2746 2747 /* Get init data for this PHY */ 2748 data = of_device_get_match_data(dev); 2749 if (!data) 2750 return -EINVAL; 2751 2752 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); 2753 if (!cdns_phy) 2754 return -ENOMEM; 2755 2756 dev_set_drvdata(dev, cdns_phy); 2757 cdns_phy->dev = dev; 2758 cdns_phy->init_data = data; 2759 2760 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0); 2761 if (IS_ERR(cdns_phy->sd_base)) 2762 return PTR_ERR(cdns_phy->sd_base); 2763 2764 subnodes = of_get_available_child_count(dev->of_node); 2765 if (subnodes == 0) { 2766 dev_err(dev, "No available link subnodes found\n"); 2767 return -EINVAL; 2768 } 2769 2770 ret = cdns_torrent_regmap_init(cdns_phy); 2771 if (ret) 2772 return ret; 2773 2774 ret = cdns_torrent_regfield_init(cdns_phy); 2775 if (ret) 2776 return ret; 2777 2778 ret = cdns_torrent_clk_register(cdns_phy); 2779 if (ret) 2780 return ret; 2781 2782 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured); 2783 2784 if (!already_configured) { 2785 ret = cdns_torrent_reset(cdns_phy); 2786 if (ret) 2787 goto clk_cleanup; 2788 2789 ret = cdns_torrent_clk(cdns_phy); 2790 if (ret) 2791 goto clk_cleanup; 2792 2793 /* Enable APB */ 2794 reset_control_deassert(cdns_phy->apb_rst); 2795 } 2796 2797 for_each_available_child_of_node(dev->of_node, child) { 2798 struct phy *gphy; 2799 2800 /* PHY subnode name must be 'phy'. */ 2801 if (!(of_node_name_eq(child, "phy"))) 2802 continue; 2803 2804 cdns_phy->phys[node].lnk_rst = 2805 of_reset_control_array_get_exclusive(child); 2806 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) { 2807 dev_err(dev, "%s: failed to get reset\n", 2808 child->full_name); 2809 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst); 2810 goto put_lnk_rst; 2811 } 2812 2813 if (of_property_read_u32(child, "reg", 2814 &cdns_phy->phys[node].mlane)) { 2815 dev_err(dev, "%s: No \"reg\"-property.\n", 2816 child->full_name); 2817 ret = -EINVAL; 2818 goto put_child; 2819 } 2820 2821 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) { 2822 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n", 2823 child->full_name); 2824 ret = -EINVAL; 2825 goto put_child; 2826 } 2827 2828 switch (phy_type) { 2829 case PHY_TYPE_PCIE: 2830 cdns_phy->phys[node].phy_type = TYPE_PCIE; 2831 break; 2832 case PHY_TYPE_DP: 2833 cdns_phy->phys[node].phy_type = TYPE_DP; 2834 break; 2835 case PHY_TYPE_SGMII: 2836 cdns_phy->phys[node].phy_type = TYPE_SGMII; 2837 break; 2838 case PHY_TYPE_QSGMII: 2839 cdns_phy->phys[node].phy_type = TYPE_QSGMII; 2840 break; 2841 case PHY_TYPE_USB3: 2842 cdns_phy->phys[node].phy_type = TYPE_USB; 2843 break; 2844 case PHY_TYPE_USXGMII: 2845 cdns_phy->phys[node].phy_type = TYPE_USXGMII; 2846 break; 2847 default: 2848 dev_err(dev, "Unsupported protocol\n"); 2849 ret = -EINVAL; 2850 goto put_child; 2851 } 2852 2853 if (of_property_read_u32(child, "cdns,num-lanes", 2854 &cdns_phy->phys[node].num_lanes)) { 2855 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n", 2856 child->full_name); 2857 ret = -EINVAL; 2858 goto put_child; 2859 } 2860 2861 total_num_lanes += cdns_phy->phys[node].num_lanes; 2862 2863 /* Get SSC mode */ 2864 cdns_phy->phys[node].ssc_mode = NO_SSC; 2865 of_property_read_u32(child, "cdns,ssc-mode", 2866 &cdns_phy->phys[node].ssc_mode); 2867 2868 if (!already_configured) 2869 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); 2870 else 2871 gphy = devm_phy_create(dev, child, &noop_ops); 2872 if (IS_ERR(gphy)) { 2873 ret = PTR_ERR(gphy); 2874 goto put_child; 2875 } 2876 2877 if (cdns_phy->phys[node].phy_type == TYPE_DP) { 2878 switch (cdns_phy->phys[node].num_lanes) { 2879 case 1: 2880 case 2: 2881 case 4: 2882 /* valid number of lanes */ 2883 break; 2884 default: 2885 dev_err(dev, "unsupported number of lanes: %d\n", 2886 cdns_phy->phys[node].num_lanes); 2887 ret = -EINVAL; 2888 goto put_child; 2889 } 2890 2891 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; 2892 of_property_read_u32(child, "cdns,max-bit-rate", 2893 &cdns_phy->max_bit_rate); 2894 2895 switch (cdns_phy->max_bit_rate) { 2896 case 1620: 2897 case 2160: 2898 case 2430: 2899 case 2700: 2900 case 3240: 2901 case 4320: 2902 case 5400: 2903 case 8100: 2904 /* valid bit rate */ 2905 break; 2906 default: 2907 dev_err(dev, "unsupported max bit rate: %dMbps\n", 2908 cdns_phy->max_bit_rate); 2909 ret = -EINVAL; 2910 goto put_child; 2911 } 2912 2913 /* DPTX registers */ 2914 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1); 2915 if (IS_ERR(cdns_phy->base)) { 2916 ret = PTR_ERR(cdns_phy->base); 2917 goto put_child; 2918 } 2919 2920 if (!init_dp_regmap) { 2921 ret = cdns_torrent_dp_regmap_init(cdns_phy); 2922 if (ret) 2923 goto put_child; 2924 2925 ret = cdns_torrent_dp_regfield_init(cdns_phy); 2926 if (ret) 2927 goto put_child; 2928 2929 init_dp_regmap++; 2930 } 2931 2932 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n", 2933 cdns_phy->max_bit_rate / 1000, 2934 cdns_phy->max_bit_rate % 1000); 2935 2936 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes; 2937 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate; 2938 gphy->attrs.mode = PHY_MODE_DP; 2939 } 2940 2941 cdns_phy->phys[node].phy = gphy; 2942 phy_set_drvdata(gphy, &cdns_phy->phys[node]); 2943 2944 node++; 2945 } 2946 cdns_phy->nsubnodes = node; 2947 2948 if (total_num_lanes > MAX_NUM_LANES) { 2949 dev_err(dev, "Invalid lane configuration\n"); 2950 ret = -EINVAL; 2951 goto put_lnk_rst; 2952 } 2953 2954 if (cdns_phy->nsubnodes > 1 && !already_configured) { 2955 ret = cdns_torrent_phy_configure_multilink(cdns_phy); 2956 if (ret) 2957 goto put_lnk_rst; 2958 } 2959 2960 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2961 if (IS_ERR(phy_provider)) { 2962 ret = PTR_ERR(phy_provider); 2963 goto put_lnk_rst; 2964 } 2965 2966 if (cdns_phy->nsubnodes > 1) 2967 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)", 2968 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), 2969 cdns_phy->phys[0].num_lanes, 2970 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type), 2971 cdns_phy->phys[1].num_lanes); 2972 else 2973 dev_dbg(dev, "Single link: %s (%d lanes)", 2974 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), 2975 cdns_phy->phys[0].num_lanes); 2976 2977 return 0; 2978 2979 put_child: 2980 node++; 2981 put_lnk_rst: 2982 for (i = 0; i < node; i++) 2983 reset_control_put(cdns_phy->phys[i].lnk_rst); 2984 of_node_put(child); 2985 reset_control_assert(cdns_phy->apb_rst); 2986 clk_disable_unprepare(cdns_phy->clk); 2987 clk_cleanup: 2988 cdns_torrent_clk_cleanup(cdns_phy); 2989 return ret; 2990 } 2991 2992 static void cdns_torrent_phy_remove(struct platform_device *pdev) 2993 { 2994 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev); 2995 int i; 2996 2997 reset_control_assert(cdns_phy->phy_rst); 2998 reset_control_assert(cdns_phy->apb_rst); 2999 for (i = 0; i < cdns_phy->nsubnodes; i++) { 3000 reset_control_assert(cdns_phy->phys[i].lnk_rst); 3001 reset_control_put(cdns_phy->phys[i].lnk_rst); 3002 } 3003 3004 clk_disable_unprepare(cdns_phy->clk); 3005 cdns_torrent_clk_cleanup(cdns_phy); 3006 } 3007 3008 /* USB and DP link configuration */ 3009 static struct cdns_reg_pairs usb_dp_link_cmn_regs[] = { 3010 {0x0002, PHY_PLL_CFG}, 3011 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 3012 }; 3013 3014 static struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = { 3015 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3016 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3017 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3018 }; 3019 3020 static struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = { 3021 {0x0001, XCVR_DIAG_HSCLK_SEL}, 3022 {0x0009, XCVR_DIAG_PLLDRC_CTRL} 3023 }; 3024 3025 static struct cdns_torrent_vals usb_dp_link_cmn_vals = { 3026 .reg_pairs = usb_dp_link_cmn_regs, 3027 .num_regs = ARRAY_SIZE(usb_dp_link_cmn_regs), 3028 }; 3029 3030 static struct cdns_torrent_vals usb_dp_xcvr_diag_ln_vals = { 3031 .reg_pairs = usb_dp_xcvr_diag_ln_regs, 3032 .num_regs = ARRAY_SIZE(usb_dp_xcvr_diag_ln_regs), 3033 }; 3034 3035 static struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = { 3036 .reg_pairs = dp_usb_xcvr_diag_ln_regs, 3037 .num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs), 3038 }; 3039 3040 /* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */ 3041 static struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = { 3042 {0x0040, PHY_PMA_CMN_CTRL1}, 3043 }; 3044 3045 static struct cdns_torrent_vals ti_usxgmii_phy_pma_cmn_vals = { 3046 .reg_pairs = ti_usxgmii_phy_pma_cmn_regs, 3047 .num_regs = ARRAY_SIZE(ti_usxgmii_phy_pma_cmn_regs), 3048 }; 3049 3050 /* Single USXGMII link configuration */ 3051 static struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = { 3052 {0x0000, PHY_PLL_CFG}, 3053 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0} 3054 }; 3055 3056 static struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = { 3057 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3058 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3059 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 3060 }; 3061 3062 static struct cdns_torrent_vals sl_usxgmii_link_cmn_vals = { 3063 .reg_pairs = sl_usxgmii_link_cmn_regs, 3064 .num_regs = ARRAY_SIZE(sl_usxgmii_link_cmn_regs), 3065 }; 3066 3067 static struct cdns_torrent_vals sl_usxgmii_xcvr_diag_ln_vals = { 3068 .reg_pairs = sl_usxgmii_xcvr_diag_ln_regs, 3069 .num_regs = ARRAY_SIZE(sl_usxgmii_xcvr_diag_ln_regs), 3070 }; 3071 3072 /* Single link USXGMII, 156.25 MHz Ref clk, no SSC */ 3073 static struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = { 3074 {0x0014, CMN_SSM_BIAS_TMR}, 3075 {0x0028, CMN_PLLSM0_PLLPRE_TMR}, 3076 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR}, 3077 {0x0028, CMN_PLLSM1_PLLPRE_TMR}, 3078 {0x00A4, CMN_PLLSM1_PLLLOCK_TMR}, 3079 {0x0062, CMN_BGCAL_INIT_TMR}, 3080 {0x0062, CMN_BGCAL_ITER_TMR}, 3081 {0x0014, CMN_IBCAL_INIT_TMR}, 3082 {0x0018, CMN_TXPUCAL_INIT_TMR}, 3083 {0x0005, CMN_TXPUCAL_ITER_TMR}, 3084 {0x0018, CMN_TXPDCAL_INIT_TMR}, 3085 {0x0005, CMN_TXPDCAL_ITER_TMR}, 3086 {0x024A, CMN_RXCAL_INIT_TMR}, 3087 {0x0005, CMN_RXCAL_ITER_TMR}, 3088 {0x000B, CMN_SD_CAL_REFTIM_START}, 3089 {0x0132, CMN_SD_CAL_PLLCNT_START}, 3090 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3091 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0}, 3092 {0x0014, CMN_PLL1_DSM_FBH_OVRD_M0}, 3093 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0}, 3094 {0x0005, CMN_PLL1_DSM_FBL_OVRD_M0}, 3095 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR}, 3096 {0x061B, CMN_PLL1_VCOCAL_INIT_TMR}, 3097 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR}, 3098 {0x0019, CMN_PLL1_VCOCAL_ITER_TMR}, 3099 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START}, 3100 {0x1354, CMN_PLL1_VCOCAL_REFTIM_START}, 3101 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START}, 3102 {0x1354, CMN_PLL1_VCOCAL_PLLCNT_START}, 3103 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3104 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3105 {0x0138, CMN_PLL0_LOCK_REFCNT_START}, 3106 {0x0138, CMN_PLL1_LOCK_REFCNT_START}, 3107 {0x0138, CMN_PLL0_LOCK_PLLCNT_START}, 3108 {0x0138, CMN_PLL1_LOCK_PLLCNT_START} 3109 }; 3110 3111 static struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = { 3112 {0x07A2, TX_RCVDET_ST_TMR}, 3113 {0x00F3, TX_PSC_A0}, 3114 {0x04A2, TX_PSC_A2}, 3115 {0x04A2, TX_PSC_A3}, 3116 {0x0000, TX_TXCC_CPOST_MULT_00}, 3117 {0x0000, XCVR_DIAG_PSC_OVRD} 3118 }; 3119 3120 static struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = { 3121 {0x0014, RX_SDCAL0_INIT_TMR}, 3122 {0x0062, RX_SDCAL0_ITER_TMR}, 3123 {0x0014, RX_SDCAL1_INIT_TMR}, 3124 {0x0062, RX_SDCAL1_ITER_TMR}, 3125 {0x091D, RX_PSC_A0}, 3126 {0x0900, RX_PSC_A2}, 3127 {0x0100, RX_PSC_A3}, 3128 {0x0030, RX_REE_SMGM_CTRL1}, 3129 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3130 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3131 {0x0000, RX_DIAG_DFE_CTRL}, 3132 {0x0019, RX_REE_TAP1_CLIP}, 3133 {0x0019, RX_REE_TAP2TON_CLIP}, 3134 {0x00B9, RX_DIAG_NQST_CTRL}, 3135 {0x0C21, RX_DIAG_DFE_AMP_TUNE_2}, 3136 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 3137 {0x0033, RX_DIAG_PI_RATE}, 3138 {0x0001, RX_DIAG_ACYA}, 3139 {0x018C, RX_CDRLF_CNFG} 3140 }; 3141 3142 static struct cdns_torrent_vals sl_usxgmii_156_25_no_ssc_cmn_vals = { 3143 .reg_pairs = sl_usxgmii_156_25_no_ssc_cmn_regs, 3144 .num_regs = ARRAY_SIZE(sl_usxgmii_156_25_no_ssc_cmn_regs), 3145 }; 3146 3147 static struct cdns_torrent_vals usxgmii_156_25_no_ssc_tx_ln_vals = { 3148 .reg_pairs = usxgmii_156_25_no_ssc_tx_ln_regs, 3149 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_tx_ln_regs), 3150 }; 3151 3152 static struct cdns_torrent_vals usxgmii_156_25_no_ssc_rx_ln_vals = { 3153 .reg_pairs = usxgmii_156_25_no_ssc_rx_ln_regs, 3154 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_rx_ln_regs), 3155 }; 3156 3157 /* PCIe and DP link configuration */ 3158 static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = { 3159 {0x0003, PHY_PLL_CFG}, 3160 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3161 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1} 3162 }; 3163 3164 static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = { 3165 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3166 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3167 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3168 }; 3169 3170 static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = { 3171 {0x0001, XCVR_DIAG_HSCLK_SEL}, 3172 {0x0009, XCVR_DIAG_PLLDRC_CTRL} 3173 }; 3174 3175 static struct cdns_torrent_vals pcie_dp_link_cmn_vals = { 3176 .reg_pairs = pcie_dp_link_cmn_regs, 3177 .num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs), 3178 }; 3179 3180 static struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = { 3181 .reg_pairs = pcie_dp_xcvr_diag_ln_regs, 3182 .num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs), 3183 }; 3184 3185 static struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = { 3186 .reg_pairs = dp_pcie_xcvr_diag_ln_regs, 3187 .num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs), 3188 }; 3189 3190 /* DP Multilink, 100 MHz Ref clk, no SSC */ 3191 static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = { 3192 {0x007F, CMN_TXPUCAL_TUNE}, 3193 {0x007F, CMN_TXPDCAL_TUNE} 3194 }; 3195 3196 static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = { 3197 {0x00FB, TX_PSC_A0}, 3198 {0x04AA, TX_PSC_A2}, 3199 {0x04AA, TX_PSC_A3}, 3200 {0x000F, XCVR_DIAG_BIDI_CTRL} 3201 }; 3202 3203 static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = { 3204 {0x0000, RX_PSC_A0}, 3205 {0x0000, RX_PSC_A2}, 3206 {0x0000, RX_PSC_A3}, 3207 {0x0000, RX_PSC_CAL}, 3208 {0x0000, RX_REE_GCSM1_CTRL}, 3209 {0x0000, RX_REE_GCSM2_CTRL}, 3210 {0x0000, RX_REE_PERGCSM_CTRL} 3211 }; 3212 3213 static struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = { 3214 .reg_pairs = dp_100_no_ssc_cmn_regs, 3215 .num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs), 3216 }; 3217 3218 static struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = { 3219 .reg_pairs = dp_100_no_ssc_tx_ln_regs, 3220 .num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs), 3221 }; 3222 3223 static struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = { 3224 .reg_pairs = dp_100_no_ssc_rx_ln_regs, 3225 .num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs), 3226 }; 3227 3228 /* Single DisplayPort(DP) link configuration */ 3229 static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = { 3230 {0x0000, PHY_PLL_CFG}, 3231 }; 3232 3233 static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = { 3234 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3235 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 3236 }; 3237 3238 static struct cdns_torrent_vals sl_dp_link_cmn_vals = { 3239 .reg_pairs = sl_dp_link_cmn_regs, 3240 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs), 3241 }; 3242 3243 static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = { 3244 .reg_pairs = sl_dp_xcvr_diag_ln_regs, 3245 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs), 3246 }; 3247 3248 /* Single DP, 19.2 MHz Ref clk, no SSC */ 3249 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = { 3250 {0x0014, CMN_SSM_BIAS_TMR}, 3251 {0x0027, CMN_PLLSM0_PLLPRE_TMR}, 3252 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR}, 3253 {0x0027, CMN_PLLSM1_PLLPRE_TMR}, 3254 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR}, 3255 {0x0060, CMN_BGCAL_INIT_TMR}, 3256 {0x0060, CMN_BGCAL_ITER_TMR}, 3257 {0x0014, CMN_IBCAL_INIT_TMR}, 3258 {0x0018, CMN_TXPUCAL_INIT_TMR}, 3259 {0x0005, CMN_TXPUCAL_ITER_TMR}, 3260 {0x0018, CMN_TXPDCAL_INIT_TMR}, 3261 {0x0005, CMN_TXPDCAL_ITER_TMR}, 3262 {0x0240, CMN_RXCAL_INIT_TMR}, 3263 {0x0005, CMN_RXCAL_ITER_TMR}, 3264 {0x0002, CMN_SD_CAL_INIT_TMR}, 3265 {0x0002, CMN_SD_CAL_ITER_TMR}, 3266 {0x000B, CMN_SD_CAL_REFTIM_START}, 3267 {0x0137, CMN_SD_CAL_PLLCNT_START}, 3268 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3269 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3270 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3271 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3272 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3273 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3274 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3275 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3276 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR}, 3277 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 3278 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR}, 3279 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 3280 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START}, 3281 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3282 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START}, 3283 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3284 }; 3285 3286 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = { 3287 {0x0780, TX_RCVDET_ST_TMR}, 3288 {0x00FB, TX_PSC_A0}, 3289 {0x04AA, TX_PSC_A2}, 3290 {0x04AA, TX_PSC_A3}, 3291 {0x000F, XCVR_DIAG_BIDI_CTRL} 3292 }; 3293 3294 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = { 3295 {0x0000, RX_PSC_A0}, 3296 {0x0000, RX_PSC_A2}, 3297 {0x0000, RX_PSC_A3}, 3298 {0x0000, RX_PSC_CAL}, 3299 {0x0000, RX_REE_GCSM1_CTRL}, 3300 {0x0000, RX_REE_GCSM2_CTRL}, 3301 {0x0000, RX_REE_PERGCSM_CTRL} 3302 }; 3303 3304 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = { 3305 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs, 3306 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs), 3307 }; 3308 3309 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = { 3310 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs, 3311 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs), 3312 }; 3313 3314 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = { 3315 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs, 3316 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs), 3317 }; 3318 3319 /* Single DP, 25 MHz Ref clk, no SSC */ 3320 static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = { 3321 {0x0019, CMN_SSM_BIAS_TMR}, 3322 {0x0032, CMN_PLLSM0_PLLPRE_TMR}, 3323 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR}, 3324 {0x0032, CMN_PLLSM1_PLLPRE_TMR}, 3325 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR}, 3326 {0x007D, CMN_BGCAL_INIT_TMR}, 3327 {0x007D, CMN_BGCAL_ITER_TMR}, 3328 {0x0019, CMN_IBCAL_INIT_TMR}, 3329 {0x001E, CMN_TXPUCAL_INIT_TMR}, 3330 {0x0006, CMN_TXPUCAL_ITER_TMR}, 3331 {0x001E, CMN_TXPDCAL_INIT_TMR}, 3332 {0x0006, CMN_TXPDCAL_ITER_TMR}, 3333 {0x02EE, CMN_RXCAL_INIT_TMR}, 3334 {0x0006, CMN_RXCAL_ITER_TMR}, 3335 {0x0002, CMN_SD_CAL_INIT_TMR}, 3336 {0x0002, CMN_SD_CAL_ITER_TMR}, 3337 {0x000E, CMN_SD_CAL_REFTIM_START}, 3338 {0x012B, CMN_SD_CAL_PLLCNT_START}, 3339 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3340 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3341 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3342 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3343 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3344 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3345 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3346 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3347 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR}, 3348 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 3349 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR}, 3350 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 3351 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START}, 3352 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3353 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START}, 3354 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3355 }; 3356 3357 static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = { 3358 {0x09C4, TX_RCVDET_ST_TMR}, 3359 {0x00FB, TX_PSC_A0}, 3360 {0x04AA, TX_PSC_A2}, 3361 {0x04AA, TX_PSC_A3}, 3362 {0x000F, XCVR_DIAG_BIDI_CTRL} 3363 }; 3364 3365 static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = { 3366 {0x0000, RX_PSC_A0}, 3367 {0x0000, RX_PSC_A2}, 3368 {0x0000, RX_PSC_A3}, 3369 {0x0000, RX_PSC_CAL}, 3370 {0x0000, RX_REE_GCSM1_CTRL}, 3371 {0x0000, RX_REE_GCSM2_CTRL}, 3372 {0x0000, RX_REE_PERGCSM_CTRL} 3373 }; 3374 3375 static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = { 3376 .reg_pairs = sl_dp_25_no_ssc_cmn_regs, 3377 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs), 3378 }; 3379 3380 static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = { 3381 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs, 3382 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs), 3383 }; 3384 3385 static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = { 3386 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs, 3387 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs), 3388 }; 3389 3390 /* Single DP, 100 MHz Ref clk, no SSC */ 3391 static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = { 3392 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3393 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3394 }; 3395 3396 static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = { 3397 {0x00FB, TX_PSC_A0}, 3398 {0x04AA, TX_PSC_A2}, 3399 {0x04AA, TX_PSC_A3}, 3400 {0x000F, XCVR_DIAG_BIDI_CTRL} 3401 }; 3402 3403 static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = { 3404 {0x0000, RX_PSC_A0}, 3405 {0x0000, RX_PSC_A2}, 3406 {0x0000, RX_PSC_A3}, 3407 {0x0000, RX_PSC_CAL}, 3408 {0x0000, RX_REE_GCSM1_CTRL}, 3409 {0x0000, RX_REE_GCSM2_CTRL}, 3410 {0x0000, RX_REE_PERGCSM_CTRL} 3411 }; 3412 3413 static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = { 3414 .reg_pairs = sl_dp_100_no_ssc_cmn_regs, 3415 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs), 3416 }; 3417 3418 static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = { 3419 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs, 3420 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs), 3421 }; 3422 3423 static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = { 3424 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs, 3425 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs), 3426 }; 3427 3428 /* USB and SGMII/QSGMII link configuration */ 3429 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = { 3430 {0x0002, PHY_PLL_CFG}, 3431 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3432 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3433 }; 3434 3435 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = { 3436 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3437 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3438 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3439 }; 3440 3441 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = { 3442 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3443 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3444 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 3445 }; 3446 3447 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = { 3448 .reg_pairs = usb_sgmii_link_cmn_regs, 3449 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs), 3450 }; 3451 3452 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = { 3453 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs, 3454 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs), 3455 }; 3456 3457 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = { 3458 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs, 3459 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs), 3460 }; 3461 3462 /* PCIe and USB Unique SSC link configuration */ 3463 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = { 3464 {0x0003, PHY_PLL_CFG}, 3465 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3466 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3467 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0} 3468 }; 3469 3470 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = { 3471 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3472 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3473 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3474 }; 3475 3476 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = { 3477 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3478 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3479 {0x00C9, XCVR_DIAG_PLLDRC_CTRL} 3480 }; 3481 3482 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = { 3483 .reg_pairs = pcie_usb_link_cmn_regs, 3484 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs), 3485 }; 3486 3487 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = { 3488 .reg_pairs = pcie_usb_xcvr_diag_ln_regs, 3489 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs), 3490 }; 3491 3492 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = { 3493 .reg_pairs = usb_pcie_xcvr_diag_ln_regs, 3494 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs), 3495 }; 3496 3497 /* USB 100 MHz Ref clk, internal SSC */ 3498 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { 3499 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3500 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3501 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3502 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3503 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3504 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3505 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3506 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3507 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3508 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3509 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3510 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3511 {0x0064, CMN_PLL0_INTDIV_M0}, 3512 {0x0050, CMN_PLL0_INTDIV_M1}, 3513 {0x0064, CMN_PLL1_INTDIV_M0}, 3514 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3515 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3516 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3517 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3518 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3519 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3520 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3521 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3522 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3523 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3524 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3525 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3526 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3527 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3528 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3529 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3530 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3531 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3532 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3533 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3534 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3535 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3536 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3537 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3538 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3539 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3540 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3541 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3542 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3543 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3544 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3545 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3546 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 3547 {0x007F, CMN_TXPUCAL_TUNE}, 3548 {0x007F, CMN_TXPDCAL_TUNE} 3549 }; 3550 3551 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = { 3552 .reg_pairs = usb_100_int_ssc_cmn_regs, 3553 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs), 3554 }; 3555 3556 /* Single USB link configuration */ 3557 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { 3558 {0x0000, PHY_PLL_CFG}, 3559 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 3560 }; 3561 3562 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { 3563 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3564 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3565 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3566 }; 3567 3568 static struct cdns_torrent_vals sl_usb_link_cmn_vals = { 3569 .reg_pairs = sl_usb_link_cmn_regs, 3570 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs), 3571 }; 3572 3573 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = { 3574 .reg_pairs = sl_usb_xcvr_diag_ln_regs, 3575 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs), 3576 }; 3577 3578 /* USB PHY PCS common configuration */ 3579 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { 3580 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0}, 3581 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0}, 3582 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1} 3583 }; 3584 3585 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = { 3586 .reg_pairs = usb_phy_pcs_cmn_regs, 3587 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs), 3588 }; 3589 3590 /* USB 100 MHz Ref clk, no SSC */ 3591 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { 3592 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3593 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3594 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3595 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3596 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3597 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3598 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 3599 }; 3600 3601 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = { 3602 .reg_pairs = sl_usb_100_no_ssc_cmn_regs, 3603 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs), 3604 }; 3605 3606 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { 3607 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3608 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 3609 {0x007F, CMN_TXPUCAL_TUNE}, 3610 {0x007F, CMN_TXPDCAL_TUNE} 3611 }; 3612 3613 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { 3614 {0x02FF, TX_PSC_A0}, 3615 {0x06AF, TX_PSC_A1}, 3616 {0x06AE, TX_PSC_A2}, 3617 {0x06AE, TX_PSC_A3}, 3618 {0x2A82, TX_TXCC_CTRL}, 3619 {0x0014, TX_TXCC_CPOST_MULT_01}, 3620 {0x0003, XCVR_DIAG_PSC_OVRD} 3621 }; 3622 3623 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { 3624 {0x0D1D, RX_PSC_A0}, 3625 {0x0D1D, RX_PSC_A1}, 3626 {0x0D00, RX_PSC_A2}, 3627 {0x0500, RX_PSC_A3}, 3628 {0x0013, RX_SIGDET_HL_FILT_TMR}, 3629 {0x0000, RX_REE_GCSM1_CTRL}, 3630 {0x0C02, RX_REE_ATTEN_THR}, 3631 {0x0330, RX_REE_SMGM_CTRL1}, 3632 {0x0300, RX_REE_SMGM_CTRL2}, 3633 {0x0019, RX_REE_TAP1_CLIP}, 3634 {0x0019, RX_REE_TAP2TON_CLIP}, 3635 {0x1004, RX_DIAG_SIGDET_TUNE}, 3636 {0x00F9, RX_DIAG_NQST_CTRL}, 3637 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3638 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 3639 {0x0000, RX_DIAG_PI_CAP}, 3640 {0x0031, RX_DIAG_PI_RATE}, 3641 {0x0001, RX_DIAG_ACYA}, 3642 {0x018C, RX_CDRLF_CNFG}, 3643 {0x0003, RX_CDRLF_CNFG3} 3644 }; 3645 3646 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = { 3647 .reg_pairs = usb_100_no_ssc_cmn_regs, 3648 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs), 3649 }; 3650 3651 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = { 3652 .reg_pairs = usb_100_no_ssc_tx_ln_regs, 3653 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs), 3654 }; 3655 3656 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = { 3657 .reg_pairs = usb_100_no_ssc_rx_ln_regs, 3658 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs), 3659 }; 3660 3661 /* Single link USB, 100 MHz Ref clk, internal SSC */ 3662 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { 3663 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3664 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3665 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3666 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3667 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3668 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3669 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3670 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3671 {0x0064, CMN_PLL0_INTDIV_M0}, 3672 {0x0064, CMN_PLL1_INTDIV_M0}, 3673 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3674 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3675 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3676 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3677 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3678 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3679 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3680 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3681 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3682 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3683 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3684 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3685 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3686 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3687 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3688 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3689 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3690 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3691 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3692 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3693 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3694 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3695 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3696 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3697 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3698 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3699 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3700 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 3701 }; 3702 3703 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = { 3704 .reg_pairs = sl_usb_100_int_ssc_cmn_regs, 3705 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs), 3706 }; 3707 3708 /* PCIe and SGMII/QSGMII Unique SSC link configuration */ 3709 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { 3710 {0x0003, PHY_PLL_CFG}, 3711 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3712 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3713 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3714 }; 3715 3716 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { 3717 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3718 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3719 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3720 }; 3721 3722 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { 3723 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3724 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3725 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 3726 }; 3727 3728 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = { 3729 .reg_pairs = pcie_sgmii_link_cmn_regs, 3730 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs), 3731 }; 3732 3733 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = { 3734 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs, 3735 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs), 3736 }; 3737 3738 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = { 3739 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs, 3740 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs), 3741 }; 3742 3743 /* SGMII 100 MHz Ref clk, no SSC */ 3744 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { 3745 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3746 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3747 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3748 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3749 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3750 }; 3751 3752 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = { 3753 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs, 3754 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs), 3755 }; 3756 3757 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { 3758 {0x007F, CMN_TXPUCAL_TUNE}, 3759 {0x007F, CMN_TXPDCAL_TUNE} 3760 }; 3761 3762 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { 3763 {0x00F3, TX_PSC_A0}, 3764 {0x04A2, TX_PSC_A2}, 3765 {0x04A2, TX_PSC_A3}, 3766 {0x0000, TX_TXCC_CPOST_MULT_00}, 3767 {0x00B3, DRV_DIAG_TX_DRV} 3768 }; 3769 3770 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { 3771 {0x00F3, TX_PSC_A0}, 3772 {0x04A2, TX_PSC_A2}, 3773 {0x04A2, TX_PSC_A3}, 3774 {0x0000, TX_TXCC_CPOST_MULT_00}, 3775 {0x00B3, DRV_DIAG_TX_DRV}, 3776 {0x4000, XCVR_DIAG_RXCLK_CTRL}, 3777 }; 3778 3779 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { 3780 {0x091D, RX_PSC_A0}, 3781 {0x0900, RX_PSC_A2}, 3782 {0x0100, RX_PSC_A3}, 3783 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3784 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3785 {0x0000, RX_DIAG_DFE_CTRL}, 3786 {0x0019, RX_REE_TAP1_CLIP}, 3787 {0x0019, RX_REE_TAP2TON_CLIP}, 3788 {0x0098, RX_DIAG_NQST_CTRL}, 3789 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3790 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 3791 {0x0000, RX_DIAG_PI_CAP}, 3792 {0x0010, RX_DIAG_PI_RATE}, 3793 {0x0001, RX_DIAG_ACYA}, 3794 {0x018C, RX_CDRLF_CNFG}, 3795 }; 3796 3797 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = { 3798 .reg_pairs = sgmii_100_no_ssc_cmn_regs, 3799 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs), 3800 }; 3801 3802 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = { 3803 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs, 3804 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs), 3805 }; 3806 3807 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = { 3808 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs, 3809 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs), 3810 }; 3811 3812 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = { 3813 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs, 3814 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs), 3815 }; 3816 3817 /* SGMII 100 MHz Ref clk, internal SSC */ 3818 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { 3819 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3820 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3821 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3822 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3823 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3824 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3825 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3826 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3827 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3828 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3829 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3830 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3831 {0x0064, CMN_PLL0_INTDIV_M0}, 3832 {0x0050, CMN_PLL0_INTDIV_M1}, 3833 {0x0064, CMN_PLL1_INTDIV_M0}, 3834 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3835 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3836 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3837 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3838 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3839 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3840 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3841 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3842 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3843 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3844 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3845 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3846 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3847 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3848 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3849 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3850 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3851 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3852 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3853 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3854 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3855 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3856 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3857 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3858 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3859 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3860 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3861 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3862 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3863 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3864 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3865 {0x007F, CMN_TXPUCAL_TUNE}, 3866 {0x007F, CMN_TXPDCAL_TUNE} 3867 }; 3868 3869 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { 3870 .reg_pairs = sgmii_100_int_ssc_cmn_regs, 3871 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs), 3872 }; 3873 3874 /* QSGMII 100 MHz Ref clk, no SSC */ 3875 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { 3876 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3877 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3878 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3879 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3880 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3881 }; 3882 3883 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = { 3884 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs, 3885 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs), 3886 }; 3887 3888 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { 3889 {0x007F, CMN_TXPUCAL_TUNE}, 3890 {0x007F, CMN_TXPDCAL_TUNE} 3891 }; 3892 3893 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { 3894 {0x00F3, TX_PSC_A0}, 3895 {0x04A2, TX_PSC_A2}, 3896 {0x04A2, TX_PSC_A3}, 3897 {0x0000, TX_TXCC_CPOST_MULT_00}, 3898 {0x0011, TX_TXCC_MGNFS_MULT_100}, 3899 {0x0003, DRV_DIAG_TX_DRV} 3900 }; 3901 3902 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { 3903 {0x00F3, TX_PSC_A0}, 3904 {0x04A2, TX_PSC_A2}, 3905 {0x04A2, TX_PSC_A3}, 3906 {0x0000, TX_TXCC_CPOST_MULT_00}, 3907 {0x0011, TX_TXCC_MGNFS_MULT_100}, 3908 {0x0003, DRV_DIAG_TX_DRV}, 3909 {0x4000, XCVR_DIAG_RXCLK_CTRL}, 3910 }; 3911 3912 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { 3913 {0x091D, RX_PSC_A0}, 3914 {0x0900, RX_PSC_A2}, 3915 {0x0100, RX_PSC_A3}, 3916 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3917 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3918 {0x0000, RX_DIAG_DFE_CTRL}, 3919 {0x0019, RX_REE_TAP1_CLIP}, 3920 {0x0019, RX_REE_TAP2TON_CLIP}, 3921 {0x0098, RX_DIAG_NQST_CTRL}, 3922 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3923 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 3924 {0x0000, RX_DIAG_PI_CAP}, 3925 {0x0010, RX_DIAG_PI_RATE}, 3926 {0x0001, RX_DIAG_ACYA}, 3927 {0x018C, RX_CDRLF_CNFG}, 3928 }; 3929 3930 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = { 3931 .reg_pairs = qsgmii_100_no_ssc_cmn_regs, 3932 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs), 3933 }; 3934 3935 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = { 3936 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs, 3937 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs), 3938 }; 3939 3940 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = { 3941 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs, 3942 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs), 3943 }; 3944 3945 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = { 3946 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs, 3947 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs), 3948 }; 3949 3950 /* QSGMII 100 MHz Ref clk, internal SSC */ 3951 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { 3952 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3953 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3954 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3955 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3956 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3957 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3958 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3959 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3960 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3961 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3962 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3963 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3964 {0x0064, CMN_PLL0_INTDIV_M0}, 3965 {0x0050, CMN_PLL0_INTDIV_M1}, 3966 {0x0064, CMN_PLL1_INTDIV_M0}, 3967 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3968 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3969 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3970 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3971 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3972 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3973 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3974 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3975 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3976 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3977 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3978 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3979 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3980 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3981 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3982 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3983 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3984 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3985 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3986 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3987 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3988 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3989 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3990 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3991 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3992 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3993 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3994 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3995 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3996 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3997 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3998 {0x007F, CMN_TXPUCAL_TUNE}, 3999 {0x007F, CMN_TXPDCAL_TUNE} 4000 }; 4001 4002 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = { 4003 .reg_pairs = qsgmii_100_int_ssc_cmn_regs, 4004 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs), 4005 }; 4006 4007 /* Single SGMII/QSGMII link configuration */ 4008 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = { 4009 {0x0000, PHY_PLL_CFG}, 4010 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} 4011 }; 4012 4013 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = { 4014 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4015 {0x0003, XCVR_DIAG_HSCLK_DIV}, 4016 {0x0013, XCVR_DIAG_PLLDRC_CTRL} 4017 }; 4018 4019 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = { 4020 .reg_pairs = sl_sgmii_link_cmn_regs, 4021 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs), 4022 }; 4023 4024 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = { 4025 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs, 4026 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs), 4027 }; 4028 4029 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */ 4030 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { 4031 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4032 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4033 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4034 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4035 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 4036 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4037 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4038 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 4039 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4040 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4041 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 4042 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4043 {0x0064, CMN_PLL0_INTDIV_M0}, 4044 {0x0050, CMN_PLL0_INTDIV_M1}, 4045 {0x0064, CMN_PLL1_INTDIV_M0}, 4046 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4047 {0x0002, CMN_PLL0_FRACDIVH_M1}, 4048 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4049 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4050 {0x0036, CMN_PLL0_HIGH_THR_M1}, 4051 {0x0044, CMN_PLL1_HIGH_THR_M0}, 4052 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4053 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 4054 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4055 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4056 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 4057 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4058 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4059 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 4060 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4061 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4062 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 4063 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 4064 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4065 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 4066 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 4067 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4068 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4069 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4070 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4071 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4072 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4073 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4074 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4075 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4076 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 4077 }; 4078 4079 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = { 4080 .reg_pairs = pcie_100_int_ssc_cmn_regs, 4081 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs), 4082 }; 4083 4084 /* Single link PCIe, 100 MHz Ref clk, internal SSC */ 4085 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { 4086 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4087 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4088 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4089 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4090 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 4091 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4092 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4093 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 4094 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4095 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4096 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 4097 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4098 {0x0064, CMN_PLL0_INTDIV_M0}, 4099 {0x0050, CMN_PLL0_INTDIV_M1}, 4100 {0x0050, CMN_PLL1_INTDIV_M0}, 4101 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4102 {0x0002, CMN_PLL0_FRACDIVH_M1}, 4103 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4104 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4105 {0x0036, CMN_PLL0_HIGH_THR_M1}, 4106 {0x0036, CMN_PLL1_HIGH_THR_M0}, 4107 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4108 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 4109 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4110 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4111 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 4112 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4113 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4114 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 4115 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4116 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4117 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 4118 {0x0058, CMN_PLL1_SS_CTRL3_M0}, 4119 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4120 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 4121 {0x0012, CMN_PLL1_SS_CTRL4_M0}, 4122 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4123 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4124 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4125 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4126 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4127 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4128 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4129 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4130 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4131 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 4132 }; 4133 4134 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = { 4135 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs, 4136 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs), 4137 }; 4138 4139 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */ 4140 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { 4141 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4142 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4143 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0} 4144 }; 4145 4146 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { 4147 {0x0019, RX_REE_TAP1_CLIP}, 4148 {0x0019, RX_REE_TAP2TON_CLIP}, 4149 {0x0001, RX_DIAG_ACYA} 4150 }; 4151 4152 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = { 4153 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs, 4154 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs), 4155 }; 4156 4157 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = { 4158 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs, 4159 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs), 4160 }; 4161 4162 static struct cdns_torrent_vals_entry link_cmn_vals_entries[] = { 4163 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_link_cmn_vals}, 4164 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &pcie_dp_link_cmn_vals}, 4165 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals}, 4166 4167 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL}, 4168 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals}, 4169 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals}, 4170 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals}, 4171 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals}, 4172 4173 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals}, 4174 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals}, 4175 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &usb_sgmii_link_cmn_vals}, 4176 4177 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals}, 4178 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals}, 4179 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &usb_sgmii_link_cmn_vals}, 4180 4181 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals}, 4182 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals}, 4183 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_link_cmn_vals}, 4184 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_link_cmn_vals}, 4185 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals}, 4186 4187 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_link_cmn_vals}, 4188 }; 4189 4190 static struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = { 4191 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_xcvr_diag_ln_vals}, 4192 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &dp_pcie_xcvr_diag_ln_vals}, 4193 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals}, 4194 4195 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL}, 4196 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals}, 4197 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals}, 4198 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals}, 4199 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals}, 4200 4201 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals}, 4202 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals}, 4203 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals}, 4204 4205 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals}, 4206 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals}, 4207 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals}, 4208 4209 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals}, 4210 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals}, 4211 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_xcvr_diag_ln_vals}, 4212 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_xcvr_diag_ln_vals}, 4213 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals}, 4214 4215 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_xcvr_diag_ln_vals}, 4216 }; 4217 4218 static struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = { 4219 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &usb_phy_pcs_cmn_vals}, 4220 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_phy_pcs_cmn_vals}, 4221 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_phy_pcs_cmn_vals}, 4222 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_phy_pcs_cmn_vals}, 4223 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_phy_pcs_cmn_vals}, 4224 }; 4225 4226 static struct cdns_torrent_vals_entry cmn_vals_entries[] = { 4227 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals}, 4228 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals}, 4229 4230 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals}, 4231 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals}, 4232 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals}, 4233 4234 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 4235 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 4236 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals}, 4237 4238 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 4239 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 4240 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 4241 4242 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 4243 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 4244 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 4245 4246 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 4247 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 4248 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 4249 4250 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 4251 4252 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals}, 4253 4254 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals}, 4255 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 4256 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals}, 4257 4258 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals}, 4259 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 4260 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 4261 4262 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals}, 4263 4264 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals}, 4265 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 4266 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals}, 4267 4268 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals}, 4269 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 4270 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 4271 4272 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 4273 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 4274 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 4275 4276 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals}, 4277 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals}, 4278 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals}, 4279 4280 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 4281 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 4282 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 4283 4284 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 4285 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 4286 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 4287 4288 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals}, 4289 4290 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals}, 4291 }; 4292 4293 static struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = { 4294 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals}, 4295 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals}, 4296 4297 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals}, 4298 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 4299 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 4300 4301 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 4302 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 4303 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL}, 4304 4305 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL}, 4306 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL}, 4307 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL}, 4308 4309 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL}, 4310 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL}, 4311 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL}, 4312 4313 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL}, 4314 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL}, 4315 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL}, 4316 4317 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 4318 4319 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 4320 4321 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 4322 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 4323 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 4324 4325 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 4326 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 4327 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 4328 4329 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 4330 4331 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 4332 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 4333 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 4334 4335 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 4336 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 4337 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 4338 4339 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4340 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4341 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4342 4343 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4344 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4345 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4346 4347 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4348 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4349 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4350 4351 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4352 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4353 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4354 4355 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4356 4357 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals}, 4358 }; 4359 4360 static struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = { 4361 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals}, 4362 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals}, 4363 4364 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals}, 4365 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals}, 4366 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals}, 4367 4368 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4369 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4370 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4371 4372 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4373 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4374 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4375 4376 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4377 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4378 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4379 4380 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4381 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4382 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4383 4384 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 4385 4386 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 4387 4388 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 4389 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 4390 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 4391 4392 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 4393 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 4394 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 4395 4396 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 4397 4398 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 4399 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 4400 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 4401 4402 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 4403 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 4404 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 4405 4406 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 4407 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4408 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4409 4410 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 4411 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4412 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4413 4414 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 4415 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4416 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4417 4418 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 4419 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4420 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 4421 4422 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 4423 4424 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals}, 4425 }; 4426 4427 static const struct cdns_torrent_data cdns_map_torrent = { 4428 .block_offset_shift = 0x2, 4429 .reg_offset_shift = 0x2, 4430 .link_cmn_vals_tbl = { 4431 .entries = link_cmn_vals_entries, 4432 .num_entries = ARRAY_SIZE(link_cmn_vals_entries), 4433 }, 4434 .xcvr_diag_vals_tbl = { 4435 .entries = xcvr_diag_vals_entries, 4436 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries), 4437 }, 4438 .pcs_cmn_vals_tbl = { 4439 .entries = pcs_cmn_vals_entries, 4440 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries), 4441 }, 4442 .cmn_vals_tbl = { 4443 .entries = cmn_vals_entries, 4444 .num_entries = ARRAY_SIZE(cmn_vals_entries), 4445 }, 4446 .tx_ln_vals_tbl = { 4447 .entries = cdns_tx_ln_vals_entries, 4448 .num_entries = ARRAY_SIZE(cdns_tx_ln_vals_entries), 4449 }, 4450 .rx_ln_vals_tbl = { 4451 .entries = cdns_rx_ln_vals_entries, 4452 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries), 4453 }, 4454 }; 4455 4456 static struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = { 4457 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &ti_usxgmii_phy_pma_cmn_vals}, 4458 }; 4459 4460 static struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = { 4461 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals}, 4462 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals}, 4463 4464 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals}, 4465 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 4466 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 4467 4468 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 4469 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 4470 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL}, 4471 4472 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL}, 4473 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL}, 4474 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL}, 4475 4476 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL}, 4477 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL}, 4478 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL}, 4479 4480 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL}, 4481 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL}, 4482 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL}, 4483 4484 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 4485 4486 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 4487 4488 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 4489 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 4490 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 4491 4492 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 4493 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 4494 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 4495 4496 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 4497 4498 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 4499 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 4500 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 4501 4502 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 4503 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 4504 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 4505 4506 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4507 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4508 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4509 4510 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4511 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4512 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4513 4514 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4515 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4516 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4517 4518 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4519 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4520 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 4521 4522 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 4523 4524 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals}, 4525 }; 4526 4527 static const struct cdns_torrent_data ti_j721e_map_torrent = { 4528 .block_offset_shift = 0x0, 4529 .reg_offset_shift = 0x1, 4530 .link_cmn_vals_tbl = { 4531 .entries = link_cmn_vals_entries, 4532 .num_entries = ARRAY_SIZE(link_cmn_vals_entries), 4533 }, 4534 .xcvr_diag_vals_tbl = { 4535 .entries = xcvr_diag_vals_entries, 4536 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries), 4537 }, 4538 .pcs_cmn_vals_tbl = { 4539 .entries = pcs_cmn_vals_entries, 4540 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries), 4541 }, 4542 .phy_pma_cmn_vals_tbl = { 4543 .entries = j721e_phy_pma_cmn_vals_entries, 4544 .num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries), 4545 }, 4546 .cmn_vals_tbl = { 4547 .entries = cmn_vals_entries, 4548 .num_entries = ARRAY_SIZE(cmn_vals_entries), 4549 }, 4550 .tx_ln_vals_tbl = { 4551 .entries = ti_tx_ln_vals_entries, 4552 .num_entries = ARRAY_SIZE(ti_tx_ln_vals_entries), 4553 }, 4554 .rx_ln_vals_tbl = { 4555 .entries = cdns_rx_ln_vals_entries, 4556 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries), 4557 }, 4558 }; 4559 4560 static const struct of_device_id cdns_torrent_phy_of_match[] = { 4561 { 4562 .compatible = "cdns,torrent-phy", 4563 .data = &cdns_map_torrent, 4564 }, 4565 { 4566 .compatible = "ti,j721e-serdes-10g", 4567 .data = &ti_j721e_map_torrent, 4568 }, 4569 {} 4570 }; 4571 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); 4572 4573 static struct platform_driver cdns_torrent_phy_driver = { 4574 .probe = cdns_torrent_phy_probe, 4575 .remove_new = cdns_torrent_phy_remove, 4576 .driver = { 4577 .name = "cdns-torrent-phy", 4578 .of_match_table = cdns_torrent_phy_of_match, 4579 } 4580 }; 4581 module_platform_driver(cdns_torrent_phy_driver); 4582 4583 MODULE_AUTHOR("Cadence Design Systems, Inc."); 4584 MODULE_DESCRIPTION("Cadence Torrent PHY driver"); 4585 MODULE_LICENSE("GPL v2"); 4586