17a343c8bSMaxime Ripard // SPDX-License-Identifier: GPL-2.0+
27a343c8bSMaxime Ripard /*
37a343c8bSMaxime Ripard * Copyright: 2017-2018 Cadence Design Systems, Inc.
47a343c8bSMaxime Ripard */
57a343c8bSMaxime Ripard
6efcd5f52SRahul T R #include <linux/bitfield.h>
77a343c8bSMaxime Ripard #include <linux/bitops.h>
87a343c8bSMaxime Ripard #include <linux/clk.h>
97a343c8bSMaxime Ripard #include <linux/io.h>
10f6723b84SRahul T R #include <linux/iopoll.h>
117a343c8bSMaxime Ripard #include <linux/module.h>
12*7559e757SRob Herring #include <linux/of.h>
137a343c8bSMaxime Ripard #include <linux/platform_device.h>
147a343c8bSMaxime Ripard #include <linux/reset.h>
157a343c8bSMaxime Ripard
167a343c8bSMaxime Ripard #include <linux/phy/phy.h>
177a343c8bSMaxime Ripard #include <linux/phy/phy-mipi-dphy.h>
187a343c8bSMaxime Ripard
197a343c8bSMaxime Ripard #define REG_WAKEUP_TIME_NS 800
207a343c8bSMaxime Ripard #define DPHY_PLL_RATE_HZ 108000000
21f6723b84SRahul T R #define POLL_TIMEOUT_US 1000
227a343c8bSMaxime Ripard
237a343c8bSMaxime Ripard /* DPHY registers */
247a343c8bSMaxime Ripard #define DPHY_PMA_CMN(reg) (reg)
257a343c8bSMaxime Ripard #define DPHY_PMA_LCLK(reg) (0x100 + (reg))
267a343c8bSMaxime Ripard #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg))
277a343c8bSMaxime Ripard #define DPHY_PMA_RCLK(reg) (0x600 + (reg))
287a343c8bSMaxime Ripard #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg))
297a343c8bSMaxime Ripard #define DPHY_PCS(reg) (0xb00 + (reg))
307a343c8bSMaxime Ripard
317a343c8bSMaxime Ripard #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
327a343c8bSMaxime Ripard #define DPHY_CMN_SSM_EN BIT(0)
337a343c8bSMaxime Ripard #define DPHY_CMN_TX_MODE_EN BIT(9)
347a343c8bSMaxime Ripard
357a343c8bSMaxime Ripard #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40)
367a343c8bSMaxime Ripard #define DPHY_CMN_PWM_DIV(x) ((x) << 20)
377a343c8bSMaxime Ripard #define DPHY_CMN_PWM_LOW(x) ((x) << 10)
387a343c8bSMaxime Ripard #define DPHY_CMN_PWM_HIGH(x) (x)
397a343c8bSMaxime Ripard
407a343c8bSMaxime Ripard #define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c)
417a343c8bSMaxime Ripard #define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22))
427a343c8bSMaxime Ripard #define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21))
437a343c8bSMaxime Ripard
447a343c8bSMaxime Ripard #define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50)
457a343c8bSMaxime Ripard #define DPHY_CMN_IPDIV_FROM_REG BIT(0)
467a343c8bSMaxime Ripard #define DPHY_CMN_IPDIV(x) ((x) << 1)
477a343c8bSMaxime Ripard #define DPHY_CMN_OPDIV_FROM_REG BIT(6)
487a343c8bSMaxime Ripard #define DPHY_CMN_OPDIV(x) ((x) << 7)
497a343c8bSMaxime Ripard
50efcd5f52SRahul T R #define DPHY_BAND_CFG DPHY_PCS(0x0)
51efcd5f52SRahul T R #define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0)
52efcd5f52SRahul T R #define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5)
53efcd5f52SRahul T R
547a343c8bSMaxime Ripard #define DPHY_PSM_CFG DPHY_PCS(0x4)
557a343c8bSMaxime Ripard #define DPHY_PSM_CFG_FROM_REG BIT(0)
567a343c8bSMaxime Ripard #define DPHY_PSM_CLK_DIV(x) ((x) << 1)
577a343c8bSMaxime Ripard
587a343c8bSMaxime Ripard #define DSI_HBP_FRAME_OVERHEAD 12
597a343c8bSMaxime Ripard #define DSI_HSA_FRAME_OVERHEAD 14
607a343c8bSMaxime Ripard #define DSI_HFP_FRAME_OVERHEAD 6
617a343c8bSMaxime Ripard #define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
627a343c8bSMaxime Ripard #define DSI_BLANKING_FRAME_OVERHEAD 6
637a343c8bSMaxime Ripard #define DSI_NULL_FRAME_OVERHEAD 6
647a343c8bSMaxime Ripard #define DSI_EOT_PKT_SIZE 4
657a343c8bSMaxime Ripard
66f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_PLL_CTRL 0xF04
67f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_STATUS 0xF08
68f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_RST_CTRL 0xF0C
69f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_PSM_FREQ 0xF10
70f6723b84SRahul T R
71f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_IPDIV GENMASK(4, 0)
72f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_OPDIV GENMASK(13, 8)
73f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_FBDIV GENMASK(25, 16)
74f6723b84SRahul T R #define DPHY_TX_J721E_WIZ_LANE_RSTB BIT(31)
75f6723b84SRahul T R #define DPHY_TX_WIZ_PLL_LOCK BIT(31)
76f6723b84SRahul T R #define DPHY_TX_WIZ_O_CMN_READY BIT(31)
77f6723b84SRahul T R
787a343c8bSMaxime Ripard struct cdns_dphy_cfg {
797a343c8bSMaxime Ripard u8 pll_ipdiv;
807a343c8bSMaxime Ripard u8 pll_opdiv;
817a343c8bSMaxime Ripard u16 pll_fbdiv;
827a343c8bSMaxime Ripard unsigned int nlanes;
837a343c8bSMaxime Ripard };
847a343c8bSMaxime Ripard
857a343c8bSMaxime Ripard enum cdns_dphy_clk_lane_cfg {
867a343c8bSMaxime Ripard DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0,
877a343c8bSMaxime Ripard DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1,
887a343c8bSMaxime Ripard DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2,
897a343c8bSMaxime Ripard DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3,
907a343c8bSMaxime Ripard };
917a343c8bSMaxime Ripard
927a343c8bSMaxime Ripard struct cdns_dphy;
937a343c8bSMaxime Ripard struct cdns_dphy_ops {
947a343c8bSMaxime Ripard int (*probe)(struct cdns_dphy *dphy);
957a343c8bSMaxime Ripard void (*remove)(struct cdns_dphy *dphy);
967a343c8bSMaxime Ripard void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
977a343c8bSMaxime Ripard void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
987a343c8bSMaxime Ripard enum cdns_dphy_clk_lane_cfg cfg);
997a343c8bSMaxime Ripard void (*set_pll_cfg)(struct cdns_dphy *dphy,
1007a343c8bSMaxime Ripard const struct cdns_dphy_cfg *cfg);
1017a343c8bSMaxime Ripard unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
1027a343c8bSMaxime Ripard };
1037a343c8bSMaxime Ripard
1047a343c8bSMaxime Ripard struct cdns_dphy {
1057a343c8bSMaxime Ripard struct cdns_dphy_cfg cfg;
1067a343c8bSMaxime Ripard void __iomem *regs;
1077a343c8bSMaxime Ripard struct clk *psm_clk;
1087a343c8bSMaxime Ripard struct clk *pll_ref_clk;
1097a343c8bSMaxime Ripard const struct cdns_dphy_ops *ops;
1107a343c8bSMaxime Ripard struct phy *phy;
1117a343c8bSMaxime Ripard };
1127a343c8bSMaxime Ripard
113efcd5f52SRahul T R /* Order of bands is important since the index is the band number. */
114efcd5f52SRahul T R static const unsigned int tx_bands[] = {
115efcd5f52SRahul T R 80, 100, 120, 160, 200, 240, 320, 390, 450, 510, 560, 640, 690, 770,
116efcd5f52SRahul T R 870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500
117efcd5f52SRahul T R };
118efcd5f52SRahul T R
cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy * dphy,struct cdns_dphy_cfg * cfg,struct phy_configure_opts_mipi_dphy * opts,unsigned int * dsi_hfp_ext)1197a343c8bSMaxime Ripard static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
1207a343c8bSMaxime Ripard struct cdns_dphy_cfg *cfg,
1217a343c8bSMaxime Ripard struct phy_configure_opts_mipi_dphy *opts,
1227a343c8bSMaxime Ripard unsigned int *dsi_hfp_ext)
1237a343c8bSMaxime Ripard {
1247a343c8bSMaxime Ripard unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);
1257a343c8bSMaxime Ripard u64 dlane_bps;
1267a343c8bSMaxime Ripard
1277a343c8bSMaxime Ripard memset(cfg, 0, sizeof(*cfg));
1287a343c8bSMaxime Ripard
1297a343c8bSMaxime Ripard if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)
1307a343c8bSMaxime Ripard return -EINVAL;
1317a343c8bSMaxime Ripard else if (pll_ref_hz < 19200000)
1327a343c8bSMaxime Ripard cfg->pll_ipdiv = 1;
1337a343c8bSMaxime Ripard else if (pll_ref_hz < 38400000)
1347a343c8bSMaxime Ripard cfg->pll_ipdiv = 2;
1357a343c8bSMaxime Ripard else if (pll_ref_hz < 76800000)
1367a343c8bSMaxime Ripard cfg->pll_ipdiv = 4;
1377a343c8bSMaxime Ripard else
1387a343c8bSMaxime Ripard cfg->pll_ipdiv = 8;
1397a343c8bSMaxime Ripard
1407a343c8bSMaxime Ripard dlane_bps = opts->hs_clk_rate;
1417a343c8bSMaxime Ripard
1427a343c8bSMaxime Ripard if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL)
1437a343c8bSMaxime Ripard return -EINVAL;
1447a343c8bSMaxime Ripard else if (dlane_bps >= 1250000000)
1457a343c8bSMaxime Ripard cfg->pll_opdiv = 1;
1467a343c8bSMaxime Ripard else if (dlane_bps >= 630000000)
1477a343c8bSMaxime Ripard cfg->pll_opdiv = 2;
1487a343c8bSMaxime Ripard else if (dlane_bps >= 320000000)
1497a343c8bSMaxime Ripard cfg->pll_opdiv = 4;
1507a343c8bSMaxime Ripard else if (dlane_bps >= 160000000)
1517a343c8bSMaxime Ripard cfg->pll_opdiv = 8;
1527a343c8bSMaxime Ripard
1537a343c8bSMaxime Ripard cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv *
1547a343c8bSMaxime Ripard cfg->pll_ipdiv,
1557a343c8bSMaxime Ripard pll_ref_hz);
1567a343c8bSMaxime Ripard
1577a343c8bSMaxime Ripard return 0;
1587a343c8bSMaxime Ripard }
1597a343c8bSMaxime Ripard
cdns_dphy_setup_psm(struct cdns_dphy * dphy)1607a343c8bSMaxime Ripard static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)
1617a343c8bSMaxime Ripard {
1627a343c8bSMaxime Ripard unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk);
1637a343c8bSMaxime Ripard unsigned long psm_div;
1647a343c8bSMaxime Ripard
1657a343c8bSMaxime Ripard if (!psm_clk_hz || psm_clk_hz > 100000000)
1667a343c8bSMaxime Ripard return -EINVAL;
1677a343c8bSMaxime Ripard
1687a343c8bSMaxime Ripard psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000);
1697a343c8bSMaxime Ripard if (dphy->ops->set_psm_div)
1707a343c8bSMaxime Ripard dphy->ops->set_psm_div(dphy, psm_div);
1717a343c8bSMaxime Ripard
1727a343c8bSMaxime Ripard return 0;
1737a343c8bSMaxime Ripard }
1747a343c8bSMaxime Ripard
cdns_dphy_set_clk_lane_cfg(struct cdns_dphy * dphy,enum cdns_dphy_clk_lane_cfg cfg)1757a343c8bSMaxime Ripard static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy,
1767a343c8bSMaxime Ripard enum cdns_dphy_clk_lane_cfg cfg)
1777a343c8bSMaxime Ripard {
1787a343c8bSMaxime Ripard if (dphy->ops->set_clk_lane_cfg)
1797a343c8bSMaxime Ripard dphy->ops->set_clk_lane_cfg(dphy, cfg);
1807a343c8bSMaxime Ripard }
1817a343c8bSMaxime Ripard
cdns_dphy_set_pll_cfg(struct cdns_dphy * dphy,const struct cdns_dphy_cfg * cfg)1827a343c8bSMaxime Ripard static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy,
1837a343c8bSMaxime Ripard const struct cdns_dphy_cfg *cfg)
1847a343c8bSMaxime Ripard {
1857a343c8bSMaxime Ripard if (dphy->ops->set_pll_cfg)
1867a343c8bSMaxime Ripard dphy->ops->set_pll_cfg(dphy, cfg);
1877a343c8bSMaxime Ripard }
1887a343c8bSMaxime Ripard
cdns_dphy_get_wakeup_time_ns(struct cdns_dphy * dphy)1897a343c8bSMaxime Ripard static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy)
1907a343c8bSMaxime Ripard {
1917a343c8bSMaxime Ripard return dphy->ops->get_wakeup_time_ns(dphy);
1927a343c8bSMaxime Ripard }
1937a343c8bSMaxime Ripard
cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy * dphy)1947a343c8bSMaxime Ripard static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dphy)
1957a343c8bSMaxime Ripard {
1967a343c8bSMaxime Ripard /* Default wakeup time is 800 ns (in a simulated environment). */
1977a343c8bSMaxime Ripard return 800;
1987a343c8bSMaxime Ripard }
1997a343c8bSMaxime Ripard
cdns_dphy_ref_set_pll_cfg(struct cdns_dphy * dphy,const struct cdns_dphy_cfg * cfg)2007a343c8bSMaxime Ripard static void cdns_dphy_ref_set_pll_cfg(struct cdns_dphy *dphy,
2017a343c8bSMaxime Ripard const struct cdns_dphy_cfg *cfg)
2027a343c8bSMaxime Ripard {
2037a343c8bSMaxime Ripard u32 fbdiv_low, fbdiv_high;
2047a343c8bSMaxime Ripard
2057a343c8bSMaxime Ripard fbdiv_low = (cfg->pll_fbdiv / 4) - 2;
2067a343c8bSMaxime Ripard fbdiv_high = cfg->pll_fbdiv - fbdiv_low - 2;
2077a343c8bSMaxime Ripard
2087a343c8bSMaxime Ripard writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG |
2097a343c8bSMaxime Ripard DPHY_CMN_IPDIV(cfg->pll_ipdiv) |
2107a343c8bSMaxime Ripard DPHY_CMN_OPDIV(cfg->pll_opdiv),
2117a343c8bSMaxime Ripard dphy->regs + DPHY_CMN_OPIPDIV);
2127a343c8bSMaxime Ripard writel(DPHY_CMN_FBDIV_FROM_REG |
2137a343c8bSMaxime Ripard DPHY_CMN_FBDIV_VAL(fbdiv_low, fbdiv_high),
2147a343c8bSMaxime Ripard dphy->regs + DPHY_CMN_FBDIV);
2157a343c8bSMaxime Ripard writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
2167a343c8bSMaxime Ripard DPHY_CMN_PWM_DIV(0x8),
2177a343c8bSMaxime Ripard dphy->regs + DPHY_CMN_PWM);
2187a343c8bSMaxime Ripard }
2197a343c8bSMaxime Ripard
cdns_dphy_ref_set_psm_div(struct cdns_dphy * dphy,u8 div)2207a343c8bSMaxime Ripard static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div)
2217a343c8bSMaxime Ripard {
2227a343c8bSMaxime Ripard writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div),
2237a343c8bSMaxime Ripard dphy->regs + DPHY_PSM_CFG);
2247a343c8bSMaxime Ripard }
2257a343c8bSMaxime Ripard
cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy * dphy)226f6723b84SRahul T R static unsigned long cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy *dphy)
227f6723b84SRahul T R {
228f6723b84SRahul T R /* Minimum wakeup time as per MIPI D-PHY spec v1.2 */
229f6723b84SRahul T R return 1000000;
230f6723b84SRahul T R }
231f6723b84SRahul T R
cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy * dphy,const struct cdns_dphy_cfg * cfg)232f6723b84SRahul T R static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy *dphy,
233f6723b84SRahul T R const struct cdns_dphy_cfg *cfg)
234f6723b84SRahul T R {
235f6723b84SRahul T R u32 status;
236f6723b84SRahul T R
237f6723b84SRahul T R /*
238f6723b84SRahul T R * set the PWM and PLL Byteclk divider settings to recommended values
239f6723b84SRahul T R * which is same as that of in ref ops
240f6723b84SRahul T R */
241f6723b84SRahul T R writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
242f6723b84SRahul T R DPHY_CMN_PWM_DIV(0x8),
243f6723b84SRahul T R dphy->regs + DPHY_CMN_PWM);
244f6723b84SRahul T R
245f6723b84SRahul T R writel((FIELD_PREP(DPHY_TX_J721E_WIZ_IPDIV, cfg->pll_ipdiv) |
246f6723b84SRahul T R FIELD_PREP(DPHY_TX_J721E_WIZ_OPDIV, cfg->pll_opdiv) |
247f6723b84SRahul T R FIELD_PREP(DPHY_TX_J721E_WIZ_FBDIV, cfg->pll_fbdiv)),
248f6723b84SRahul T R dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL);
249f6723b84SRahul T R
250f6723b84SRahul T R writel(DPHY_TX_J721E_WIZ_LANE_RSTB,
251f6723b84SRahul T R dphy->regs + DPHY_TX_J721E_WIZ_RST_CTRL);
252f6723b84SRahul T R
253f6723b84SRahul T R readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status,
254f6723b84SRahul T R (status & DPHY_TX_WIZ_PLL_LOCK), 0, POLL_TIMEOUT_US);
255f6723b84SRahul T R
256f6723b84SRahul T R readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status,
257f6723b84SRahul T R (status & DPHY_TX_WIZ_O_CMN_READY), 0,
258f6723b84SRahul T R POLL_TIMEOUT_US);
259f6723b84SRahul T R }
260f6723b84SRahul T R
cdns_dphy_j721e_set_psm_div(struct cdns_dphy * dphy,u8 div)261f6723b84SRahul T R static void cdns_dphy_j721e_set_psm_div(struct cdns_dphy *dphy, u8 div)
262f6723b84SRahul T R {
263f6723b84SRahul T R writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ);
264f6723b84SRahul T R }
265f6723b84SRahul T R
2667a343c8bSMaxime Ripard /*
2677a343c8bSMaxime Ripard * This is the reference implementation of DPHY hooks. Specific integration of
2687a343c8bSMaxime Ripard * this IP may have to re-implement some of them depending on how they decided
2697a343c8bSMaxime Ripard * to wire things in the SoC.
2707a343c8bSMaxime Ripard */
2717a343c8bSMaxime Ripard static const struct cdns_dphy_ops ref_dphy_ops = {
2727a343c8bSMaxime Ripard .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns,
2737a343c8bSMaxime Ripard .set_pll_cfg = cdns_dphy_ref_set_pll_cfg,
2747a343c8bSMaxime Ripard .set_psm_div = cdns_dphy_ref_set_psm_div,
2757a343c8bSMaxime Ripard };
2767a343c8bSMaxime Ripard
277f6723b84SRahul T R static const struct cdns_dphy_ops j721e_dphy_ops = {
278f6723b84SRahul T R .get_wakeup_time_ns = cdns_dphy_j721e_get_wakeup_time_ns,
279f6723b84SRahul T R .set_pll_cfg = cdns_dphy_j721e_set_pll_cfg,
280f6723b84SRahul T R .set_psm_div = cdns_dphy_j721e_set_psm_div,
281f6723b84SRahul T R };
282f6723b84SRahul T R
cdns_dphy_config_from_opts(struct phy * phy,struct phy_configure_opts_mipi_dphy * opts,struct cdns_dphy_cfg * cfg)2837a343c8bSMaxime Ripard static int cdns_dphy_config_from_opts(struct phy *phy,
2847a343c8bSMaxime Ripard struct phy_configure_opts_mipi_dphy *opts,
2857a343c8bSMaxime Ripard struct cdns_dphy_cfg *cfg)
2867a343c8bSMaxime Ripard {
2877a343c8bSMaxime Ripard struct cdns_dphy *dphy = phy_get_drvdata(phy);
2887a343c8bSMaxime Ripard unsigned int dsi_hfp_ext = 0;
2897a343c8bSMaxime Ripard int ret;
2907a343c8bSMaxime Ripard
2917a343c8bSMaxime Ripard ret = phy_mipi_dphy_config_validate(opts);
2927a343c8bSMaxime Ripard if (ret)
2937a343c8bSMaxime Ripard return ret;
2947a343c8bSMaxime Ripard
2957a343c8bSMaxime Ripard ret = cdns_dsi_get_dphy_pll_cfg(dphy, cfg,
2967a343c8bSMaxime Ripard opts, &dsi_hfp_ext);
2977a343c8bSMaxime Ripard if (ret)
2987a343c8bSMaxime Ripard return ret;
2997a343c8bSMaxime Ripard
3007a343c8bSMaxime Ripard opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000;
3017a343c8bSMaxime Ripard
3027a343c8bSMaxime Ripard return 0;
3037a343c8bSMaxime Ripard }
3047a343c8bSMaxime Ripard
cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate)305efcd5f52SRahul T R static int cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate)
306efcd5f52SRahul T R {
307efcd5f52SRahul T R unsigned int rate;
308efcd5f52SRahul T R int i;
309efcd5f52SRahul T R
310efcd5f52SRahul T R rate = hs_clk_rate / 1000000UL;
311efcd5f52SRahul T R
312efcd5f52SRahul T R if (rate < tx_bands[0])
313efcd5f52SRahul T R return -EOPNOTSUPP;
314efcd5f52SRahul T R
315efcd5f52SRahul T R for (i = 0; i < ARRAY_SIZE(tx_bands) - 1; i++) {
316efcd5f52SRahul T R if (rate >= tx_bands[i] && rate < tx_bands[i + 1])
317efcd5f52SRahul T R return i;
318efcd5f52SRahul T R }
319efcd5f52SRahul T R
320efcd5f52SRahul T R return -EOPNOTSUPP;
321efcd5f52SRahul T R }
322efcd5f52SRahul T R
cdns_dphy_validate(struct phy * phy,enum phy_mode mode,int submode,union phy_configure_opts * opts)3237a343c8bSMaxime Ripard static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
3247a343c8bSMaxime Ripard union phy_configure_opts *opts)
3257a343c8bSMaxime Ripard {
3267a343c8bSMaxime Ripard struct cdns_dphy_cfg cfg = { 0 };
3277a343c8bSMaxime Ripard
3287a343c8bSMaxime Ripard if (mode != PHY_MODE_MIPI_DPHY)
3297a343c8bSMaxime Ripard return -EINVAL;
3307a343c8bSMaxime Ripard
3317a343c8bSMaxime Ripard return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
3327a343c8bSMaxime Ripard }
3337a343c8bSMaxime Ripard
cdns_dphy_configure(struct phy * phy,union phy_configure_opts * opts)3347a343c8bSMaxime Ripard static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
3357a343c8bSMaxime Ripard {
3367a343c8bSMaxime Ripard struct cdns_dphy *dphy = phy_get_drvdata(phy);
3377a343c8bSMaxime Ripard struct cdns_dphy_cfg cfg = { 0 };
338efcd5f52SRahul T R int ret, band_ctrl;
339efcd5f52SRahul T R unsigned int reg;
3407a343c8bSMaxime Ripard
3417a343c8bSMaxime Ripard ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
3427a343c8bSMaxime Ripard if (ret)
3437a343c8bSMaxime Ripard return ret;
3447a343c8bSMaxime Ripard
3457a343c8bSMaxime Ripard /*
3467a343c8bSMaxime Ripard * Configure the internal PSM clk divider so that the DPHY has a
3477a343c8bSMaxime Ripard * 1MHz clk (or something close).
3487a343c8bSMaxime Ripard */
3497a343c8bSMaxime Ripard ret = cdns_dphy_setup_psm(dphy);
3507a343c8bSMaxime Ripard if (ret)
3517a343c8bSMaxime Ripard return ret;
3527a343c8bSMaxime Ripard
3537a343c8bSMaxime Ripard /*
3547a343c8bSMaxime Ripard * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes
3557a343c8bSMaxime Ripard * and 8 data lanes, each clk lane can be attache different set of
3567a343c8bSMaxime Ripard * data lanes. The 2 groups are named 'left' and 'right', so here we
3577a343c8bSMaxime Ripard * just say that we want the 'left' clk lane to drive the 'left' data
3587a343c8bSMaxime Ripard * lanes.
3597a343c8bSMaxime Ripard */
3607a343c8bSMaxime Ripard cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT);
3617a343c8bSMaxime Ripard
3627a343c8bSMaxime Ripard /*
3637a343c8bSMaxime Ripard * Configure the DPHY PLL that will be used to generate the TX byte
3647a343c8bSMaxime Ripard * clk.
3657a343c8bSMaxime Ripard */
3667a343c8bSMaxime Ripard cdns_dphy_set_pll_cfg(dphy, &cfg);
3677a343c8bSMaxime Ripard
368efcd5f52SRahul T R band_ctrl = cdns_dphy_tx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);
369efcd5f52SRahul T R if (band_ctrl < 0)
370efcd5f52SRahul T R return band_ctrl;
371efcd5f52SRahul T R
372efcd5f52SRahul T R reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) |
373efcd5f52SRahul T R FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl);
374efcd5f52SRahul T R writel(reg, dphy->regs + DPHY_BAND_CFG);
375efcd5f52SRahul T R
3767a343c8bSMaxime Ripard return 0;
3777a343c8bSMaxime Ripard }
3787a343c8bSMaxime Ripard
cdns_dphy_power_on(struct phy * phy)3797a343c8bSMaxime Ripard static int cdns_dphy_power_on(struct phy *phy)
3807a343c8bSMaxime Ripard {
3817a343c8bSMaxime Ripard struct cdns_dphy *dphy = phy_get_drvdata(phy);
3827a343c8bSMaxime Ripard
3837a343c8bSMaxime Ripard clk_prepare_enable(dphy->psm_clk);
3847a343c8bSMaxime Ripard clk_prepare_enable(dphy->pll_ref_clk);
3857a343c8bSMaxime Ripard
3867a343c8bSMaxime Ripard /* Start TX state machine. */
3877a343c8bSMaxime Ripard writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
3887a343c8bSMaxime Ripard dphy->regs + DPHY_CMN_SSM);
3897a343c8bSMaxime Ripard
3907a343c8bSMaxime Ripard return 0;
3917a343c8bSMaxime Ripard }
3927a343c8bSMaxime Ripard
cdns_dphy_power_off(struct phy * phy)3937a343c8bSMaxime Ripard static int cdns_dphy_power_off(struct phy *phy)
3947a343c8bSMaxime Ripard {
3957a343c8bSMaxime Ripard struct cdns_dphy *dphy = phy_get_drvdata(phy);
3967a343c8bSMaxime Ripard
3977a343c8bSMaxime Ripard clk_disable_unprepare(dphy->pll_ref_clk);
3987a343c8bSMaxime Ripard clk_disable_unprepare(dphy->psm_clk);
3997a343c8bSMaxime Ripard
4007a343c8bSMaxime Ripard return 0;
4017a343c8bSMaxime Ripard }
4027a343c8bSMaxime Ripard
4037a343c8bSMaxime Ripard static const struct phy_ops cdns_dphy_ops = {
4047a343c8bSMaxime Ripard .configure = cdns_dphy_configure,
4057a343c8bSMaxime Ripard .validate = cdns_dphy_validate,
4067a343c8bSMaxime Ripard .power_on = cdns_dphy_power_on,
4077a343c8bSMaxime Ripard .power_off = cdns_dphy_power_off,
4087a343c8bSMaxime Ripard };
4097a343c8bSMaxime Ripard
cdns_dphy_probe(struct platform_device * pdev)4107a343c8bSMaxime Ripard static int cdns_dphy_probe(struct platform_device *pdev)
4117a343c8bSMaxime Ripard {
4127a343c8bSMaxime Ripard struct phy_provider *phy_provider;
4137a343c8bSMaxime Ripard struct cdns_dphy *dphy;
4147a343c8bSMaxime Ripard int ret;
4157a343c8bSMaxime Ripard
4167a343c8bSMaxime Ripard dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
4177a343c8bSMaxime Ripard if (!dphy)
4187a343c8bSMaxime Ripard return -ENOMEM;
4197a343c8bSMaxime Ripard dev_set_drvdata(&pdev->dev, dphy);
4207a343c8bSMaxime Ripard
4217a343c8bSMaxime Ripard dphy->ops = of_device_get_match_data(&pdev->dev);
4227a343c8bSMaxime Ripard if (!dphy->ops)
4237a343c8bSMaxime Ripard return -EINVAL;
4247a343c8bSMaxime Ripard
425fa629094SChunfeng Yun dphy->regs = devm_platform_ioremap_resource(pdev, 0);
4267a343c8bSMaxime Ripard if (IS_ERR(dphy->regs))
4277a343c8bSMaxime Ripard return PTR_ERR(dphy->regs);
4287a343c8bSMaxime Ripard
4297a343c8bSMaxime Ripard dphy->psm_clk = devm_clk_get(&pdev->dev, "psm");
4307a343c8bSMaxime Ripard if (IS_ERR(dphy->psm_clk))
4317a343c8bSMaxime Ripard return PTR_ERR(dphy->psm_clk);
4327a343c8bSMaxime Ripard
4337a343c8bSMaxime Ripard dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref");
4347a343c8bSMaxime Ripard if (IS_ERR(dphy->pll_ref_clk))
4357a343c8bSMaxime Ripard return PTR_ERR(dphy->pll_ref_clk);
4367a343c8bSMaxime Ripard
4377a343c8bSMaxime Ripard if (dphy->ops->probe) {
4387a343c8bSMaxime Ripard ret = dphy->ops->probe(dphy);
4397a343c8bSMaxime Ripard if (ret)
4407a343c8bSMaxime Ripard return ret;
4417a343c8bSMaxime Ripard }
4427a343c8bSMaxime Ripard
4437a343c8bSMaxime Ripard dphy->phy = devm_phy_create(&pdev->dev, NULL, &cdns_dphy_ops);
4447a343c8bSMaxime Ripard if (IS_ERR(dphy->phy)) {
4457a343c8bSMaxime Ripard dev_err(&pdev->dev, "failed to create PHY\n");
4467a343c8bSMaxime Ripard if (dphy->ops->remove)
4477a343c8bSMaxime Ripard dphy->ops->remove(dphy);
4487a343c8bSMaxime Ripard return PTR_ERR(dphy->phy);
4497a343c8bSMaxime Ripard }
4507a343c8bSMaxime Ripard
4517a343c8bSMaxime Ripard phy_set_drvdata(dphy->phy, dphy);
4527a343c8bSMaxime Ripard phy_provider = devm_of_phy_provider_register(&pdev->dev,
4537a343c8bSMaxime Ripard of_phy_simple_xlate);
4547a343c8bSMaxime Ripard
4557a343c8bSMaxime Ripard return PTR_ERR_OR_ZERO(phy_provider);
4567a343c8bSMaxime Ripard }
4577a343c8bSMaxime Ripard
cdns_dphy_remove(struct platform_device * pdev)4587b23fd5cSUwe Kleine-König static void cdns_dphy_remove(struct platform_device *pdev)
4597a343c8bSMaxime Ripard {
4607a343c8bSMaxime Ripard struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev);
4617a343c8bSMaxime Ripard
4627a343c8bSMaxime Ripard if (dphy->ops->remove)
4637a343c8bSMaxime Ripard dphy->ops->remove(dphy);
4647a343c8bSMaxime Ripard }
4657a343c8bSMaxime Ripard
4667a343c8bSMaxime Ripard static const struct of_device_id cdns_dphy_of_match[] = {
4677a343c8bSMaxime Ripard { .compatible = "cdns,dphy", .data = &ref_dphy_ops },
468f6723b84SRahul T R { .compatible = "ti,j721e-dphy", .data = &j721e_dphy_ops },
4697a343c8bSMaxime Ripard { /* sentinel */ },
4707a343c8bSMaxime Ripard };
4717a343c8bSMaxime Ripard MODULE_DEVICE_TABLE(of, cdns_dphy_of_match);
4727a343c8bSMaxime Ripard
4737a343c8bSMaxime Ripard static struct platform_driver cdns_dphy_platform_driver = {
4747a343c8bSMaxime Ripard .probe = cdns_dphy_probe,
4757b23fd5cSUwe Kleine-König .remove_new = cdns_dphy_remove,
4767a343c8bSMaxime Ripard .driver = {
4777a343c8bSMaxime Ripard .name = "cdns-mipi-dphy",
4787a343c8bSMaxime Ripard .of_match_table = cdns_dphy_of_match,
4797a343c8bSMaxime Ripard },
4807a343c8bSMaxime Ripard };
4817a343c8bSMaxime Ripard module_platform_driver(cdns_dphy_platform_driver);
4827a343c8bSMaxime Ripard
4837a343c8bSMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
4847a343c8bSMaxime Ripard MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver");
4857a343c8bSMaxime Ripard MODULE_LICENSE("GPL");
486