1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/phy/phy.h> 12 #include <linux/phy/phy-mipi-dphy.h> 13 #include <linux/platform_device.h> 14 #include <linux/sys_soc.h> 15 16 #define DPHY_PMA_CMN(reg) (reg) 17 #define DPHY_PCS(reg) (0xb00 + (reg)) 18 #define DPHY_ISO(reg) (0xc00 + (reg)) 19 #define DPHY_WRAP(reg) (0x1000 + (reg)) 20 21 #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) 22 #define DPHY_CMN_RX_MODE_EN BIT(10) 23 #define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) 24 #define DPHY_CMN_SSM_EN BIT(0) 25 26 #define DPHY_CMN_RX_BANDGAP_TIMER 0x14 27 28 #define DPHY_BAND_CFG DPHY_PCS(0x0) 29 #define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) 30 #define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) 31 32 #define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) 33 #define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa 34 35 #define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) 36 #define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa 37 38 #define DPHY_LANE DPHY_WRAP(0x0) 39 #define DPHY_LANE_RESET_CMN_EN BIT(23) 40 41 #define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) 42 #define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) 43 #define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) 44 #define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) 45 #define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) 46 47 #define DPHY_ISO_LANE_READY_BIT 0 48 #define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL 49 50 #define DPHY_LANES_MIN 1 51 #define DPHY_LANES_MAX 4 52 53 struct cdns_dphy_rx { 54 void __iomem *regs; 55 struct device *dev; 56 struct phy *phy; 57 }; 58 59 struct cdns_dphy_rx_band { 60 /* Rates are in Mbps. */ 61 unsigned int min_rate; 62 unsigned int max_rate; 63 }; 64 65 struct cdns_dphy_soc_data { 66 bool has_hw_cmn_rstb; 67 }; 68 69 /* Order of bands is important since the index is the band number. */ 70 static const struct cdns_dphy_rx_band bands[] = { 71 { 80, 100 }, { 100, 120 }, { 120, 160 }, { 160, 200 }, { 200, 240 }, 72 { 240, 280 }, { 280, 320 }, { 320, 360 }, { 360, 400 }, { 400, 480 }, 73 { 480, 560 }, { 560, 640 }, { 640, 720 }, { 720, 800 }, { 800, 880 }, 74 { 880, 1040 }, { 1040, 1200 }, { 1200, 1350 }, { 1350, 1500 }, 75 { 1500, 1750 }, { 1750, 2000 }, { 2000, 2250 }, { 2250, 2500 } 76 }; 77 78 static int cdns_dphy_rx_power_on(struct phy *phy) 79 { 80 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); 81 82 /* Start RX state machine. */ 83 writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | 84 FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, 85 DPHY_CMN_RX_BANDGAP_TIMER), 86 dphy->regs + DPHY_CMN_SSM); 87 88 return 0; 89 } 90 91 static int cdns_dphy_rx_power_off(struct phy *phy) 92 { 93 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); 94 95 writel(0, dphy->regs + DPHY_CMN_SSM); 96 97 return 0; 98 } 99 100 static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) 101 { 102 unsigned int rate, i; 103 104 rate = hs_clk_rate / 1000000UL; 105 /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ 106 rate *= 2; 107 108 if (rate < bands[0].min_rate) 109 return -EOPNOTSUPP; 110 111 for (i = 0; i < ARRAY_SIZE(bands); i++) 112 if (rate < bands[i].max_rate) 113 return i; 114 115 return -EOPNOTSUPP; 116 } 117 118 static inline int cdns_dphy_rx_wait_for_bit(void __iomem *addr, 119 unsigned int bit) 120 { 121 u32 val; 122 123 return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, 124 DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); 125 } 126 127 static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, 128 unsigned int lanes) 129 { 130 static const u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0, 131 DPHY_ISO_DL_CTRL_L1, 132 DPHY_ISO_DL_CTRL_L2, 133 DPHY_ISO_DL_CTRL_L3}; 134 void __iomem *reg = dphy->regs; 135 unsigned int i; 136 int ret; 137 138 /* Clock lane */ 139 ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, 140 DPHY_ISO_LANE_READY_BIT); 141 if (ret) 142 return ret; 143 144 for (i = 0; i < lanes; i++) { 145 ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i], 146 DPHY_ISO_LANE_READY_BIT); 147 if (ret) 148 return ret; 149 } 150 151 return 0; 152 } 153 154 static struct cdns_dphy_soc_data j721e_soc_data = { 155 .has_hw_cmn_rstb = true, 156 }; 157 158 static const struct soc_device_attribute cdns_dphy_socinfo[] = { 159 { 160 .family = "J721E", 161 .revision = "SR1.0", 162 .data = &j721e_soc_data, 163 }, 164 {/* sentinel */} 165 }; 166 167 static int cdns_dphy_rx_configure(struct phy *phy, 168 union phy_configure_opts *opts) 169 { 170 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); 171 unsigned int reg, lanes = opts->mipi_dphy.lanes; 172 const struct cdns_dphy_soc_data *soc_data = NULL; 173 const struct soc_device_attribute *soc; 174 int band_ctrl, ret; 175 176 soc = soc_device_match(cdns_dphy_socinfo); 177 if (soc && soc->data) 178 soc_data = soc->data; 179 if (!soc || (soc_data && !soc_data->has_hw_cmn_rstb)) { 180 reg = DPHY_LANE_RESET_CMN_EN; 181 writel(reg, dphy->regs + DPHY_LANE); 182 } 183 184 /* Data lanes. Minimum one lane is mandatory. */ 185 if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) 186 return -EINVAL; 187 188 band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); 189 if (band_ctrl < 0) 190 return band_ctrl; 191 192 reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | 193 FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); 194 writel(reg, dphy->regs + DPHY_BAND_CFG); 195 196 /* 197 * Set the required power island phase 2 time. This is mandated by DPHY 198 * specs. 199 */ 200 reg = DPHY_POWER_ISLAND_EN_DATA_VAL; 201 writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); 202 reg = DPHY_POWER_ISLAND_EN_CLK_VAL; 203 writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); 204 205 ret = cdns_dphy_rx_wait_lane_ready(dphy, lanes); 206 if (ret) { 207 dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); 208 return ret; 209 } 210 211 return 0; 212 } 213 214 static int cdns_dphy_rx_validate(struct phy *phy, enum phy_mode mode, 215 int submode, union phy_configure_opts *opts) 216 { 217 int ret; 218 219 if (mode != PHY_MODE_MIPI_DPHY) 220 return -EINVAL; 221 222 ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); 223 if (ret < 0) 224 return ret; 225 226 return phy_mipi_dphy_config_validate(&opts->mipi_dphy); 227 } 228 229 static const struct phy_ops cdns_dphy_rx_ops = { 230 .power_on = cdns_dphy_rx_power_on, 231 .power_off = cdns_dphy_rx_power_off, 232 .configure = cdns_dphy_rx_configure, 233 .validate = cdns_dphy_rx_validate, 234 }; 235 236 static int cdns_dphy_rx_probe(struct platform_device *pdev) 237 { 238 struct device *dev = &pdev->dev; 239 struct phy_provider *provider; 240 struct cdns_dphy_rx *dphy; 241 242 dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL); 243 if (!dphy) 244 return -ENOMEM; 245 246 dev_set_drvdata(dev, dphy); 247 dphy->dev = dev; 248 249 dphy->regs = devm_platform_ioremap_resource(pdev, 0); 250 if (IS_ERR(dphy->regs)) 251 return PTR_ERR(dphy->regs); 252 253 dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops); 254 if (IS_ERR(dphy->phy)) { 255 dev_err(dev, "Failed to create PHY: %ld\n", PTR_ERR(dphy->phy)); 256 return PTR_ERR(dphy->phy); 257 } 258 259 phy_set_drvdata(dphy->phy, dphy); 260 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 261 if (IS_ERR(provider)) { 262 dev_err(dev, "Failed to register PHY provider: %ld\n", 263 PTR_ERR(provider)); 264 return PTR_ERR(provider); 265 } 266 267 return 0; 268 } 269 270 static const struct of_device_id cdns_dphy_rx_of_match[] = { 271 { .compatible = "cdns,dphy-rx" }, 272 { /* sentinel */ }, 273 }; 274 MODULE_DEVICE_TABLE(of, cdns_dphy_rx_of_match); 275 276 static struct platform_driver cdns_dphy_rx_platform_driver = { 277 .probe = cdns_dphy_rx_probe, 278 .driver = { 279 .name = "cdns-mipi-dphy-rx", 280 .of_match_table = cdns_dphy_rx_of_match, 281 }, 282 }; 283 module_platform_driver(cdns_dphy_rx_platform_driver); 284 285 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 286 MODULE_DESCRIPTION("Cadence D-PHY Rx Driver"); 287 MODULE_LICENSE("GPL"); 288