1 /* 2 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions 3 * 4 * Copyright (C) 2014-2017 Broadcom 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 /* 17 * This module contains USB PHY initialization for power up and S3 resume 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/io.h> 22 23 #include <linux/soc/brcmstb/brcmstb.h> 24 #include "phy-brcm-usb-init.h" 25 26 #define PHY_PORTS 2 27 #define PHY_PORT_SELECT_0 0 28 #define PHY_PORT_SELECT_1 0x1000 29 30 /* Register definitions for the USB CTRL block */ 31 #define USB_CTRL_SETUP 0x00 32 #define USB_CTRL_SETUP_IOC_MASK 0x00000010 33 #define USB_CTRL_SETUP_IPP_MASK 0x00000020 34 #define USB_CTRL_SETUP_BABO_MASK 0x00000001 35 #define USB_CTRL_SETUP_FNHW_MASK 0x00000002 36 #define USB_CTRL_SETUP_FNBO_MASK 0x00000004 37 #define USB_CTRL_SETUP_WABO_MASK 0x00000008 38 #define USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK 0x00002000 /* option */ 39 #define USB_CTRL_SETUP_SCB1_EN_MASK 0x00004000 /* option */ 40 #define USB_CTRL_SETUP_SCB2_EN_MASK 0x00008000 /* option */ 41 #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK 0X00020000 /* option */ 42 #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK 0x00010000 /* option */ 43 #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK 0x02000000 /* option */ 44 #define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK 0x04000000 /* option */ 45 #define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK 0x08000000 /* opt */ 46 #define USB_CTRL_SETUP_OC3_DISABLE_MASK 0xc0000000 /* option */ 47 #define USB_CTRL_PLL_CTL 0x04 48 #define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000 49 #define USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000 50 #define USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000 /* option */ 51 #define USB_CTRL_EBRIDGE 0x0c 52 #define USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK 0x00020000 /* option */ 53 #define USB_CTRL_OBRIDGE 0x10 54 #define USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK 0x08000000 55 #define USB_CTRL_MDIO 0x14 56 #define USB_CTRL_MDIO2 0x18 57 #define USB_CTRL_UTMI_CTL_1 0x2c 58 #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800 59 #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK 0x08000000 60 #define USB_CTRL_USB_PM 0x34 61 #define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK 0x00800000 /* option */ 62 #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK 0x00400000 /* option */ 63 #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK 0x40000000 /* option */ 64 #define USB_CTRL_USB_PM_USB_PWRDN_MASK 0x80000000 /* option */ 65 #define USB_CTRL_USB_PM_SOFT_RESET_MASK 0x40000000 /* option */ 66 #define USB_CTRL_USB_PM_USB20_HC_RESETB_MASK 0x30000000 /* option */ 67 #define USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK 0x00300000 /* option */ 68 #define USB_CTRL_USB30_CTL1 0x60 69 #define USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK 0x00000010 70 #define USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK 0x00010000 71 #define USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK 0x00020000 /* option */ 72 #define USB_CTRL_USB30_CTL1_USB3_IOC_MASK 0x10000000 /* option */ 73 #define USB_CTRL_USB30_CTL1_USB3_IPP_MASK 0x20000000 /* option */ 74 #define USB_CTRL_USB30_PCTL 0x70 75 #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002 76 #define USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK 0x00008000 77 #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000 78 #define USB_CTRL_USB_DEVICE_CTL1 0x90 79 #define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK 0x00000003 /* option */ 80 81 /* Register definitions for the XHCI EC block */ 82 #define USB_XHCI_EC_IRAADR 0x658 83 #define USB_XHCI_EC_IRADAT 0x65c 84 85 enum brcm_family_type { 86 BRCM_FAMILY_3390A0, 87 BRCM_FAMILY_7250B0, 88 BRCM_FAMILY_7271A0, 89 BRCM_FAMILY_7364A0, 90 BRCM_FAMILY_7366C0, 91 BRCM_FAMILY_74371A0, 92 BRCM_FAMILY_7439B0, 93 BRCM_FAMILY_7445D0, 94 BRCM_FAMILY_7260A0, 95 BRCM_FAMILY_7278A0, 96 BRCM_FAMILY_COUNT, 97 }; 98 99 #define USB_BRCM_FAMILY(chip) \ 100 [BRCM_FAMILY_##chip] = __stringify(chip) 101 102 static const char *family_names[BRCM_FAMILY_COUNT] = { 103 USB_BRCM_FAMILY(3390A0), 104 USB_BRCM_FAMILY(7250B0), 105 USB_BRCM_FAMILY(7271A0), 106 USB_BRCM_FAMILY(7364A0), 107 USB_BRCM_FAMILY(7366C0), 108 USB_BRCM_FAMILY(74371A0), 109 USB_BRCM_FAMILY(7439B0), 110 USB_BRCM_FAMILY(7445D0), 111 USB_BRCM_FAMILY(7260A0), 112 USB_BRCM_FAMILY(7278A0), 113 }; 114 115 enum { 116 USB_CTRL_SETUP_SCB1_EN_SELECTOR, 117 USB_CTRL_SETUP_SCB2_EN_SELECTOR, 118 USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR, 119 USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR, 120 USB_CTRL_SETUP_OC3_DISABLE_SELECTOR, 121 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR, 122 USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR, 123 USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR, 124 USB_CTRL_USB_PM_USB_PWRDN_SELECTOR, 125 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR, 126 USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR, 127 USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR, 128 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR, 129 USB_CTRL_USB_PM_SOFT_RESET_SELECTOR, 130 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR, 131 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR, 132 USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR, 133 USB_CTRL_SETUP_ENDIAN_SELECTOR, 134 USB_CTRL_SELECTOR_COUNT, 135 }; 136 137 #define USB_CTRL_REG(base, reg) ((void *)base + USB_CTRL_##reg) 138 #define USB_XHCI_EC_REG(base, reg) ((void *)base + USB_XHCI_EC_##reg) 139 #define USB_CTRL_MASK(reg, field) \ 140 USB_CTRL_##reg##_##field##_MASK 141 #define USB_CTRL_MASK_FAMILY(params, reg, field) \ 142 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR]) 143 144 #define USB_CTRL_SET_FAMILY(params, reg, field) \ 145 usb_ctrl_set_family(params, USB_CTRL_##reg, \ 146 USB_CTRL_##reg##_##field##_SELECTOR) 147 #define USB_CTRL_UNSET_FAMILY(params, reg, field) \ 148 usb_ctrl_unset_family(params, USB_CTRL_##reg, \ 149 USB_CTRL_##reg##_##field##_SELECTOR) 150 151 #define USB_CTRL_SET(base, reg, field) \ 152 usb_ctrl_set(USB_CTRL_REG(base, reg), \ 153 USB_CTRL_##reg##_##field##_MASK) 154 #define USB_CTRL_UNSET(base, reg, field) \ 155 usb_ctrl_unset(USB_CTRL_REG(base, reg), \ 156 USB_CTRL_##reg##_##field##_MASK) 157 158 #define MDIO_USB2 0 159 #define MDIO_USB3 BIT(31) 160 161 #define USB_CTRL_SETUP_ENDIAN_BITS ( \ 162 USB_CTRL_MASK(SETUP, BABO) | \ 163 USB_CTRL_MASK(SETUP, FNHW) | \ 164 USB_CTRL_MASK(SETUP, FNBO) | \ 165 USB_CTRL_MASK(SETUP, WABO)) 166 167 #ifdef __LITTLE_ENDIAN 168 #define ENDIAN_SETTINGS ( \ 169 USB_CTRL_MASK(SETUP, BABO) | \ 170 USB_CTRL_MASK(SETUP, FNHW)) 171 #else 172 #define ENDIAN_SETTINGS ( \ 173 USB_CTRL_MASK(SETUP, FNHW) | \ 174 USB_CTRL_MASK(SETUP, FNBO) | \ 175 USB_CTRL_MASK(SETUP, WABO)) 176 #endif 177 178 struct id_to_type { 179 u32 id; 180 int type; 181 }; 182 183 static const struct id_to_type id_to_type_table[] = { 184 { 0x33900000, BRCM_FAMILY_3390A0 }, 185 { 0x72500010, BRCM_FAMILY_7250B0 }, 186 { 0x72600000, BRCM_FAMILY_7260A0 }, 187 { 0x72680000, BRCM_FAMILY_7271A0 }, 188 { 0x72710000, BRCM_FAMILY_7271A0 }, 189 { 0x73640000, BRCM_FAMILY_7364A0 }, 190 { 0x73660020, BRCM_FAMILY_7366C0 }, 191 { 0x07437100, BRCM_FAMILY_74371A0 }, 192 { 0x74390010, BRCM_FAMILY_7439B0 }, 193 { 0x74450030, BRCM_FAMILY_7445D0 }, 194 { 0x72780000, BRCM_FAMILY_7278A0 }, 195 { 0, BRCM_FAMILY_7271A0 }, /* default */ 196 }; 197 198 static const u32 199 usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { 200 /* 3390B0 */ 201 [BRCM_FAMILY_3390A0] = { 202 USB_CTRL_SETUP_SCB1_EN_MASK, 203 USB_CTRL_SETUP_SCB2_EN_MASK, 204 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 205 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 206 USB_CTRL_SETUP_OC3_DISABLE_MASK, 207 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 208 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 209 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 210 USB_CTRL_USB_PM_USB_PWRDN_MASK, 211 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 212 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 213 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 214 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 215 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 216 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 217 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 218 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 219 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 220 }, 221 /* 7250b0 */ 222 [BRCM_FAMILY_7250B0] = { 223 USB_CTRL_SETUP_SCB1_EN_MASK, 224 USB_CTRL_SETUP_SCB2_EN_MASK, 225 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 226 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 227 USB_CTRL_SETUP_OC3_DISABLE_MASK, 228 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 229 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 230 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK, 231 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 232 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 233 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 234 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 235 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 236 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 237 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 238 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 239 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK, 240 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 241 }, 242 /* 7271a0 */ 243 [BRCM_FAMILY_7271A0] = { 244 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */ 245 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 246 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 247 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 248 USB_CTRL_SETUP_OC3_DISABLE_MASK, 249 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 250 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 251 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 252 USB_CTRL_USB_PM_USB_PWRDN_MASK, 253 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 254 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 255 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 256 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 257 USB_CTRL_USB_PM_SOFT_RESET_MASK, 258 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK, 259 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK, 260 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 261 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 262 }, 263 /* 7364a0 */ 264 [BRCM_FAMILY_7364A0] = { 265 USB_CTRL_SETUP_SCB1_EN_MASK, 266 USB_CTRL_SETUP_SCB2_EN_MASK, 267 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 268 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 269 USB_CTRL_SETUP_OC3_DISABLE_MASK, 270 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 271 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 272 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK, 273 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 274 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 275 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 276 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 277 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 278 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 279 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 280 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 281 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK, 282 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 283 }, 284 /* 7366c0 */ 285 [BRCM_FAMILY_7366C0] = { 286 USB_CTRL_SETUP_SCB1_EN_MASK, 287 USB_CTRL_SETUP_SCB2_EN_MASK, 288 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 289 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 290 USB_CTRL_SETUP_OC3_DISABLE_MASK, 291 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 292 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 293 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK, 294 USB_CTRL_USB_PM_USB_PWRDN_MASK, 295 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 296 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 297 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 298 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 299 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 300 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 301 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 302 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK, 303 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 304 }, 305 /* 74371A0 */ 306 [BRCM_FAMILY_74371A0] = { 307 USB_CTRL_SETUP_SCB1_EN_MASK, 308 USB_CTRL_SETUP_SCB2_EN_MASK, 309 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 310 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 311 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */ 312 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 313 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 314 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */ 315 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 316 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK, 317 USB_CTRL_USB30_CTL1_USB3_IOC_MASK, 318 USB_CTRL_USB30_CTL1_USB3_IPP_MASK, 319 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 320 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 321 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 322 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 323 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */ 324 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 325 }, 326 /* 7439B0 */ 327 [BRCM_FAMILY_7439B0] = { 328 USB_CTRL_SETUP_SCB1_EN_MASK, 329 USB_CTRL_SETUP_SCB2_EN_MASK, 330 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 331 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 332 USB_CTRL_SETUP_OC3_DISABLE_MASK, 333 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 334 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 335 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 336 USB_CTRL_USB_PM_USB_PWRDN_MASK, 337 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 338 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 339 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 340 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 341 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 342 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 343 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 344 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 345 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 346 }, 347 /* 7445d0 */ 348 [BRCM_FAMILY_7445D0] = { 349 USB_CTRL_SETUP_SCB1_EN_MASK, 350 USB_CTRL_SETUP_SCB2_EN_MASK, 351 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 352 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 353 USB_CTRL_SETUP_OC3_DISABLE_MASK, 354 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 355 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 356 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */ 357 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 358 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK, 359 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 360 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 361 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 362 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 363 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 364 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 365 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 366 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 367 }, 368 /* 7260a0 */ 369 [BRCM_FAMILY_7260A0] = { 370 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */ 371 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 372 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 373 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 374 USB_CTRL_SETUP_OC3_DISABLE_MASK, 375 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 376 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 377 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 378 USB_CTRL_USB_PM_USB_PWRDN_MASK, 379 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 380 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 381 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 382 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 383 USB_CTRL_USB_PM_SOFT_RESET_MASK, 384 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK, 385 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK, 386 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 387 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 388 }, 389 /* 7278a0 */ 390 [BRCM_FAMILY_7278A0] = { 391 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */ 392 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 393 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */ 394 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 395 USB_CTRL_SETUP_OC3_DISABLE_MASK, 396 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 397 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 398 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 399 USB_CTRL_USB_PM_USB_PWRDN_MASK, 400 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 401 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 402 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 403 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 404 USB_CTRL_USB_PM_SOFT_RESET_MASK, 405 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 406 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 407 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */ 408 0, /* USB_CTRL_SETUP ENDIAN bits */ 409 }, 410 }; 411 412 static inline u32 brcmusb_readl(void __iomem *addr) 413 { 414 return readl(addr); 415 } 416 417 static inline void brcmusb_writel(u32 val, void __iomem *addr) 418 { 419 writel(val, addr); 420 } 421 422 static inline 423 void usb_ctrl_unset_family(struct brcm_usb_init_params *params, 424 u32 reg_offset, u32 field) 425 { 426 u32 mask; 427 void *reg; 428 429 mask = params->usb_reg_bits_map[field]; 430 reg = params->ctrl_regs + reg_offset; 431 brcmusb_writel(brcmusb_readl(reg) & ~mask, reg); 432 }; 433 434 static inline 435 void usb_ctrl_set_family(struct brcm_usb_init_params *params, 436 u32 reg_offset, u32 field) 437 { 438 u32 mask; 439 void *reg; 440 441 mask = params->usb_reg_bits_map[field]; 442 reg = params->ctrl_regs + reg_offset; 443 brcmusb_writel(brcmusb_readl(reg) | mask, reg); 444 }; 445 446 static inline void usb_ctrl_set(void __iomem *reg, u32 field) 447 { 448 u32 value; 449 450 value = brcmusb_readl(reg); 451 brcmusb_writel(value | field, reg); 452 } 453 454 static inline void usb_ctrl_unset(void __iomem *reg, u32 field) 455 { 456 u32 value; 457 458 value = brcmusb_readl(reg); 459 brcmusb_writel(value & ~field, reg); 460 } 461 462 static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode) 463 { 464 u32 data; 465 466 data = (reg << 16) | mode; 467 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 468 data |= (1 << 24); 469 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 470 data &= ~(1 << 24); 471 /* wait for the 60MHz parallel to serial shifter */ 472 usleep_range(10, 20); 473 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 474 /* wait for the 60MHz parallel to serial shifter */ 475 usleep_range(10, 20); 476 477 return brcmusb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff; 478 } 479 480 static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg, 481 u32 val, int mode) 482 { 483 u32 data; 484 485 data = (reg << 16) | val | mode; 486 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 487 data |= (1 << 25); 488 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 489 data &= ~(1 << 25); 490 491 /* wait for the 60MHz parallel to serial shifter */ 492 usleep_range(10, 20); 493 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 494 /* wait for the 60MHz parallel to serial shifter */ 495 usleep_range(10, 20); 496 } 497 498 static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base) 499 { 500 /* first disable FSM but also leave it that way */ 501 /* to allow normal suspend/resume */ 502 USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN); 503 USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN_P1); 504 505 /* reset USB 2.0 PLL */ 506 USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB); 507 /* PLL reset period */ 508 udelay(1); 509 USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB); 510 /* Give PLL enough time to lock */ 511 usleep_range(1000, 2000); 512 } 513 514 static void brcmusb_usb2_eye_fix(void __iomem *ctrl_base) 515 { 516 /* Increase USB 2.0 TX level to meet spec requirement */ 517 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2); 518 brcmusb_usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2); 519 } 520 521 static void brcmusb_usb3_pll_fix(void __iomem *ctrl_base) 522 { 523 /* Set correct window for PLL lock detect */ 524 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3); 525 brcmusb_usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3); 526 } 527 528 static void brcmusb_usb3_enable_pipe_reset(void __iomem *ctrl_base) 529 { 530 u32 val; 531 532 /* Re-enable USB 3.0 pipe reset */ 533 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3); 534 val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200; 535 brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3); 536 } 537 538 static void brcmusb_usb3_enable_sigdet(void __iomem *ctrl_base) 539 { 540 u32 val, ofs; 541 int ii; 542 543 ofs = 0; 544 for (ii = 0; ii < PHY_PORTS; ++ii) { 545 /* Set correct default for sigdet */ 546 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs), 547 MDIO_USB3); 548 val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3); 549 val = (val & ~0x800f) | 0x800d; 550 brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3); 551 ofs = PHY_PORT_SELECT_1; 552 } 553 } 554 555 static void brcmusb_usb3_enable_skip_align(void __iomem *ctrl_base) 556 { 557 u32 val, ofs; 558 int ii; 559 560 ofs = 0; 561 for (ii = 0; ii < PHY_PORTS; ++ii) { 562 /* Set correct default for SKIP align */ 563 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs), 564 MDIO_USB3); 565 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200; 566 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 567 ofs = PHY_PORT_SELECT_1; 568 } 569 } 570 571 static void brcmusb_usb3_unfreeze_aeq(void __iomem *ctrl_base) 572 { 573 u32 val, ofs; 574 int ii; 575 576 ofs = 0; 577 for (ii = 0; ii < PHY_PORTS; ++ii) { 578 /* Let EQ freeze after TSEQ */ 579 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs), 580 MDIO_USB3); 581 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3); 582 val &= ~0x0008; 583 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 584 ofs = PHY_PORT_SELECT_1; 585 } 586 } 587 588 static void brcmusb_usb3_pll_54mhz(struct brcm_usb_init_params *params) 589 { 590 u32 ofs; 591 int ii; 592 void __iomem *ctrl_base = params->ctrl_regs; 593 594 /* 595 * On newer B53 based SoC's, the reference clock for the 596 * 3.0 PLL has been changed from 50MHz to 54MHz so the 597 * PLL needs to be reprogrammed. 598 * See SWLINUX-4006. 599 * 600 * On the 7364C0, the reference clock for the 601 * 3.0 PLL has been changed from 50MHz to 54MHz to 602 * work around a MOCA issue. 603 * See SWLINUX-4169. 604 */ 605 switch (params->selected_family) { 606 case BRCM_FAMILY_3390A0: 607 case BRCM_FAMILY_7250B0: 608 case BRCM_FAMILY_7366C0: 609 case BRCM_FAMILY_74371A0: 610 case BRCM_FAMILY_7439B0: 611 case BRCM_FAMILY_7445D0: 612 case BRCM_FAMILY_7260A0: 613 return; 614 case BRCM_FAMILY_7364A0: 615 if (BRCM_REV(params->family_id) < 0x20) 616 return; 617 break; 618 } 619 620 /* set USB 3.0 PLL to accept 54Mhz reference clock */ 621 USB_CTRL_UNSET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START); 622 623 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3); 624 brcmusb_usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3); 625 brcmusb_usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3); 626 brcmusb_usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3); 627 brcmusb_usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3); 628 brcmusb_usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3); 629 brcmusb_usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3); 630 brcmusb_usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3); 631 brcmusb_usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3); 632 brcmusb_usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3); 633 634 /* both ports */ 635 ofs = 0; 636 for (ii = 0; ii < PHY_PORTS; ++ii) { 637 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs), 638 MDIO_USB3); 639 brcmusb_usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3); 640 brcmusb_usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3); 641 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs), 642 MDIO_USB3); 643 brcmusb_usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3); 644 ofs = PHY_PORT_SELECT_1; 645 } 646 647 /* restart PLL sequence */ 648 USB_CTRL_SET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START); 649 /* Give PLL enough time to lock */ 650 usleep_range(1000, 2000); 651 } 652 653 static void brcmusb_usb3_ssc_enable(void __iomem *ctrl_base) 654 { 655 u32 val; 656 657 /* Enable USB 3.0 TX spread spectrum */ 658 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3); 659 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf; 660 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 661 662 /* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers, 663 * which should have been adequate. However, due to a bug in the 664 * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26). 665 */ 666 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3); 667 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf; 668 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 669 } 670 671 static void brcmusb_usb3_phy_workarounds(struct brcm_usb_init_params *params) 672 { 673 void __iomem *ctrl_base = params->ctrl_regs; 674 675 brcmusb_usb3_pll_fix(ctrl_base); 676 brcmusb_usb3_pll_54mhz(params); 677 brcmusb_usb3_ssc_enable(ctrl_base); 678 brcmusb_usb3_enable_pipe_reset(ctrl_base); 679 brcmusb_usb3_enable_sigdet(ctrl_base); 680 brcmusb_usb3_enable_skip_align(ctrl_base); 681 brcmusb_usb3_unfreeze_aeq(ctrl_base); 682 } 683 684 static void brcmusb_memc_fix(struct brcm_usb_init_params *params) 685 { 686 u32 prid; 687 688 if (params->selected_family != BRCM_FAMILY_7445D0) 689 return; 690 /* 691 * This is a workaround for HW7445-1869 where a DMA write ends up 692 * doing a read pre-fetch after the end of the DMA buffer. This 693 * causes a problem when the DMA buffer is at the end of physical 694 * memory, causing the pre-fetch read to access non-existent memory, 695 * and the chip bondout has MEMC2 disabled. When the pre-fetch read 696 * tries to use the disabled MEMC2, it hangs the bus. The workaround 697 * is to disable MEMC2 access in the usb controller which avoids 698 * the hang. 699 */ 700 701 prid = params->product_id & 0xfffff000; 702 switch (prid) { 703 case 0x72520000: 704 case 0x74480000: 705 case 0x74490000: 706 case 0x07252000: 707 case 0x07448000: 708 case 0x07449000: 709 USB_CTRL_UNSET_FAMILY(params, SETUP, SCB2_EN); 710 } 711 } 712 713 static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params) 714 { 715 void __iomem *xhci_ec_base = params->xhci_ec_regs; 716 u32 val; 717 718 if (params->family_id != 0x74371000 || xhci_ec_base == 0) 719 return; 720 brcmusb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR)); 721 val = brcmusb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT)); 722 723 /* set cfg_pick_ss_lock */ 724 val |= (1 << 27); 725 brcmusb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT)); 726 727 /* Reset USB 3.0 PHY for workaround to take effect */ 728 USB_CTRL_UNSET(params->ctrl_regs, USB30_CTL1, PHY3_RESETB); 729 USB_CTRL_SET(params->ctrl_regs, USB30_CTL1, PHY3_RESETB); 730 } 731 732 static void brcmusb_xhci_soft_reset(struct brcm_usb_init_params *params, 733 int on_off) 734 { 735 /* Assert reset */ 736 if (on_off) { 737 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB)) 738 USB_CTRL_UNSET_FAMILY(params, USB_PM, XHC_SOFT_RESETB); 739 else 740 USB_CTRL_UNSET_FAMILY(params, 741 USB30_CTL1, XHC_SOFT_RESETB); 742 } else { /* De-assert reset */ 743 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB)) 744 USB_CTRL_SET_FAMILY(params, USB_PM, XHC_SOFT_RESETB); 745 else 746 USB_CTRL_SET_FAMILY(params, USB30_CTL1, 747 XHC_SOFT_RESETB); 748 } 749 } 750 751 /* 752 * Return the best map table family. The order is: 753 * - exact match of chip and major rev 754 * - exact match of chip and closest older major rev 755 * - default chip/rev. 756 * NOTE: The minor rev is always ignored. 757 */ 758 static enum brcm_family_type brcmusb_get_family_type( 759 struct brcm_usb_init_params *params) 760 { 761 int last_type = -1; 762 u32 last_family = 0; 763 u32 family_no_major; 764 unsigned int x; 765 u32 family; 766 767 family = params->family_id & 0xfffffff0; 768 family_no_major = params->family_id & 0xffffff00; 769 for (x = 0; id_to_type_table[x].id; x++) { 770 if (family == id_to_type_table[x].id) 771 return id_to_type_table[x].type; 772 if (family_no_major == (id_to_type_table[x].id & 0xffffff00)) 773 if (family > id_to_type_table[x].id && 774 last_family < id_to_type_table[x].id) { 775 last_family = id_to_type_table[x].id; 776 last_type = id_to_type_table[x].type; 777 } 778 } 779 780 /* If no match, return the default family */ 781 if (last_type == -1) 782 return id_to_type_table[x].type; 783 return last_type; 784 } 785 786 void brcm_usb_init_ipp(struct brcm_usb_init_params *params) 787 { 788 void __iomem *ctrl = params->ctrl_regs; 789 u32 reg; 790 u32 orig_reg; 791 792 /* Starting with the 7445d0, there are no longer separate 3.0 793 * versions of IOC and IPP. 794 */ 795 if (USB_CTRL_MASK_FAMILY(params, USB30_CTL1, USB3_IOC)) { 796 if (params->ioc) 797 USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IOC); 798 if (params->ipp == 1) 799 USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IPP); 800 } 801 802 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); 803 orig_reg = reg; 804 if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_CC_DRD_MODE_ENABLE_SEL)) 805 /* Never use the strap, it's going away. */ 806 reg &= ~(USB_CTRL_MASK_FAMILY(params, 807 SETUP, 808 STRAP_CC_DRD_MODE_ENABLE_SEL)); 809 if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_IPP_SEL)) 810 if (params->ipp != 2) 811 /* override ipp strap pin (if it exits) */ 812 reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP, 813 STRAP_IPP_SEL)); 814 815 /* Override the default OC and PP polarity */ 816 reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC)); 817 if (params->ioc) 818 reg |= USB_CTRL_MASK(SETUP, IOC); 819 if (params->ipp == 1 && ((reg & USB_CTRL_MASK(SETUP, IPP)) == 0)) 820 reg |= USB_CTRL_MASK(SETUP, IPP); 821 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); 822 823 /* 824 * If we're changing IPP, make sure power is off long enough 825 * to turn off any connected devices. 826 */ 827 if (reg != orig_reg) 828 msleep(50); 829 } 830 831 int brcm_usb_init_get_dual_select(struct brcm_usb_init_params *params) 832 { 833 void __iomem *ctrl = params->ctrl_regs; 834 u32 reg = 0; 835 836 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { 837 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 838 reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 839 PORT_MODE); 840 } 841 return reg; 842 } 843 844 void brcm_usb_init_set_dual_select(struct brcm_usb_init_params *params, 845 int mode) 846 { 847 void __iomem *ctrl = params->ctrl_regs; 848 u32 reg; 849 850 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { 851 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 852 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 853 PORT_MODE); 854 reg |= mode; 855 brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 856 } 857 } 858 859 void brcm_usb_init_common(struct brcm_usb_init_params *params) 860 { 861 u32 reg; 862 void __iomem *ctrl = params->ctrl_regs; 863 864 /* Take USB out of power down */ 865 if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) { 866 USB_CTRL_UNSET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN); 867 /* 1 millisecond - for USB clocks to settle down */ 868 usleep_range(1000, 2000); 869 } 870 871 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) { 872 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB_PWRDN); 873 /* 1 millisecond - for USB clocks to settle down */ 874 usleep_range(1000, 2000); 875 } 876 877 if (params->selected_family != BRCM_FAMILY_74371A0 && 878 (BRCM_ID(params->family_id) != 0x7364)) 879 /* 880 * HW7439-637: 7439a0 and its derivatives do not have large 881 * enough descriptor storage for this. 882 */ 883 USB_CTRL_SET_FAMILY(params, SETUP, SS_EHCI64BIT_EN); 884 885 /* Block auto PLL suspend by USB2 PHY (Sasi) */ 886 USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN); 887 888 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); 889 if (params->selected_family == BRCM_FAMILY_7364A0) 890 /* Suppress overcurrent indication from USB30 ports for A0 */ 891 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE); 892 893 brcmusb_usb_phy_ldo_fix(ctrl); 894 brcmusb_usb2_eye_fix(ctrl); 895 896 /* 897 * Make sure the the second and third memory controller 898 * interfaces are enabled if they exist. 899 */ 900 if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN)) 901 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN); 902 if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN)) 903 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN); 904 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); 905 906 brcmusb_memc_fix(params); 907 908 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { 909 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 910 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 911 PORT_MODE); 912 reg |= params->mode; 913 brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 914 } 915 if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) { 916 switch (params->mode) { 917 case USB_CTLR_MODE_HOST: 918 USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB); 919 break; 920 default: 921 USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB); 922 USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB); 923 break; 924 } 925 } 926 if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) { 927 if (params->mode == USB_CTLR_MODE_TYPEC_PD) 928 USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE); 929 else 930 USB_CTRL_UNSET_FAMILY(params, SETUP, 931 CC_DRD_MODE_ENABLE); 932 } 933 } 934 935 void brcm_usb_init_eohci(struct brcm_usb_init_params *params) 936 { 937 u32 reg; 938 void __iomem *ctrl = params->ctrl_regs; 939 940 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB)) 941 USB_CTRL_SET_FAMILY(params, USB_PM, USB20_HC_RESETB); 942 943 if (params->selected_family == BRCM_FAMILY_7366C0) 944 /* 945 * Don't enable this so the memory controller doesn't read 946 * into memory holes. NOTE: This bit is low true on 7366C0. 947 */ 948 USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ); 949 950 /* Setup the endian bits */ 951 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); 952 reg &= ~USB_CTRL_SETUP_ENDIAN_BITS; 953 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN); 954 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); 955 956 if (params->selected_family == BRCM_FAMILY_7271A0) 957 /* Enable LS keep alive fix for certain keyboards */ 958 USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE); 959 } 960 961 void brcm_usb_init_xhci(struct brcm_usb_init_params *params) 962 { 963 void __iomem *ctrl = params->ctrl_regs; 964 965 if (BRCM_ID(params->family_id) == 0x7366) { 966 /* 967 * The PHY3_SOFT_RESETB bits default to the wrong state. 968 */ 969 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB); 970 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB_P1); 971 } 972 973 /* 974 * Kick start USB3 PHY 975 * Make sure it's low to insure a rising edge. 976 */ 977 USB_CTRL_UNSET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START); 978 USB_CTRL_SET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START); 979 980 brcmusb_usb3_phy_workarounds(params); 981 brcmusb_xhci_soft_reset(params, 0); 982 brcmusb_usb3_otp_fix(params); 983 } 984 985 void brcm_usb_uninit_common(struct brcm_usb_init_params *params) 986 { 987 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) 988 USB_CTRL_SET_FAMILY(params, USB_PM, USB_PWRDN); 989 990 if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) 991 USB_CTRL_SET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN); 992 } 993 994 void brcm_usb_uninit_eohci(struct brcm_usb_init_params *params) 995 { 996 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB)) 997 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB20_HC_RESETB); 998 } 999 1000 void brcm_usb_uninit_xhci(struct brcm_usb_init_params *params) 1001 { 1002 brcmusb_xhci_soft_reset(params, 1); 1003 USB_CTRL_SET(params->ctrl_regs, USB30_PCTL, PHY3_IDDQ_OVERRIDE); 1004 } 1005 1006 void brcm_usb_set_family_map(struct brcm_usb_init_params *params) 1007 { 1008 int fam; 1009 1010 fam = brcmusb_get_family_type(params); 1011 params->selected_family = fam; 1012 params->usb_reg_bits_map = 1013 &usb_reg_bits_map_table[fam][0]; 1014 params->family_name = family_names[fam]; 1015 } 1016