1 /* 2 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions 3 * 4 * Copyright (C) 2014-2017 Broadcom 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 /* 17 * This module contains USB PHY initialization for power up and S3 resume 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/io.h> 22 23 #include <linux/soc/brcmstb/brcmstb.h> 24 #include "phy-brcm-usb-init.h" 25 26 #define PHY_PORTS 2 27 #define PHY_PORT_SELECT_0 0 28 #define PHY_PORT_SELECT_1 0x1000 29 30 /* Register definitions for the USB CTRL block */ 31 #define USB_CTRL_SETUP 0x00 32 #define USB_CTRL_SETUP_IOC_MASK 0x00000010 33 #define USB_CTRL_SETUP_IPP_MASK 0x00000020 34 #define USB_CTRL_SETUP_BABO_MASK 0x00000001 35 #define USB_CTRL_SETUP_FNHW_MASK 0x00000002 36 #define USB_CTRL_SETUP_FNBO_MASK 0x00000004 37 #define USB_CTRL_SETUP_WABO_MASK 0x00000008 38 #define USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK 0x00002000 /* option */ 39 #define USB_CTRL_SETUP_SCB1_EN_MASK 0x00004000 /* option */ 40 #define USB_CTRL_SETUP_SCB2_EN_MASK 0x00008000 /* option */ 41 #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK 0X00020000 /* option */ 42 #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK 0x00010000 /* option */ 43 #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK 0x02000000 /* option */ 44 #define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK 0x04000000 /* option */ 45 #define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK 0x08000000 /* opt */ 46 #define USB_CTRL_SETUP_OC3_DISABLE_MASK 0xc0000000 /* option */ 47 #define USB_CTRL_PLL_CTL 0x04 48 #define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000 49 #define USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000 50 #define USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000 /* option */ 51 #define USB_CTRL_EBRIDGE 0x0c 52 #define USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK 0x00020000 /* option */ 53 #define USB_CTRL_MDIO 0x14 54 #define USB_CTRL_MDIO2 0x18 55 #define USB_CTRL_UTMI_CTL_1 0x2c 56 #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800 57 #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK 0x08000000 58 #define USB_CTRL_USB_PM 0x34 59 #define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK 0x00800000 /* option */ 60 #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK 0x00400000 /* option */ 61 #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK 0x40000000 /* option */ 62 #define USB_CTRL_USB_PM_USB_PWRDN_MASK 0x80000000 /* option */ 63 #define USB_CTRL_USB_PM_SOFT_RESET_MASK 0x40000000 /* option */ 64 #define USB_CTRL_USB_PM_USB20_HC_RESETB_MASK 0x30000000 /* option */ 65 #define USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK 0x00300000 /* option */ 66 #define USB_CTRL_USB30_CTL1 0x60 67 #define USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK 0x00000010 68 #define USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK 0x00010000 69 #define USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK 0x00020000 /* option */ 70 #define USB_CTRL_USB30_CTL1_USB3_IOC_MASK 0x10000000 /* option */ 71 #define USB_CTRL_USB30_CTL1_USB3_IPP_MASK 0x20000000 /* option */ 72 #define USB_CTRL_USB30_PCTL 0x70 73 #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002 74 #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000 75 #define USB_CTRL_USB_DEVICE_CTL1 0x90 76 #define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK 0x00000003 /* option */ 77 78 /* Register definitions for the XHCI EC block */ 79 #define USB_XHCI_EC_IRAADR 0x658 80 #define USB_XHCI_EC_IRADAT 0x65c 81 82 enum brcm_family_type { 83 BRCM_FAMILY_3390A0, 84 BRCM_FAMILY_7250B0, 85 BRCM_FAMILY_7271A0, 86 BRCM_FAMILY_7364A0, 87 BRCM_FAMILY_7366C0, 88 BRCM_FAMILY_74371A0, 89 BRCM_FAMILY_7439B0, 90 BRCM_FAMILY_7445D0, 91 BRCM_FAMILY_7260A0, 92 BRCM_FAMILY_7278A0, 93 BRCM_FAMILY_COUNT, 94 }; 95 96 #define USB_BRCM_FAMILY(chip) \ 97 [BRCM_FAMILY_##chip] = __stringify(chip) 98 99 static const char *family_names[BRCM_FAMILY_COUNT] = { 100 USB_BRCM_FAMILY(3390A0), 101 USB_BRCM_FAMILY(7250B0), 102 USB_BRCM_FAMILY(7271A0), 103 USB_BRCM_FAMILY(7364A0), 104 USB_BRCM_FAMILY(7366C0), 105 USB_BRCM_FAMILY(74371A0), 106 USB_BRCM_FAMILY(7439B0), 107 USB_BRCM_FAMILY(7445D0), 108 USB_BRCM_FAMILY(7260A0), 109 USB_BRCM_FAMILY(7278A0), 110 }; 111 112 enum { 113 USB_CTRL_SETUP_SCB1_EN_SELECTOR, 114 USB_CTRL_SETUP_SCB2_EN_SELECTOR, 115 USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR, 116 USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR, 117 USB_CTRL_SETUP_OC3_DISABLE_SELECTOR, 118 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR, 119 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SELECTOR, 120 USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR, 121 USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR, 122 USB_CTRL_USB_PM_USB_PWRDN_SELECTOR, 123 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR, 124 USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR, 125 USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR, 126 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR, 127 USB_CTRL_USB_PM_SOFT_RESET_SELECTOR, 128 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR, 129 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR, 130 USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR, 131 USB_CTRL_SETUP_ENDIAN_SELECTOR, 132 USB_CTRL_SELECTOR_COUNT, 133 }; 134 135 #define USB_CTRL_REG(base, reg) ((void *)base + USB_CTRL_##reg) 136 #define USB_XHCI_EC_REG(base, reg) ((void *)base + USB_XHCI_EC_##reg) 137 #define USB_CTRL_MASK(reg, field) \ 138 USB_CTRL_##reg##_##field##_MASK 139 #define USB_CTRL_MASK_FAMILY(params, reg, field) \ 140 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR]) 141 142 #define USB_CTRL_SET_FAMILY(params, reg, field) \ 143 usb_ctrl_set_family(params, USB_CTRL_##reg, \ 144 USB_CTRL_##reg##_##field##_SELECTOR) 145 #define USB_CTRL_UNSET_FAMILY(params, reg, field) \ 146 usb_ctrl_unset_family(params, USB_CTRL_##reg, \ 147 USB_CTRL_##reg##_##field##_SELECTOR) 148 149 #define USB_CTRL_SET(base, reg, field) \ 150 usb_ctrl_set(USB_CTRL_REG(base, reg), \ 151 USB_CTRL_##reg##_##field##_MASK) 152 #define USB_CTRL_UNSET(base, reg, field) \ 153 usb_ctrl_unset(USB_CTRL_REG(base, reg), \ 154 USB_CTRL_##reg##_##field##_MASK) 155 156 #define MDIO_USB2 0 157 #define MDIO_USB3 BIT(31) 158 159 #define USB_CTRL_SETUP_ENDIAN_BITS ( \ 160 USB_CTRL_MASK(SETUP, BABO) | \ 161 USB_CTRL_MASK(SETUP, FNHW) | \ 162 USB_CTRL_MASK(SETUP, FNBO) | \ 163 USB_CTRL_MASK(SETUP, WABO)) 164 165 #ifdef __LITTLE_ENDIAN 166 #define ENDIAN_SETTINGS ( \ 167 USB_CTRL_MASK(SETUP, BABO) | \ 168 USB_CTRL_MASK(SETUP, FNHW)) 169 #else 170 #define ENDIAN_SETTINGS ( \ 171 USB_CTRL_MASK(SETUP, FNHW) | \ 172 USB_CTRL_MASK(SETUP, FNBO) | \ 173 USB_CTRL_MASK(SETUP, WABO)) 174 #endif 175 176 struct id_to_type { 177 u32 id; 178 int type; 179 }; 180 181 static const struct id_to_type id_to_type_table[] = { 182 { 0x33900000, BRCM_FAMILY_3390A0 }, 183 { 0x72500010, BRCM_FAMILY_7250B0 }, 184 { 0x72600000, BRCM_FAMILY_7260A0 }, 185 { 0x72680000, BRCM_FAMILY_7271A0 }, 186 { 0x72710000, BRCM_FAMILY_7271A0 }, 187 { 0x73640000, BRCM_FAMILY_7364A0 }, 188 { 0x73660020, BRCM_FAMILY_7366C0 }, 189 { 0x07437100, BRCM_FAMILY_74371A0 }, 190 { 0x74390010, BRCM_FAMILY_7439B0 }, 191 { 0x74450030, BRCM_FAMILY_7445D0 }, 192 { 0x72780000, BRCM_FAMILY_7278A0 }, 193 { 0, BRCM_FAMILY_7271A0 }, /* default */ 194 }; 195 196 static const u32 197 usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { 198 /* 3390B0 */ 199 [BRCM_FAMILY_3390A0] = { 200 USB_CTRL_SETUP_SCB1_EN_MASK, 201 USB_CTRL_SETUP_SCB2_EN_MASK, 202 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 203 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 204 USB_CTRL_SETUP_OC3_DISABLE_MASK, 205 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 206 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK, 207 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 208 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 209 USB_CTRL_USB_PM_USB_PWRDN_MASK, 210 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 211 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 212 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 213 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 214 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 215 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 216 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 217 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 218 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 219 }, 220 /* 7250b0 */ 221 [BRCM_FAMILY_7250B0] = { 222 USB_CTRL_SETUP_SCB1_EN_MASK, 223 USB_CTRL_SETUP_SCB2_EN_MASK, 224 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 225 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 226 USB_CTRL_SETUP_OC3_DISABLE_MASK, 227 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 228 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK, 229 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 230 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK, 231 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 232 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 233 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 234 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 235 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 236 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 237 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 238 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 239 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK, 240 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 241 }, 242 /* 7271a0 */ 243 [BRCM_FAMILY_7271A0] = { 244 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */ 245 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 246 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 247 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 248 USB_CTRL_SETUP_OC3_DISABLE_MASK, 249 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 250 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK, 251 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 252 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 253 USB_CTRL_USB_PM_USB_PWRDN_MASK, 254 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 255 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 256 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 257 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 258 USB_CTRL_USB_PM_SOFT_RESET_MASK, 259 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK, 260 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK, 261 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 262 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 263 }, 264 /* 7364a0 */ 265 [BRCM_FAMILY_7364A0] = { 266 USB_CTRL_SETUP_SCB1_EN_MASK, 267 USB_CTRL_SETUP_SCB2_EN_MASK, 268 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 269 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 270 USB_CTRL_SETUP_OC3_DISABLE_MASK, 271 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 272 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK, 273 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 274 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK, 275 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 276 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 277 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 278 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 279 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 280 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 281 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 282 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 283 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK, 284 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 285 }, 286 /* 7366c0 */ 287 [BRCM_FAMILY_7366C0] = { 288 USB_CTRL_SETUP_SCB1_EN_MASK, 289 USB_CTRL_SETUP_SCB2_EN_MASK, 290 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 291 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 292 USB_CTRL_SETUP_OC3_DISABLE_MASK, 293 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 294 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK, 295 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 296 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK, 297 USB_CTRL_USB_PM_USB_PWRDN_MASK, 298 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 299 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 300 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 301 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 302 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 303 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 304 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 305 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK, 306 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 307 }, 308 /* 74371A0 */ 309 [BRCM_FAMILY_74371A0] = { 310 USB_CTRL_SETUP_SCB1_EN_MASK, 311 USB_CTRL_SETUP_SCB2_EN_MASK, 312 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 313 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 314 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */ 315 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 316 0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */ 317 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 318 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */ 319 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 320 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK, 321 USB_CTRL_USB30_CTL1_USB3_IOC_MASK, 322 USB_CTRL_USB30_CTL1_USB3_IPP_MASK, 323 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 324 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 325 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 326 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 327 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */ 328 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 329 }, 330 /* 7439B0 */ 331 [BRCM_FAMILY_7439B0] = { 332 USB_CTRL_SETUP_SCB1_EN_MASK, 333 USB_CTRL_SETUP_SCB2_EN_MASK, 334 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 335 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 336 USB_CTRL_SETUP_OC3_DISABLE_MASK, 337 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 338 0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */ 339 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 340 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 341 USB_CTRL_USB_PM_USB_PWRDN_MASK, 342 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 343 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 344 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 345 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 346 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 347 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 348 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 349 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 350 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 351 }, 352 /* 7445d0 */ 353 [BRCM_FAMILY_7445D0] = { 354 USB_CTRL_SETUP_SCB1_EN_MASK, 355 USB_CTRL_SETUP_SCB2_EN_MASK, 356 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK, 357 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ 358 USB_CTRL_SETUP_OC3_DISABLE_MASK, 359 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK, 360 0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */ 361 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ 362 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */ 363 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */ 364 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK, 365 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 366 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 367 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ 368 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ 369 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 370 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 371 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 372 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 373 }, 374 /* 7260a0 */ 375 [BRCM_FAMILY_7260A0] = { 376 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */ 377 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 378 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK, 379 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 380 USB_CTRL_SETUP_OC3_DISABLE_MASK, 381 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 382 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK, 383 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 384 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 385 USB_CTRL_USB_PM_USB_PWRDN_MASK, 386 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 387 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 388 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 389 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 390 USB_CTRL_USB_PM_SOFT_RESET_MASK, 391 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK, 392 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK, 393 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, 394 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ 395 }, 396 /* 7278a0 */ 397 [BRCM_FAMILY_7278A0] = { 398 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */ 399 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ 400 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */ 401 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK, 402 USB_CTRL_SETUP_OC3_DISABLE_MASK, 403 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ 404 USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK, 405 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK, 406 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, 407 USB_CTRL_USB_PM_USB_PWRDN_MASK, 408 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ 409 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ 410 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ 411 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK, 412 USB_CTRL_USB_PM_SOFT_RESET_MASK, 413 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ 414 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ 415 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */ 416 0, /* USB_CTRL_SETUP ENDIAN bits */ 417 }, 418 }; 419 420 static inline u32 brcmusb_readl(void __iomem *addr) 421 { 422 return readl(addr); 423 } 424 425 static inline void brcmusb_writel(u32 val, void __iomem *addr) 426 { 427 writel(val, addr); 428 } 429 430 static inline 431 void usb_ctrl_unset_family(struct brcm_usb_init_params *params, 432 u32 reg_offset, u32 field) 433 { 434 u32 mask; 435 void *reg; 436 437 mask = params->usb_reg_bits_map[field]; 438 reg = params->ctrl_regs + reg_offset; 439 brcmusb_writel(brcmusb_readl(reg) & ~mask, reg); 440 }; 441 442 static inline 443 void usb_ctrl_set_family(struct brcm_usb_init_params *params, 444 u32 reg_offset, u32 field) 445 { 446 u32 mask; 447 void *reg; 448 449 mask = params->usb_reg_bits_map[field]; 450 reg = params->ctrl_regs + reg_offset; 451 brcmusb_writel(brcmusb_readl(reg) | mask, reg); 452 }; 453 454 static inline void usb_ctrl_set(void __iomem *reg, u32 field) 455 { 456 u32 value; 457 458 value = brcmusb_readl(reg); 459 brcmusb_writel(value | field, reg); 460 } 461 462 static inline void usb_ctrl_unset(void __iomem *reg, u32 field) 463 { 464 u32 value; 465 466 value = brcmusb_readl(reg); 467 brcmusb_writel(value & ~field, reg); 468 } 469 470 static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode) 471 { 472 u32 data; 473 474 data = (reg << 16) | mode; 475 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 476 data |= (1 << 24); 477 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 478 data &= ~(1 << 24); 479 /* wait for the 60MHz parallel to serial shifter */ 480 usleep_range(10, 20); 481 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 482 /* wait for the 60MHz parallel to serial shifter */ 483 usleep_range(10, 20); 484 485 return brcmusb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff; 486 } 487 488 static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg, 489 u32 val, int mode) 490 { 491 u32 data; 492 493 data = (reg << 16) | val | mode; 494 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 495 data |= (1 << 25); 496 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 497 data &= ~(1 << 25); 498 499 /* wait for the 60MHz parallel to serial shifter */ 500 usleep_range(10, 20); 501 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); 502 /* wait for the 60MHz parallel to serial shifter */ 503 usleep_range(10, 20); 504 } 505 506 static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base) 507 { 508 /* first disable FSM but also leave it that way */ 509 /* to allow normal suspend/resume */ 510 USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN); 511 USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN_P1); 512 513 /* reset USB 2.0 PLL */ 514 USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB); 515 /* PLL reset period */ 516 udelay(1); 517 USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB); 518 /* Give PLL enough time to lock */ 519 usleep_range(1000, 2000); 520 } 521 522 static void brcmusb_usb2_eye_fix(void __iomem *ctrl_base) 523 { 524 /* Increase USB 2.0 TX level to meet spec requirement */ 525 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2); 526 brcmusb_usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2); 527 } 528 529 static void brcmusb_usb3_pll_fix(void __iomem *ctrl_base) 530 { 531 /* Set correct window for PLL lock detect */ 532 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3); 533 brcmusb_usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3); 534 } 535 536 static void brcmusb_usb3_enable_pipe_reset(void __iomem *ctrl_base) 537 { 538 u32 val; 539 540 /* Re-enable USB 3.0 pipe reset */ 541 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3); 542 val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200; 543 brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3); 544 } 545 546 static void brcmusb_usb3_enable_sigdet(void __iomem *ctrl_base) 547 { 548 u32 val, ofs; 549 int ii; 550 551 ofs = 0; 552 for (ii = 0; ii < PHY_PORTS; ++ii) { 553 /* Set correct default for sigdet */ 554 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs), 555 MDIO_USB3); 556 val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3); 557 val = (val & ~0x800f) | 0x800d; 558 brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3); 559 ofs = PHY_PORT_SELECT_1; 560 } 561 } 562 563 static void brcmusb_usb3_enable_skip_align(void __iomem *ctrl_base) 564 { 565 u32 val, ofs; 566 int ii; 567 568 ofs = 0; 569 for (ii = 0; ii < PHY_PORTS; ++ii) { 570 /* Set correct default for SKIP align */ 571 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs), 572 MDIO_USB3); 573 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200; 574 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 575 ofs = PHY_PORT_SELECT_1; 576 } 577 } 578 579 static void brcmusb_usb3_unfreeze_aeq(void __iomem *ctrl_base) 580 { 581 u32 val, ofs; 582 int ii; 583 584 ofs = 0; 585 for (ii = 0; ii < PHY_PORTS; ++ii) { 586 /* Let EQ freeze after TSEQ */ 587 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs), 588 MDIO_USB3); 589 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3); 590 val &= ~0x0008; 591 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 592 ofs = PHY_PORT_SELECT_1; 593 } 594 } 595 596 static void brcmusb_usb3_pll_54mhz(struct brcm_usb_init_params *params) 597 { 598 u32 ofs; 599 int ii; 600 void __iomem *ctrl_base = params->ctrl_regs; 601 602 /* 603 * On newer B53 based SoC's, the reference clock for the 604 * 3.0 PLL has been changed from 50MHz to 54MHz so the 605 * PLL needs to be reprogrammed. 606 * See SWLINUX-4006. 607 * 608 * On the 7364C0, the reference clock for the 609 * 3.0 PLL has been changed from 50MHz to 54MHz to 610 * work around a MOCA issue. 611 * See SWLINUX-4169. 612 */ 613 switch (params->selected_family) { 614 case BRCM_FAMILY_3390A0: 615 case BRCM_FAMILY_7250B0: 616 case BRCM_FAMILY_7366C0: 617 case BRCM_FAMILY_74371A0: 618 case BRCM_FAMILY_7439B0: 619 case BRCM_FAMILY_7445D0: 620 case BRCM_FAMILY_7260A0: 621 return; 622 case BRCM_FAMILY_7364A0: 623 if (BRCM_REV(params->family_id) < 0x20) 624 return; 625 break; 626 } 627 628 /* set USB 3.0 PLL to accept 54Mhz reference clock */ 629 USB_CTRL_UNSET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START); 630 631 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3); 632 brcmusb_usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3); 633 brcmusb_usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3); 634 brcmusb_usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3); 635 brcmusb_usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3); 636 brcmusb_usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3); 637 brcmusb_usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3); 638 brcmusb_usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3); 639 brcmusb_usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3); 640 brcmusb_usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3); 641 642 /* both ports */ 643 ofs = 0; 644 for (ii = 0; ii < PHY_PORTS; ++ii) { 645 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs), 646 MDIO_USB3); 647 brcmusb_usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3); 648 brcmusb_usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3); 649 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs), 650 MDIO_USB3); 651 brcmusb_usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3); 652 ofs = PHY_PORT_SELECT_1; 653 } 654 655 /* restart PLL sequence */ 656 USB_CTRL_SET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START); 657 /* Give PLL enough time to lock */ 658 usleep_range(1000, 2000); 659 } 660 661 static void brcmusb_usb3_ssc_enable(void __iomem *ctrl_base) 662 { 663 u32 val; 664 665 /* Enable USB 3.0 TX spread spectrum */ 666 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3); 667 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf; 668 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 669 670 /* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers, 671 * which should have been adequate. However, due to a bug in the 672 * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26). 673 */ 674 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3); 675 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf; 676 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3); 677 } 678 679 static void brcmusb_usb3_phy_workarounds(struct brcm_usb_init_params *params) 680 { 681 void __iomem *ctrl_base = params->ctrl_regs; 682 683 brcmusb_usb3_pll_fix(ctrl_base); 684 brcmusb_usb3_pll_54mhz(params); 685 brcmusb_usb3_ssc_enable(ctrl_base); 686 brcmusb_usb3_enable_pipe_reset(ctrl_base); 687 brcmusb_usb3_enable_sigdet(ctrl_base); 688 brcmusb_usb3_enable_skip_align(ctrl_base); 689 brcmusb_usb3_unfreeze_aeq(ctrl_base); 690 } 691 692 static void brcmusb_memc_fix(struct brcm_usb_init_params *params) 693 { 694 u32 prid; 695 696 if (params->selected_family != BRCM_FAMILY_7445D0) 697 return; 698 /* 699 * This is a workaround for HW7445-1869 where a DMA write ends up 700 * doing a read pre-fetch after the end of the DMA buffer. This 701 * causes a problem when the DMA buffer is at the end of physical 702 * memory, causing the pre-fetch read to access non-existent memory, 703 * and the chip bondout has MEMC2 disabled. When the pre-fetch read 704 * tries to use the disabled MEMC2, it hangs the bus. The workaround 705 * is to disable MEMC2 access in the usb controller which avoids 706 * the hang. 707 */ 708 709 prid = params->product_id & 0xfffff000; 710 switch (prid) { 711 case 0x72520000: 712 case 0x74480000: 713 case 0x74490000: 714 case 0x07252000: 715 case 0x07448000: 716 case 0x07449000: 717 USB_CTRL_UNSET_FAMILY(params, SETUP, SCB2_EN); 718 } 719 } 720 721 static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params) 722 { 723 void __iomem *xhci_ec_base = params->xhci_ec_regs; 724 u32 val; 725 726 if (params->family_id != 0x74371000 || xhci_ec_base == 0) 727 return; 728 brcmusb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR)); 729 val = brcmusb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT)); 730 731 /* set cfg_pick_ss_lock */ 732 val |= (1 << 27); 733 brcmusb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT)); 734 735 /* Reset USB 3.0 PHY for workaround to take effect */ 736 USB_CTRL_UNSET(params->ctrl_regs, USB30_CTL1, PHY3_RESETB); 737 USB_CTRL_SET(params->ctrl_regs, USB30_CTL1, PHY3_RESETB); 738 } 739 740 static void brcmusb_xhci_soft_reset(struct brcm_usb_init_params *params, 741 int on_off) 742 { 743 /* Assert reset */ 744 if (on_off) { 745 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB)) 746 USB_CTRL_UNSET_FAMILY(params, USB_PM, XHC_SOFT_RESETB); 747 else 748 USB_CTRL_UNSET_FAMILY(params, 749 USB30_CTL1, XHC_SOFT_RESETB); 750 } else { /* De-assert reset */ 751 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB)) 752 USB_CTRL_SET_FAMILY(params, USB_PM, XHC_SOFT_RESETB); 753 else 754 USB_CTRL_SET_FAMILY(params, USB30_CTL1, 755 XHC_SOFT_RESETB); 756 } 757 } 758 759 /* 760 * Return the best map table family. The order is: 761 * - exact match of chip and major rev 762 * - exact match of chip and closest older major rev 763 * - default chip/rev. 764 * NOTE: The minor rev is always ignored. 765 */ 766 static enum brcm_family_type brcmusb_get_family_type( 767 struct brcm_usb_init_params *params) 768 { 769 int last_type = -1; 770 u32 last_family = 0; 771 u32 family_no_major; 772 unsigned int x; 773 u32 family; 774 775 family = params->family_id & 0xfffffff0; 776 family_no_major = params->family_id & 0xffffff00; 777 for (x = 0; id_to_type_table[x].id; x++) { 778 if (family == id_to_type_table[x].id) 779 return id_to_type_table[x].type; 780 if (family_no_major == (id_to_type_table[x].id & 0xffffff00)) 781 if (family > id_to_type_table[x].id && 782 last_family < id_to_type_table[x].id) { 783 last_family = id_to_type_table[x].id; 784 last_type = id_to_type_table[x].type; 785 } 786 } 787 788 /* If no match, return the default family */ 789 if (last_type == -1) 790 return id_to_type_table[x].type; 791 return last_type; 792 } 793 794 void brcm_usb_init_ipp(struct brcm_usb_init_params *params) 795 { 796 void __iomem *ctrl = params->ctrl_regs; 797 u32 reg; 798 u32 orig_reg; 799 800 /* Starting with the 7445d0, there are no longer separate 3.0 801 * versions of IOC and IPP. 802 */ 803 if (USB_CTRL_MASK_FAMILY(params, USB30_CTL1, USB3_IOC)) { 804 if (params->ioc) 805 USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IOC); 806 if (params->ipp == 1) 807 USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IPP); 808 } 809 810 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); 811 orig_reg = reg; 812 if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_CC_DRD_MODE_ENABLE_SEL)) 813 /* Never use the strap, it's going away. */ 814 reg &= ~(USB_CTRL_MASK_FAMILY(params, 815 SETUP, 816 STRAP_CC_DRD_MODE_ENABLE_SEL)); 817 if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_IPP_SEL)) 818 if (params->ipp != 2) 819 /* override ipp strap pin (if it exits) */ 820 reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP, 821 STRAP_IPP_SEL)); 822 823 /* Override the default OC and PP polarity */ 824 reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC)); 825 if (params->ioc) 826 reg |= USB_CTRL_MASK(SETUP, IOC); 827 if (params->ipp == 1 && ((reg & USB_CTRL_MASK(SETUP, IPP)) == 0)) 828 reg |= USB_CTRL_MASK(SETUP, IPP); 829 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); 830 831 /* 832 * If we're changing IPP, make sure power is off long enough 833 * to turn off any connected devices. 834 */ 835 if (reg != orig_reg) 836 msleep(50); 837 } 838 839 int brcm_usb_init_get_dual_select(struct brcm_usb_init_params *params) 840 { 841 void __iomem *ctrl = params->ctrl_regs; 842 u32 reg = 0; 843 844 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { 845 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 846 reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 847 PORT_MODE); 848 } 849 return reg; 850 } 851 852 void brcm_usb_init_set_dual_select(struct brcm_usb_init_params *params, 853 int mode) 854 { 855 void __iomem *ctrl = params->ctrl_regs; 856 u32 reg; 857 858 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { 859 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 860 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 861 PORT_MODE); 862 reg |= mode; 863 brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 864 } 865 } 866 867 void brcm_usb_init_common(struct brcm_usb_init_params *params) 868 { 869 u32 reg; 870 void __iomem *ctrl = params->ctrl_regs; 871 872 /* Take USB out of power down */ 873 if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) { 874 USB_CTRL_UNSET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN); 875 /* 1 millisecond - for USB clocks to settle down */ 876 usleep_range(1000, 2000); 877 } 878 879 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) { 880 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB_PWRDN); 881 /* 1 millisecond - for USB clocks to settle down */ 882 usleep_range(1000, 2000); 883 } 884 885 if (params->selected_family != BRCM_FAMILY_74371A0 && 886 (BRCM_ID(params->family_id) != 0x7364)) 887 /* 888 * HW7439-637: 7439a0 and its derivatives do not have large 889 * enough descriptor storage for this. 890 */ 891 USB_CTRL_SET_FAMILY(params, SETUP, SS_EHCI64BIT_EN); 892 893 /* Block auto PLL suspend by USB2 PHY (Sasi) */ 894 USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN); 895 896 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); 897 if (params->selected_family == BRCM_FAMILY_7364A0) 898 /* Suppress overcurrent indication from USB30 ports for A0 */ 899 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE); 900 901 brcmusb_usb_phy_ldo_fix(ctrl); 902 brcmusb_usb2_eye_fix(ctrl); 903 904 /* 905 * Make sure the the second and third memory controller 906 * interfaces are enabled if they exist. 907 */ 908 if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN)) 909 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN); 910 if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN)) 911 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN); 912 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); 913 914 brcmusb_memc_fix(params); 915 916 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) { 917 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 918 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 919 PORT_MODE); 920 reg |= params->mode; 921 brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 922 } 923 if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) { 924 switch (params->mode) { 925 case USB_CTLR_MODE_HOST: 926 USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB); 927 break; 928 default: 929 USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB); 930 break; 931 } 932 } 933 if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) { 934 if (params->mode == USB_CTLR_MODE_TYPEC_PD) 935 USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE); 936 else 937 USB_CTRL_UNSET_FAMILY(params, SETUP, 938 CC_DRD_MODE_ENABLE); 939 } 940 } 941 942 void brcm_usb_init_eohci(struct brcm_usb_init_params *params) 943 { 944 u32 reg; 945 void __iomem *ctrl = params->ctrl_regs; 946 947 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB)) 948 USB_CTRL_SET_FAMILY(params, USB_PM, USB20_HC_RESETB); 949 950 if (params->selected_family == BRCM_FAMILY_7366C0) 951 /* 952 * Don't enable this so the memory controller doesn't read 953 * into memory holes. NOTE: This bit is low true on 7366C0. 954 */ 955 USB_CTRL_SET_FAMILY(params, EBRIDGE, ESTOP_SCB_REQ); 956 957 /* Setup the endian bits */ 958 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); 959 reg &= ~USB_CTRL_SETUP_ENDIAN_BITS; 960 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN); 961 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); 962 } 963 964 void brcm_usb_init_xhci(struct brcm_usb_init_params *params) 965 { 966 void __iomem *ctrl = params->ctrl_regs; 967 968 if (BRCM_ID(params->family_id) == 0x7366) { 969 /* 970 * The PHY3_SOFT_RESETB bits default to the wrong state. 971 */ 972 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB); 973 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB_P1); 974 } 975 976 /* 977 * Kick start USB3 PHY 978 * Make sure it's low to insure a rising edge. 979 */ 980 USB_CTRL_UNSET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START); 981 USB_CTRL_SET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START); 982 983 brcmusb_usb3_phy_workarounds(params); 984 brcmusb_xhci_soft_reset(params, 0); 985 brcmusb_usb3_otp_fix(params); 986 } 987 988 void brcm_usb_uninit_common(struct brcm_usb_init_params *params) 989 { 990 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) 991 USB_CTRL_SET_FAMILY(params, USB_PM, USB_PWRDN); 992 993 if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) 994 USB_CTRL_SET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN); 995 } 996 997 void brcm_usb_uninit_eohci(struct brcm_usb_init_params *params) 998 { 999 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB)) 1000 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB20_HC_RESETB); 1001 } 1002 1003 void brcm_usb_uninit_xhci(struct brcm_usb_init_params *params) 1004 { 1005 brcmusb_xhci_soft_reset(params, 1); 1006 } 1007 1008 void brcm_usb_set_family_map(struct brcm_usb_init_params *params) 1009 { 1010 int fam; 1011 1012 fam = brcmusb_get_family_type(params); 1013 params->selected_family = fam; 1014 params->usb_reg_bits_map = 1015 &usb_reg_bits_map_table[fam][0]; 1016 params->family_name = family_names[fam]; 1017 } 1018