1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom SATA3 AHCI Controller PHY Driver 4 * 5 * Copyright (C) 2016 Broadcom 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 19 #define SATA_PCB_BANK_OFFSET 0x23c 20 #define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4) 21 22 #define MAX_PORTS 2 23 24 /* Register offset between PHYs in PCB space */ 25 #define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000 26 27 /* The older SATA PHY registers duplicated per port registers within the map, 28 * rather than having a separate map per port. 29 */ 30 #define SATA_PCB_REG_40NM_SPACE_SIZE 0x10 31 32 /* Register offset between PHYs in PHY control space */ 33 #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8 34 35 enum brcm_sata_phy_version { 36 BRCM_SATA_PHY_STB_28NM, 37 BRCM_SATA_PHY_STB_40NM, 38 BRCM_SATA_PHY_IPROC_NS2, 39 BRCM_SATA_PHY_IPROC_NSP, 40 BRCM_SATA_PHY_IPROC_SR, 41 BRCM_SATA_PHY_DSL_28NM, 42 }; 43 44 enum brcm_sata_phy_rxaeq_mode { 45 RXAEQ_MODE_OFF = 0, 46 RXAEQ_MODE_AUTO, 47 RXAEQ_MODE_MANUAL, 48 }; 49 50 static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m) 51 { 52 if (!strcmp(m, "auto")) 53 return RXAEQ_MODE_AUTO; 54 else if (!strcmp(m, "manual")) 55 return RXAEQ_MODE_MANUAL; 56 else 57 return RXAEQ_MODE_OFF; 58 } 59 60 struct brcm_sata_port { 61 int portnum; 62 struct phy *phy; 63 struct brcm_sata_phy *phy_priv; 64 bool ssc_en; 65 enum brcm_sata_phy_rxaeq_mode rxaeq_mode; 66 u32 rxaeq_val; 67 }; 68 69 struct brcm_sata_phy { 70 struct device *dev; 71 void __iomem *phy_base; 72 void __iomem *ctrl_base; 73 enum brcm_sata_phy_version version; 74 75 struct brcm_sata_port phys[MAX_PORTS]; 76 }; 77 78 enum sata_phy_regs { 79 BLOCK0_REG_BANK = 0x000, 80 BLOCK0_XGXSSTATUS = 0x81, 81 BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12), 82 BLOCK0_SPARE = 0x8d, 83 BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3, 84 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1, 85 86 PLL_REG_BANK_0 = 0x050, 87 PLL_REG_BANK_0_PLLCONTROL_0 = 0x81, 88 PLLCONTROL_0_FREQ_DET_RESTART = BIT(13), 89 PLLCONTROL_0_FREQ_MONITOR = BIT(12), 90 PLLCONTROL_0_SEQ_START = BIT(15), 91 PLL_CAP_CHARGE_TIME = 0x83, 92 PLL_VCO_CAL_THRESH = 0x84, 93 PLL_CAP_CONTROL = 0x85, 94 PLL_FREQ_DET_TIME = 0x86, 95 PLL_ACTRL2 = 0x8b, 96 PLL_ACTRL2_SELDIV_MASK = 0x1f, 97 PLL_ACTRL2_SELDIV_SHIFT = 9, 98 PLL_ACTRL6 = 0x86, 99 100 PLL1_REG_BANK = 0x060, 101 PLL1_ACTRL2 = 0x82, 102 PLL1_ACTRL3 = 0x83, 103 PLL1_ACTRL4 = 0x84, 104 PLL1_ACTRL5 = 0x85, 105 PLL1_ACTRL6 = 0x86, 106 PLL1_ACTRL7 = 0x87, 107 108 TX_REG_BANK = 0x070, 109 TX_ACTRL0 = 0x80, 110 TX_ACTRL0_TXPOL_FLIP = BIT(6), 111 112 AEQRX_REG_BANK_0 = 0xd0, 113 AEQ_CONTROL1 = 0x81, 114 AEQ_CONTROL1_ENABLE = BIT(2), 115 AEQ_CONTROL1_FREEZE = BIT(3), 116 AEQ_FRC_EQ = 0x83, 117 AEQ_FRC_EQ_FORCE = BIT(0), 118 AEQ_FRC_EQ_FORCE_VAL = BIT(1), 119 AEQRX_REG_BANK_1 = 0xe0, 120 AEQRX_SLCAL0_CTRL0 = 0x82, 121 AEQRX_SLCAL1_CTRL0 = 0x86, 122 123 OOB_REG_BANK = 0x150, 124 OOB1_REG_BANK = 0x160, 125 OOB_CTRL1 = 0x80, 126 OOB_CTRL1_BURST_MAX_MASK = 0xf, 127 OOB_CTRL1_BURST_MAX_SHIFT = 12, 128 OOB_CTRL1_BURST_MIN_MASK = 0xf, 129 OOB_CTRL1_BURST_MIN_SHIFT = 8, 130 OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf, 131 OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4, 132 OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf, 133 OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0, 134 OOB_CTRL2 = 0x81, 135 OOB_CTRL2_SEL_ENA_SHIFT = 15, 136 OOB_CTRL2_SEL_ENA_RC_SHIFT = 14, 137 OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f, 138 OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8, 139 OOB_CTRL2_BURST_CNT_MASK = 0x3, 140 OOB_CTRL2_BURST_CNT_SHIFT = 6, 141 OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f, 142 OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0, 143 144 TXPMD_REG_BANK = 0x1a0, 145 TXPMD_CONTROL1 = 0x81, 146 TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0), 147 TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1), 148 TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82, 149 TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83, 150 TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff, 151 TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84, 152 TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff, 153 154 RXPMD_REG_BANK = 0x1c0, 155 RXPMD_RX_FREQ_MON_CONTROL1 = 0x87, 156 }; 157 158 enum sata_phy_ctrl_regs { 159 PHY_CTRL_1 = 0x0, 160 PHY_CTRL_1_RESET = BIT(0), 161 }; 162 163 static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port) 164 { 165 struct brcm_sata_phy *priv = port->phy_priv; 166 u32 size = 0; 167 168 switch (priv->version) { 169 case BRCM_SATA_PHY_STB_28NM: 170 case BRCM_SATA_PHY_IPROC_NS2: 171 case BRCM_SATA_PHY_DSL_28NM: 172 size = SATA_PCB_REG_28NM_SPACE_SIZE; 173 break; 174 case BRCM_SATA_PHY_STB_40NM: 175 size = SATA_PCB_REG_40NM_SPACE_SIZE; 176 break; 177 default: 178 dev_err(priv->dev, "invalid phy version\n"); 179 break; 180 } 181 182 return priv->phy_base + (port->portnum * size); 183 } 184 185 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port) 186 { 187 struct brcm_sata_phy *priv = port->phy_priv; 188 u32 size = 0; 189 190 switch (priv->version) { 191 case BRCM_SATA_PHY_IPROC_NS2: 192 size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE; 193 break; 194 default: 195 dev_err(priv->dev, "invalid phy version\n"); 196 break; 197 } 198 199 return priv->ctrl_base + (port->portnum * size); 200 } 201 202 static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank, 203 u32 ofs, u32 msk, u32 value) 204 { 205 u32 tmp; 206 207 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); 208 tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs)); 209 tmp = (tmp & msk) | value; 210 writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs)); 211 } 212 213 static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs) 214 { 215 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); 216 return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs)); 217 } 218 219 /* These defaults were characterized by H/W group */ 220 #define STB_FMIN_VAL_DEFAULT 0x3df 221 #define STB_FMAX_VAL_DEFAULT 0x3df 222 #define STB_FMAX_VAL_SSC 0x83 223 224 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port) 225 { 226 void __iomem *base = brcm_sata_pcb_base(port); 227 struct brcm_sata_phy *priv = port->phy_priv; 228 u32 tmp; 229 230 /* override the TX spread spectrum setting */ 231 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC; 232 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp); 233 234 /* set fixed min freq */ 235 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2, 236 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK, 237 STB_FMIN_VAL_DEFAULT); 238 239 /* set fixed max freq depending on SSC config */ 240 if (port->ssc_en) { 241 dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum); 242 tmp = STB_FMAX_VAL_SSC; 243 } else { 244 tmp = STB_FMAX_VAL_DEFAULT; 245 } 246 247 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3, 248 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp); 249 } 250 251 #define AEQ_FRC_EQ_VAL_SHIFT 2 252 #define AEQ_FRC_EQ_VAL_MASK 0x3f 253 254 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port) 255 { 256 void __iomem *base = brcm_sata_pcb_base(port); 257 u32 tmp = 0, reg = 0; 258 259 switch (port->rxaeq_mode) { 260 case RXAEQ_MODE_OFF: 261 return 0; 262 263 case RXAEQ_MODE_AUTO: 264 reg = AEQ_CONTROL1; 265 tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE; 266 break; 267 268 case RXAEQ_MODE_MANUAL: 269 reg = AEQ_FRC_EQ; 270 tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL; 271 if (port->rxaeq_val > AEQ_FRC_EQ_VAL_MASK) 272 return -EINVAL; 273 tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT; 274 break; 275 } 276 277 brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp); 278 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp); 279 280 return 0; 281 } 282 283 static int brcm_stb_sata_init(struct brcm_sata_port *port) 284 { 285 brcm_stb_sata_ssc_init(port); 286 287 return brcm_stb_sata_rxaeq_init(port); 288 } 289 290 /* NS2 SATA PLL1 defaults were characterized by H/W group */ 291 #define NS2_PLL1_ACTRL2_MAGIC 0x1df8 292 #define NS2_PLL1_ACTRL3_MAGIC 0x2b00 293 #define NS2_PLL1_ACTRL4_MAGIC 0x8824 294 295 static int brcm_ns2_sata_init(struct brcm_sata_port *port) 296 { 297 int try; 298 unsigned int val; 299 void __iomem *base = brcm_sata_pcb_base(port); 300 void __iomem *ctrl_base = brcm_sata_ctrl_base(port); 301 struct device *dev = port->phy_priv->dev; 302 303 /* Configure OOB control */ 304 val = 0x0; 305 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT); 306 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT); 307 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); 308 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); 309 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); 310 val = 0x0; 311 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); 312 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT); 313 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); 314 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); 315 316 /* Configure PHY PLL register bank 1 */ 317 val = NS2_PLL1_ACTRL2_MAGIC; 318 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); 319 val = NS2_PLL1_ACTRL3_MAGIC; 320 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); 321 val = NS2_PLL1_ACTRL4_MAGIC; 322 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); 323 324 /* Configure PHY BLOCK0 register bank */ 325 /* Set oob_clk_sel to refclk/2 */ 326 brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE, 327 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK, 328 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2); 329 330 /* Strobe PHY reset using PHY control register */ 331 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1); 332 mdelay(1); 333 writel(0x0, ctrl_base + PHY_CTRL_1); 334 mdelay(1); 335 336 /* Wait for PHY PLL lock by polling pll_lock bit */ 337 try = 50; 338 while (try) { 339 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 340 BLOCK0_XGXSSTATUS); 341 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 342 break; 343 msleep(20); 344 try--; 345 } 346 if (!try) { 347 /* PLL did not lock; give up */ 348 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 349 return -ETIMEDOUT; 350 } 351 352 dev_dbg(dev, "port%d initialized\n", port->portnum); 353 354 return 0; 355 } 356 357 static int brcm_nsp_sata_init(struct brcm_sata_port *port) 358 { 359 struct brcm_sata_phy *priv = port->phy_priv; 360 struct device *dev = port->phy_priv->dev; 361 void __iomem *base = priv->phy_base; 362 unsigned int oob_bank; 363 unsigned int val, try; 364 365 /* Configure OOB control */ 366 if (port->portnum == 0) 367 oob_bank = OOB_REG_BANK; 368 else if (port->portnum == 1) 369 oob_bank = OOB1_REG_BANK; 370 else 371 return -EINVAL; 372 373 val = 0x0; 374 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT); 375 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT); 376 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); 377 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); 378 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val); 379 380 val = 0x0; 381 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); 382 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT); 383 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); 384 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val); 385 386 387 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2, 388 ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT), 389 0x0c << PLL_ACTRL2_SELDIV_SHIFT); 390 391 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL, 392 0xff0, 0x4f0); 393 394 val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR; 395 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 396 ~val, val); 397 val = PLLCONTROL_0_SEQ_START; 398 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 399 ~val, 0); 400 mdelay(10); 401 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 402 ~val, val); 403 404 /* Wait for pll_seq_done bit */ 405 try = 50; 406 while (--try) { 407 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 408 BLOCK0_XGXSSTATUS); 409 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 410 break; 411 msleep(20); 412 } 413 if (!try) { 414 /* PLL did not lock; give up */ 415 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 416 return -ETIMEDOUT; 417 } 418 419 dev_dbg(dev, "port%d initialized\n", port->portnum); 420 421 return 0; 422 } 423 424 /* SR PHY PLL0 registers */ 425 #define SR_PLL0_ACTRL6_MAGIC 0xa 426 427 /* SR PHY PLL1 registers */ 428 #define SR_PLL1_ACTRL2_MAGIC 0x32 429 #define SR_PLL1_ACTRL3_MAGIC 0x2 430 #define SR_PLL1_ACTRL4_MAGIC 0x3e8 431 432 static int brcm_sr_sata_init(struct brcm_sata_port *port) 433 { 434 struct brcm_sata_phy *priv = port->phy_priv; 435 struct device *dev = port->phy_priv->dev; 436 void __iomem *base = priv->phy_base; 437 unsigned int val, try; 438 439 /* Configure PHY PLL register bank 1 */ 440 val = SR_PLL1_ACTRL2_MAGIC; 441 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); 442 val = SR_PLL1_ACTRL3_MAGIC; 443 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); 444 val = SR_PLL1_ACTRL4_MAGIC; 445 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); 446 447 /* Configure PHY PLL register bank 0 */ 448 val = SR_PLL0_ACTRL6_MAGIC; 449 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val); 450 451 /* Wait for PHY PLL lock by polling pll_lock bit */ 452 try = 50; 453 do { 454 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 455 BLOCK0_XGXSSTATUS); 456 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 457 break; 458 msleep(20); 459 try--; 460 } while (try); 461 462 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) { 463 /* PLL did not lock; give up */ 464 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 465 return -ETIMEDOUT; 466 } 467 468 /* Invert Tx polarity */ 469 brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0, 470 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP); 471 472 /* Configure OOB control to handle 100MHz reference clock */ 473 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) | 474 (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) | 475 (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) | 476 (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT)); 477 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); 478 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) | 479 (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) | 480 (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT)); 481 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); 482 483 return 0; 484 } 485 486 static int brcm_dsl_sata_init(struct brcm_sata_port *port) 487 { 488 void __iomem *base = brcm_sata_pcb_base(port); 489 struct device *dev = port->phy_priv->dev; 490 unsigned int try; 491 u32 tmp; 492 493 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873); 494 495 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000); 496 497 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 498 0, 0x3089); 499 usleep_range(1000, 2000); 500 501 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 502 0, 0x3088); 503 usleep_range(1000, 2000); 504 505 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0, 506 0, 0x3000); 507 508 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0, 509 0, 0x3000); 510 usleep_range(1000, 2000); 511 512 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32); 513 514 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa); 515 516 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64); 517 usleep_range(1000, 2000); 518 519 /* Acquire PLL lock */ 520 try = 50; 521 while (try) { 522 tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 523 BLOCK0_XGXSSTATUS); 524 if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK) 525 break; 526 msleep(20); 527 try--; 528 }; 529 530 if (!try) { 531 /* PLL did not lock; give up */ 532 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 533 return -ETIMEDOUT; 534 } 535 536 dev_dbg(dev, "port%d initialized\n", port->portnum); 537 538 return 0; 539 } 540 541 static int brcm_sata_phy_init(struct phy *phy) 542 { 543 int rc; 544 struct brcm_sata_port *port = phy_get_drvdata(phy); 545 546 switch (port->phy_priv->version) { 547 case BRCM_SATA_PHY_STB_28NM: 548 case BRCM_SATA_PHY_STB_40NM: 549 rc = brcm_stb_sata_init(port); 550 break; 551 case BRCM_SATA_PHY_IPROC_NS2: 552 rc = brcm_ns2_sata_init(port); 553 break; 554 case BRCM_SATA_PHY_IPROC_NSP: 555 rc = brcm_nsp_sata_init(port); 556 break; 557 case BRCM_SATA_PHY_IPROC_SR: 558 rc = brcm_sr_sata_init(port); 559 break; 560 case BRCM_SATA_PHY_DSL_28NM: 561 rc = brcm_dsl_sata_init(port); 562 break; 563 default: 564 rc = -ENODEV; 565 } 566 567 return rc; 568 } 569 570 static void brcm_stb_sata_calibrate(struct brcm_sata_port *port) 571 { 572 void __iomem *base = brcm_sata_pcb_base(port); 573 u32 tmp = BIT(8); 574 575 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1, 576 ~tmp, tmp); 577 } 578 579 static int brcm_sata_phy_calibrate(struct phy *phy) 580 { 581 struct brcm_sata_port *port = phy_get_drvdata(phy); 582 int rc = -EOPNOTSUPP; 583 584 switch (port->phy_priv->version) { 585 case BRCM_SATA_PHY_STB_28NM: 586 case BRCM_SATA_PHY_STB_40NM: 587 brcm_stb_sata_calibrate(port); 588 rc = 0; 589 break; 590 default: 591 break; 592 } 593 594 return rc; 595 } 596 597 static const struct phy_ops phy_ops = { 598 .init = brcm_sata_phy_init, 599 .calibrate = brcm_sata_phy_calibrate, 600 .owner = THIS_MODULE, 601 }; 602 603 static const struct of_device_id brcm_sata_phy_of_match[] = { 604 { .compatible = "brcm,bcm7445-sata-phy", 605 .data = (void *)BRCM_SATA_PHY_STB_28NM }, 606 { .compatible = "brcm,bcm7425-sata-phy", 607 .data = (void *)BRCM_SATA_PHY_STB_40NM }, 608 { .compatible = "brcm,iproc-ns2-sata-phy", 609 .data = (void *)BRCM_SATA_PHY_IPROC_NS2 }, 610 { .compatible = "brcm,iproc-nsp-sata-phy", 611 .data = (void *)BRCM_SATA_PHY_IPROC_NSP }, 612 { .compatible = "brcm,iproc-sr-sata-phy", 613 .data = (void *)BRCM_SATA_PHY_IPROC_SR }, 614 { .compatible = "brcm,bcm63138-sata-phy", 615 .data = (void *)BRCM_SATA_PHY_DSL_28NM }, 616 {}, 617 }; 618 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match); 619 620 static int brcm_sata_phy_probe(struct platform_device *pdev) 621 { 622 const char *rxaeq_mode; 623 struct device *dev = &pdev->dev; 624 struct device_node *dn = dev->of_node, *child; 625 const struct of_device_id *of_id; 626 struct brcm_sata_phy *priv; 627 struct resource *res; 628 struct phy_provider *provider; 629 int ret, count = 0; 630 631 if (of_get_child_count(dn) == 0) 632 return -ENODEV; 633 634 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 635 if (!priv) 636 return -ENOMEM; 637 dev_set_drvdata(dev, priv); 638 priv->dev = dev; 639 640 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 641 priv->phy_base = devm_ioremap_resource(dev, res); 642 if (IS_ERR(priv->phy_base)) 643 return PTR_ERR(priv->phy_base); 644 645 of_id = of_match_node(brcm_sata_phy_of_match, dn); 646 if (of_id) 647 priv->version = (enum brcm_sata_phy_version)of_id->data; 648 else 649 priv->version = BRCM_SATA_PHY_STB_28NM; 650 651 if (priv->version == BRCM_SATA_PHY_IPROC_NS2) { 652 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 653 "phy-ctrl"); 654 priv->ctrl_base = devm_ioremap_resource(dev, res); 655 if (IS_ERR(priv->ctrl_base)) 656 return PTR_ERR(priv->ctrl_base); 657 } 658 659 for_each_available_child_of_node(dn, child) { 660 unsigned int id; 661 struct brcm_sata_port *port; 662 663 if (of_property_read_u32(child, "reg", &id)) { 664 dev_err(dev, "missing reg property in node %pOFn\n", 665 child); 666 ret = -EINVAL; 667 goto put_child; 668 } 669 670 if (id >= MAX_PORTS) { 671 dev_err(dev, "invalid reg: %u\n", id); 672 ret = -EINVAL; 673 goto put_child; 674 } 675 if (priv->phys[id].phy) { 676 dev_err(dev, "already registered port %u\n", id); 677 ret = -EINVAL; 678 goto put_child; 679 } 680 681 port = &priv->phys[id]; 682 port->portnum = id; 683 port->phy_priv = priv; 684 port->phy = devm_phy_create(dev, child, &phy_ops); 685 port->rxaeq_mode = RXAEQ_MODE_OFF; 686 if (!of_property_read_string(child, "brcm,rxaeq-mode", 687 &rxaeq_mode)) 688 port->rxaeq_mode = rxaeq_to_val(rxaeq_mode); 689 if (port->rxaeq_mode == RXAEQ_MODE_MANUAL) 690 of_property_read_u32(child, "brcm,rxaeq-value", 691 &port->rxaeq_val); 692 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc"); 693 if (IS_ERR(port->phy)) { 694 dev_err(dev, "failed to create PHY\n"); 695 ret = PTR_ERR(port->phy); 696 goto put_child; 697 } 698 699 phy_set_drvdata(port->phy, port); 700 count++; 701 } 702 703 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 704 if (IS_ERR(provider)) { 705 dev_err(dev, "could not register PHY provider\n"); 706 return PTR_ERR(provider); 707 } 708 709 dev_info(dev, "registered %d port(s)\n", count); 710 711 return 0; 712 put_child: 713 of_node_put(child); 714 return ret; 715 } 716 717 static struct platform_driver brcm_sata_phy_driver = { 718 .probe = brcm_sata_phy_probe, 719 .driver = { 720 .of_match_table = brcm_sata_phy_of_match, 721 .name = "brcm-sata-phy", 722 } 723 }; 724 module_platform_driver(brcm_sata_phy_driver); 725 726 MODULE_DESCRIPTION("Broadcom SATA PHY driver"); 727 MODULE_LICENSE("GPL"); 728 MODULE_AUTHOR("Marc Carino"); 729 MODULE_AUTHOR("Brian Norris"); 730 MODULE_ALIAS("platform:phy-brcm-sata"); 731