1 /* 2 * Meson8, Meson8b and GXBB USB2 PHY driver 3 * 4 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/reset.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/usb/of.h> 23 24 #define REG_CONFIG 0x00 25 #define REG_CONFIG_CLK_EN BIT(0) 26 #define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1) 27 #define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4) 28 #define REG_CONFIG_CLK_32k_ALTSEL BIT(15) 29 #define REG_CONFIG_TEST_TRIG BIT(31) 30 31 #define REG_CTRL 0x04 32 #define REG_CTRL_SOFT_PRST BIT(0) 33 #define REG_CTRL_SOFT_HRESET BIT(1) 34 #define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2) 35 #define REG_CTRL_CLK_DET_RST BIT(4) 36 #define REG_CTRL_INTR_SEL BIT(5) 37 #define REG_CTRL_CLK_DETECTED BIT(8) 38 #define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9) 39 #define REG_CTRL_SOF_TOGGLE_OUT BIT(10) 40 #define REG_CTRL_POWER_ON_RESET BIT(15) 41 #define REG_CTRL_SLEEPM BIT(16) 42 #define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17) 43 #define REG_CTRL_TX_BITSTUFF_ENN BIT(18) 44 #define REG_CTRL_COMMON_ON BIT(19) 45 #define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20) 46 #define REG_CTRL_REF_CLK_SEL_SHIFT 20 47 #define REG_CTRL_FSEL_MASK GENMASK(24, 22) 48 #define REG_CTRL_FSEL_SHIFT 22 49 #define REG_CTRL_PORT_RESET BIT(25) 50 #define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26) 51 52 #define REG_ENDP_INTR 0x08 53 54 /* bits [31:26], [24:21] and [15:3] seem to be read-only */ 55 #define REG_ADP_BC 0x0c 56 #define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0) 57 #define REG_ADP_BC_VBUS_VLD_EXT BIT(1) 58 #define REG_ADP_BC_OTG_DISABLE BIT(2) 59 #define REG_ADP_BC_ID_PULLUP BIT(3) 60 #define REG_ADP_BC_DRV_VBUS BIT(4) 61 #define REG_ADP_BC_ADP_PRB_EN BIT(5) 62 #define REG_ADP_BC_ADP_DISCHARGE BIT(6) 63 #define REG_ADP_BC_ADP_CHARGE BIT(7) 64 #define REG_ADP_BC_SESS_END BIT(8) 65 #define REG_ADP_BC_DEVICE_SESS_VLD BIT(9) 66 #define REG_ADP_BC_B_VALID BIT(10) 67 #define REG_ADP_BC_A_VALID BIT(11) 68 #define REG_ADP_BC_ID_DIG BIT(12) 69 #define REG_ADP_BC_VBUS_VALID BIT(13) 70 #define REG_ADP_BC_ADP_PROBE BIT(14) 71 #define REG_ADP_BC_ADP_SENSE BIT(15) 72 #define REG_ADP_BC_ACA_ENABLE BIT(16) 73 #define REG_ADP_BC_DCD_ENABLE BIT(17) 74 #define REG_ADP_BC_VDAT_DET_EN_B BIT(18) 75 #define REG_ADP_BC_VDAT_SRC_EN_B BIT(19) 76 #define REG_ADP_BC_CHARGE_SEL BIT(20) 77 #define REG_ADP_BC_CHARGE_DETECT BIT(21) 78 #define REG_ADP_BC_ACA_PIN_RANGE_C BIT(22) 79 #define REG_ADP_BC_ACA_PIN_RANGE_B BIT(23) 80 #define REG_ADP_BC_ACA_PIN_RANGE_A BIT(24) 81 #define REG_ADP_BC_ACA_PIN_GND BIT(25) 82 #define REG_ADP_BC_ACA_PIN_FLOAT BIT(26) 83 84 #define REG_DBG_UART 0x10 85 86 #define REG_TEST 0x14 87 #define REG_TEST_DATA_IN_MASK GENMASK(3, 0) 88 #define REG_TEST_EN_MASK GENMASK(7, 4) 89 #define REG_TEST_ADDR_MASK GENMASK(11, 8) 90 #define REG_TEST_DATA_OUT_SEL BIT(12) 91 #define REG_TEST_CLK BIT(13) 92 #define REG_TEST_VA_TEST_EN_B_MASK GENMASK(15, 14) 93 #define REG_TEST_DATA_OUT_MASK GENMASK(19, 16) 94 #define REG_TEST_DISABLE_ID_PULLUP BIT(20) 95 96 #define REG_TUNE 0x18 97 #define REG_TUNE_TX_RES_TUNE_MASK GENMASK(1, 0) 98 #define REG_TUNE_TX_HSXV_TUNE_MASK GENMASK(3, 2) 99 #define REG_TUNE_TX_VREF_TUNE_MASK GENMASK(7, 4) 100 #define REG_TUNE_TX_RISE_TUNE_MASK GENMASK(9, 8) 101 #define REG_TUNE_TX_PREEMP_PULSE_TUNE BIT(10) 102 #define REG_TUNE_TX_PREEMP_AMP_TUNE_MASK GENMASK(12, 11) 103 #define REG_TUNE_TX_FSLS_TUNE_MASK GENMASK(16, 13) 104 #define REG_TUNE_SQRX_TUNE_MASK GENMASK(19, 17) 105 #define REG_TUNE_OTG_TUNE GENMASK(22, 20) 106 #define REG_TUNE_COMP_DIS_TUNE GENMASK(25, 23) 107 #define REG_TUNE_HOST_DM_PULLDOWN BIT(26) 108 #define REG_TUNE_HOST_DP_PULLDOWN BIT(27) 109 110 #define RESET_COMPLETE_TIME 500 111 #define ACA_ENABLE_COMPLETE_TIME 50 112 113 struct phy_meson8b_usb2_priv { 114 void __iomem *regs; 115 enum usb_dr_mode dr_mode; 116 struct clk *clk_usb_general; 117 struct clk *clk_usb; 118 struct reset_control *reset; 119 }; 120 121 static u32 phy_meson8b_usb2_read(struct phy_meson8b_usb2_priv *phy_priv, 122 u32 reg) 123 { 124 return readl(phy_priv->regs + reg); 125 } 126 127 static void phy_meson8b_usb2_mask_bits(struct phy_meson8b_usb2_priv *phy_priv, 128 u32 reg, u32 mask, u32 value) 129 { 130 u32 data; 131 132 data = phy_meson8b_usb2_read(phy_priv, reg); 133 data &= ~mask; 134 data |= (value & mask); 135 136 writel(data, phy_priv->regs + reg); 137 } 138 139 static int phy_meson8b_usb2_power_on(struct phy *phy) 140 { 141 struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy); 142 int ret; 143 144 if (!IS_ERR_OR_NULL(priv->reset)) { 145 ret = reset_control_reset(priv->reset); 146 if (ret) { 147 dev_err(&phy->dev, "Failed to trigger USB reset\n"); 148 return ret; 149 } 150 } 151 152 ret = clk_prepare_enable(priv->clk_usb_general); 153 if (ret) { 154 dev_err(&phy->dev, "Failed to enable USB general clock\n"); 155 return ret; 156 } 157 158 ret = clk_prepare_enable(priv->clk_usb); 159 if (ret) { 160 dev_err(&phy->dev, "Failed to enable USB DDR clock\n"); 161 clk_disable_unprepare(priv->clk_usb_general); 162 return ret; 163 } 164 165 phy_meson8b_usb2_mask_bits(priv, REG_CONFIG, REG_CONFIG_CLK_32k_ALTSEL, 166 REG_CONFIG_CLK_32k_ALTSEL); 167 168 phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_REF_CLK_SEL_MASK, 169 0x2 << REG_CTRL_REF_CLK_SEL_SHIFT); 170 171 phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_FSEL_MASK, 172 0x5 << REG_CTRL_FSEL_SHIFT); 173 174 /* reset the PHY */ 175 phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_POWER_ON_RESET, 176 REG_CTRL_POWER_ON_RESET); 177 udelay(RESET_COMPLETE_TIME); 178 phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_POWER_ON_RESET, 0); 179 udelay(RESET_COMPLETE_TIME); 180 181 phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_SOF_TOGGLE_OUT, 182 REG_CTRL_SOF_TOGGLE_OUT); 183 184 if (priv->dr_mode == USB_DR_MODE_HOST) { 185 phy_meson8b_usb2_mask_bits(priv, REG_ADP_BC, 186 REG_ADP_BC_ACA_ENABLE, 187 REG_ADP_BC_ACA_ENABLE); 188 189 udelay(ACA_ENABLE_COMPLETE_TIME); 190 191 if (phy_meson8b_usb2_read(priv, REG_ADP_BC) & 192 REG_ADP_BC_ACA_PIN_FLOAT) { 193 dev_warn(&phy->dev, "USB ID detect failed!\n"); 194 clk_disable_unprepare(priv->clk_usb); 195 clk_disable_unprepare(priv->clk_usb_general); 196 return -EINVAL; 197 } 198 } 199 200 return 0; 201 } 202 203 static int phy_meson8b_usb2_power_off(struct phy *phy) 204 { 205 struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy); 206 207 clk_disable_unprepare(priv->clk_usb); 208 clk_disable_unprepare(priv->clk_usb_general); 209 210 return 0; 211 } 212 213 static const struct phy_ops phy_meson8b_usb2_ops = { 214 .power_on = phy_meson8b_usb2_power_on, 215 .power_off = phy_meson8b_usb2_power_off, 216 .owner = THIS_MODULE, 217 }; 218 219 static int phy_meson8b_usb2_probe(struct platform_device *pdev) 220 { 221 struct phy_meson8b_usb2_priv *priv; 222 struct resource *res; 223 struct phy *phy; 224 struct phy_provider *phy_provider; 225 226 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 227 if (!priv) 228 return -ENOMEM; 229 230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 231 priv->regs = devm_ioremap_resource(&pdev->dev, res); 232 if (IS_ERR(priv->regs)) 233 return PTR_ERR(priv->regs); 234 235 priv->clk_usb_general = devm_clk_get(&pdev->dev, "usb_general"); 236 if (IS_ERR(priv->clk_usb_general)) 237 return PTR_ERR(priv->clk_usb_general); 238 239 priv->clk_usb = devm_clk_get(&pdev->dev, "usb"); 240 if (IS_ERR(priv->clk_usb)) 241 return PTR_ERR(priv->clk_usb); 242 243 priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL); 244 if (PTR_ERR(priv->reset) == -EPROBE_DEFER) 245 return PTR_ERR(priv->reset); 246 247 priv->dr_mode = of_usb_get_dr_mode_by_phy(pdev->dev.of_node, -1); 248 if (priv->dr_mode == USB_DR_MODE_UNKNOWN) { 249 dev_err(&pdev->dev, 250 "missing dual role configuration of the controller\n"); 251 return -EINVAL; 252 } 253 254 phy = devm_phy_create(&pdev->dev, NULL, &phy_meson8b_usb2_ops); 255 if (IS_ERR(phy)) { 256 dev_err(&pdev->dev, "failed to create PHY\n"); 257 return PTR_ERR(phy); 258 } 259 260 phy_set_drvdata(phy, priv); 261 262 phy_provider = 263 devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); 264 265 return PTR_ERR_OR_ZERO(phy_provider); 266 } 267 268 static const struct of_device_id phy_meson8b_usb2_of_match[] = { 269 { .compatible = "amlogic,meson8-usb2-phy", }, 270 { .compatible = "amlogic,meson8b-usb2-phy", }, 271 { .compatible = "amlogic,meson-gxbb-usb2-phy", }, 272 { }, 273 }; 274 MODULE_DEVICE_TABLE(of, phy_meson8b_usb2_of_match); 275 276 static struct platform_driver phy_meson8b_usb2_driver = { 277 .probe = phy_meson8b_usb2_probe, 278 .driver = { 279 .name = "phy-meson-usb2", 280 .of_match_table = phy_meson8b_usb2_of_match, 281 }, 282 }; 283 module_platform_driver(phy_meson8b_usb2_driver); 284 285 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 286 MODULE_DESCRIPTION("Meson8, Meson8b and GXBB USB2 PHY driver"); 287 MODULE_LICENSE("GPL"); 288