15d134abfSMaxime Ripard // SPDX-License-Identifier: GPL-2.0+
25d134abfSMaxime Ripard /*
35d134abfSMaxime Ripard * Copyright (c) 2016 Allwinnertech Co., Ltd.
45d134abfSMaxime Ripard * Copyright (C) 2017-2018 Bootlin
55d134abfSMaxime Ripard *
65d134abfSMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com>
75d134abfSMaxime Ripard */
85d134abfSMaxime Ripard
95d134abfSMaxime Ripard #include <linux/bitops.h>
105d134abfSMaxime Ripard #include <linux/clk.h>
115d134abfSMaxime Ripard #include <linux/module.h>
125d134abfSMaxime Ripard #include <linux/of_address.h>
135d134abfSMaxime Ripard #include <linux/platform_device.h>
145d134abfSMaxime Ripard #include <linux/regmap.h>
155d134abfSMaxime Ripard #include <linux/reset.h>
165d134abfSMaxime Ripard
175d134abfSMaxime Ripard #include <linux/phy/phy.h>
185d134abfSMaxime Ripard #include <linux/phy/phy-mipi-dphy.h>
195d134abfSMaxime Ripard
205d134abfSMaxime Ripard #define SUN6I_DPHY_GCTL_REG 0x00
215d134abfSMaxime Ripard #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
225d134abfSMaxime Ripard #define SUN6I_DPHY_GCTL_EN BIT(0)
235d134abfSMaxime Ripard
245d134abfSMaxime Ripard #define SUN6I_DPHY_TX_CTL_REG 0x04
255d134abfSMaxime Ripard #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
265d134abfSMaxime Ripard
2774d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_CTL_REG 0x08
2874d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
2974d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
3074d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
3174d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
3274d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
3374d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
3474d0cd47SPaul Kocialkowski
355d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME0_REG 0x10
365d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24)
375d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
385d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff)
395d134abfSMaxime Ripard
405d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME1_REG 0x14
415d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24)
425d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16)
435d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8)
445d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff)
455d134abfSMaxime Ripard
465d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME2_REG 0x18
475d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff)
485d134abfSMaxime Ripard
495d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME3_REG 0x1c
505d134abfSMaxime Ripard
515d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME4_REG 0x20
525d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
535d134abfSMaxime Ripard #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
545d134abfSMaxime Ripard
5574d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME0_REG 0x30
5674d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
5774d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
5874d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
5974d0cd47SPaul Kocialkowski
6074d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME1_REG 0x34
6174d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
6274d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xfffff)
6374d0cd47SPaul Kocialkowski
6474d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME2_REG 0x38
6574d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
6674d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
6774d0cd47SPaul Kocialkowski
6874d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME3_REG 0x40
6974d0cd47SPaul Kocialkowski #define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0xffff) << 16)
7074d0cd47SPaul Kocialkowski
715d134abfSMaxime Ripard #define SUN6I_DPHY_ANA0_REG 0x4c
725d134abfSMaxime Ripard #define SUN6I_DPHY_ANA0_REG_PWS BIT(31)
73*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_PWEND BIT(30)
74*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_PWENC BIT(29)
755d134abfSMaxime Ripard #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
765d134abfSMaxime Ripard #define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24)
77*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_SRXDT(n) (((n) & 0xf) << 20)
78*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_SRXCK(n) (((n) & 0xf) << 16)
79*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_SDIV2 BIT(15)
805d134abfSMaxime Ripard #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
815d134abfSMaxime Ripard #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
82*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_PLR(n) (((n) & 0xf) << 4)
8374d0cd47SPaul Kocialkowski #define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
84*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_RSD BIT(1)
85*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA0_REG_SELSCK BIT(0)
865d134abfSMaxime Ripard
875d134abfSMaxime Ripard #define SUN6I_DPHY_ANA1_REG 0x50
885d134abfSMaxime Ripard #define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31)
895d134abfSMaxime Ripard #define SUN6I_DPHY_ANA1_REG_CSMPS(n) (((n) & 3) << 28)
905d134abfSMaxime Ripard #define SUN6I_DPHY_ANA1_REG_SVTT(n) (((n) & 0xf) << 24)
915d134abfSMaxime Ripard
925d134abfSMaxime Ripard #define SUN6I_DPHY_ANA2_REG 0x54
935d134abfSMaxime Ripard #define SUN6I_DPHY_ANA2_EN_P2S_CPU(n) (((n) & 0xf) << 24)
945d134abfSMaxime Ripard #define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK GENMASK(27, 24)
955d134abfSMaxime Ripard #define SUN6I_DPHY_ANA2_EN_CK_CPU BIT(4)
965d134abfSMaxime Ripard #define SUN6I_DPHY_ANA2_REG_ENIB BIT(1)
975d134abfSMaxime Ripard
985d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_REG 0x58
995d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_EN_VTTD(n) (((n) & 0xf) << 28)
1005d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_EN_VTTD_MASK GENMASK(31, 28)
1015d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_EN_VTTC BIT(27)
1025d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_EN_DIV BIT(26)
1035d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_EN_LDOC BIT(25)
1045d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_EN_LDOD BIT(24)
1055d134abfSMaxime Ripard #define SUN6I_DPHY_ANA3_EN_LDOR BIT(18)
1065d134abfSMaxime Ripard
1075d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG 0x5c
108*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA4_REG_EN_MIPI BIT(31)
109*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA4_REG_EN_COMTEST BIT(30)
110*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA4_REG_COMTEST(n) (((n) & 3) << 28)
111*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA4_REG_IB(n) (((n) & 3) << 25)
1125d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_DMPLVC BIT(24)
1135d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_DMPLVD(n) (((n) & 0xf) << 20)
114*4d0c2165SSamuel Holland #define SUN6I_DPHY_ANA4_REG_VTT_SET(n) (((n) & 0x7) << 17)
1155d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_CKDV(n) (((n) & 0x1f) << 12)
1165d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_TMSC(n) (((n) & 3) << 10)
1175d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_TMSD(n) (((n) & 3) << 8)
1185d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_TXDNSC(n) (((n) & 3) << 6)
1195d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_TXDNSD(n) (((n) & 3) << 4)
1205d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_TXPUSC(n) (((n) & 3) << 2)
1215d134abfSMaxime Ripard #define SUN6I_DPHY_ANA4_REG_TXPUSD(n) ((n) & 3)
1225d134abfSMaxime Ripard
1235d134abfSMaxime Ripard #define SUN6I_DPHY_DBG5_REG 0xf4
1245d134abfSMaxime Ripard
125*4d0c2165SSamuel Holland #define SUN50I_DPHY_TX_SLEW_REG0 0xf8
126*4d0c2165SSamuel Holland #define SUN50I_DPHY_TX_SLEW_REG1 0xfc
127*4d0c2165SSamuel Holland #define SUN50I_DPHY_TX_SLEW_REG2 0x100
128*4d0c2165SSamuel Holland
129*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0 0x104
130*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_CP36_EN BIT(23)
131*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_LDO_EN BIT(22)
132*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_EN_LVS BIT(21)
133*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_PLL_EN BIT(20)
134*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_P(n) (((n) & 0xf) << 16)
135*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_N(n) (((n) & 0xff) << 8)
136*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_NDET BIT(7)
137*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_TDIV BIT(6)
138*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_M0(n) (((n) & 3) << 4)
139*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG0_M1(n) ((n) & 0xf)
140*4d0c2165SSamuel Holland
141*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1 0x108
142*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n) (((n) & 3) << 14)
143*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_LOCKMDSEL BIT(13)
144*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_LOCKDET_EN BIT(12)
145*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_VSETA(n) (((n) & 0x7) << 9)
146*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_VSETD(n) (((n) & 0x7) << 6)
147*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_LPF_SW BIT(5)
148*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_ICP_SEL(n) (((n) & 3) << 3)
149*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n) (((n) & 3) << 1)
150*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG1_TEST_EN BIT(0)
151*4d0c2165SSamuel Holland
152*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG2 0x10c
153*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG2_SDM_EN BIT(31)
154*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG2_FF_EN BIT(30)
155*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG2_SS_EN BIT(29)
156*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG2_SS_FRAC(n) (((n) & 0x1ff) << 20)
157*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG2_SS_INT(n) (((n) & 0xff) << 12)
158*4d0c2165SSamuel Holland #define SUN50I_DPHY_PLL_REG2_FRAC(n) ((n) & 0xfff)
159*4d0c2165SSamuel Holland
160*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG0 0x110
161*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO BIT(5)
162*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8 BIT(4)
163*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG0_EN_MIPI BIT(3)
164*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG0_EN_LVDS BIT(2)
165*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO BIT(1)
166*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0)
167*4d0c2165SSamuel Holland
168*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG1 0x114
169*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4)
170*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7)
171*4d0c2165SSamuel Holland
172*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG2 0x118
173*4d0c2165SSamuel Holland #define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff)
174*4d0c2165SSamuel Holland
17574d0cd47SPaul Kocialkowski enum sun6i_dphy_direction {
17674d0cd47SPaul Kocialkowski SUN6I_DPHY_DIRECTION_TX,
17774d0cd47SPaul Kocialkowski SUN6I_DPHY_DIRECTION_RX,
17874d0cd47SPaul Kocialkowski };
17974d0cd47SPaul Kocialkowski
1803fd490a7SSamuel Holland struct sun6i_dphy;
1813fd490a7SSamuel Holland
182a709ae51SSamuel Holland struct sun6i_dphy_variant {
1833fd490a7SSamuel Holland void (*tx_power_on)(struct sun6i_dphy *dphy);
184a709ae51SSamuel Holland bool rx_supported;
185a709ae51SSamuel Holland };
186a709ae51SSamuel Holland
1875d134abfSMaxime Ripard struct sun6i_dphy {
1885d134abfSMaxime Ripard struct clk *bus_clk;
1895d134abfSMaxime Ripard struct clk *mod_clk;
1905d134abfSMaxime Ripard struct regmap *regs;
1915d134abfSMaxime Ripard struct reset_control *reset;
1925d134abfSMaxime Ripard
1935d134abfSMaxime Ripard struct phy *phy;
1945d134abfSMaxime Ripard struct phy_configure_opts_mipi_dphy config;
19574d0cd47SPaul Kocialkowski
196a709ae51SSamuel Holland const struct sun6i_dphy_variant *variant;
19774d0cd47SPaul Kocialkowski enum sun6i_dphy_direction direction;
1985d134abfSMaxime Ripard };
1995d134abfSMaxime Ripard
sun6i_dphy_init(struct phy * phy)2005d134abfSMaxime Ripard static int sun6i_dphy_init(struct phy *phy)
2015d134abfSMaxime Ripard {
2025d134abfSMaxime Ripard struct sun6i_dphy *dphy = phy_get_drvdata(phy);
2035d134abfSMaxime Ripard
2045d134abfSMaxime Ripard reset_control_deassert(dphy->reset);
2055d134abfSMaxime Ripard clk_prepare_enable(dphy->mod_clk);
2065d134abfSMaxime Ripard clk_set_rate_exclusive(dphy->mod_clk, 150000000);
2075d134abfSMaxime Ripard
2085d134abfSMaxime Ripard return 0;
2095d134abfSMaxime Ripard }
2105d134abfSMaxime Ripard
sun6i_dphy_configure(struct phy * phy,union phy_configure_opts * opts)2115d134abfSMaxime Ripard static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
2125d134abfSMaxime Ripard {
2135d134abfSMaxime Ripard struct sun6i_dphy *dphy = phy_get_drvdata(phy);
2145d134abfSMaxime Ripard int ret;
2155d134abfSMaxime Ripard
2165d134abfSMaxime Ripard ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
2175d134abfSMaxime Ripard if (ret)
2185d134abfSMaxime Ripard return ret;
2195d134abfSMaxime Ripard
2205d134abfSMaxime Ripard memcpy(&dphy->config, opts, sizeof(dphy->config));
2215d134abfSMaxime Ripard
2225d134abfSMaxime Ripard return 0;
2235d134abfSMaxime Ripard }
2245d134abfSMaxime Ripard
sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy * dphy)2253fd490a7SSamuel Holland static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
2265d134abfSMaxime Ripard {
2275d134abfSMaxime Ripard u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
2285d134abfSMaxime Ripard
2295d134abfSMaxime Ripard regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
2305d134abfSMaxime Ripard SUN6I_DPHY_ANA0_REG_PWS |
2315d134abfSMaxime Ripard SUN6I_DPHY_ANA0_REG_DMPC |
2325d134abfSMaxime Ripard SUN6I_DPHY_ANA0_REG_SLV(7) |
2335d134abfSMaxime Ripard SUN6I_DPHY_ANA0_REG_DMPD(lanes_mask) |
2345d134abfSMaxime Ripard SUN6I_DPHY_ANA0_REG_DEN(lanes_mask));
2355d134abfSMaxime Ripard
2365d134abfSMaxime Ripard regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
2375d134abfSMaxime Ripard SUN6I_DPHY_ANA1_REG_CSMPS(1) |
2385d134abfSMaxime Ripard SUN6I_DPHY_ANA1_REG_SVTT(7));
2395d134abfSMaxime Ripard
2405d134abfSMaxime Ripard regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
2415d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_CKDV(1) |
2425d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_TMSC(1) |
2435d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_TMSD(1) |
2445d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_TXDNSC(1) |
2455d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_TXDNSD(1) |
2465d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_TXPUSC(1) |
2475d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_TXPUSD(1) |
2485d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_DMPLVC |
2495d134abfSMaxime Ripard SUN6I_DPHY_ANA4_REG_DMPLVD(lanes_mask));
2505d134abfSMaxime Ripard
2515d134abfSMaxime Ripard regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
2525d134abfSMaxime Ripard SUN6I_DPHY_ANA2_REG_ENIB);
2535d134abfSMaxime Ripard udelay(5);
2545d134abfSMaxime Ripard
2555d134abfSMaxime Ripard regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
2565d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_LDOR |
2575d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_LDOC |
2585d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_LDOD);
2595d134abfSMaxime Ripard udelay(1);
2603fd490a7SSamuel Holland }
2613fd490a7SSamuel Holland
sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy * dphy)262*4d0c2165SSamuel Holland static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
263*4d0c2165SSamuel Holland {
264*4d0c2165SSamuel Holland unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
265*4d0c2165SSamuel Holland unsigned int div, n;
266*4d0c2165SSamuel Holland
267*4d0c2165SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
268*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_IB(2) |
269*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
270*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
271*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_CKDV(3) |
272*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_TMSD(1) |
273*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_TMSC(1) |
274*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
275*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
276*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
277*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_TXDNSC(3));
278*4d0c2165SSamuel Holland
279*4d0c2165SSamuel Holland regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
280*4d0c2165SSamuel Holland SUN6I_DPHY_ANA2_EN_CK_CPU,
281*4d0c2165SSamuel Holland SUN6I_DPHY_ANA2_EN_CK_CPU);
282*4d0c2165SSamuel Holland
283*4d0c2165SSamuel Holland regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
284*4d0c2165SSamuel Holland SUN6I_DPHY_ANA2_REG_ENIB,
285*4d0c2165SSamuel Holland SUN6I_DPHY_ANA2_REG_ENIB);
286*4d0c2165SSamuel Holland
287*4d0c2165SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
288*4d0c2165SSamuel Holland SUN6I_DPHY_ANA3_EN_LDOR |
289*4d0c2165SSamuel Holland SUN6I_DPHY_ANA3_EN_LDOC |
290*4d0c2165SSamuel Holland SUN6I_DPHY_ANA3_EN_LDOD);
291*4d0c2165SSamuel Holland
292*4d0c2165SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
293*4d0c2165SSamuel Holland SUN6I_DPHY_ANA0_REG_PLR(4) |
294*4d0c2165SSamuel Holland SUN6I_DPHY_ANA0_REG_SFB(1));
295*4d0c2165SSamuel Holland
296*4d0c2165SSamuel Holland regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
297*4d0c2165SSamuel Holland SUN50I_COMBO_PHY_REG0_EN_CP);
298*4d0c2165SSamuel Holland
299*4d0c2165SSamuel Holland /* Choose a divider to limit the VCO frequency to around 2 GHz. */
300*4d0c2165SSamuel Holland div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
301*4d0c2165SSamuel Holland n = mipi_symbol_rate * div / 24000000;
302*4d0c2165SSamuel Holland
303*4d0c2165SSamuel Holland regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
304*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_CP36_EN |
305*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_LDO_EN |
306*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_EN_LVS |
307*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_PLL_EN |
308*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_NDET |
309*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
310*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_N(n) |
311*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
312*4d0c2165SSamuel Holland SUN50I_DPHY_PLL_REG0_M1(2));
313*4d0c2165SSamuel Holland
314*4d0c2165SSamuel Holland /* Disable sigma-delta modulation. */
315*4d0c2165SSamuel Holland regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
316*4d0c2165SSamuel Holland
317*4d0c2165SSamuel Holland regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
318*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_EN_MIPI,
319*4d0c2165SSamuel Holland SUN6I_DPHY_ANA4_REG_EN_MIPI);
320*4d0c2165SSamuel Holland
321*4d0c2165SSamuel Holland regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
322*4d0c2165SSamuel Holland SUN50I_COMBO_PHY_REG0_EN_MIPI |
323*4d0c2165SSamuel Holland SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
324*4d0c2165SSamuel Holland SUN50I_COMBO_PHY_REG0_EN_MIPI |
325*4d0c2165SSamuel Holland SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
326*4d0c2165SSamuel Holland
327*4d0c2165SSamuel Holland regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
328*4d0c2165SSamuel Holland SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
329*4d0c2165SSamuel Holland udelay(1);
330*4d0c2165SSamuel Holland }
331*4d0c2165SSamuel Holland
sun6i_dphy_tx_power_on(struct sun6i_dphy * dphy)3323fd490a7SSamuel Holland static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
3333fd490a7SSamuel Holland {
3343fd490a7SSamuel Holland u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
3353fd490a7SSamuel Holland
3363fd490a7SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
3373fd490a7SSamuel Holland SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
3383fd490a7SSamuel Holland
3393fd490a7SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
3403fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
3413fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
3423fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
3433fd490a7SSamuel Holland
3443fd490a7SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
3453fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
3463fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
3473fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
3483fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME1_CLK_POST(10));
3493fd490a7SSamuel Holland
3503fd490a7SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
3513fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
3523fd490a7SSamuel Holland
3533fd490a7SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
3543fd490a7SSamuel Holland
3553fd490a7SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
3563fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
3573fd490a7SSamuel Holland SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
3583fd490a7SSamuel Holland
3593fd490a7SSamuel Holland dphy->variant->tx_power_on(dphy);
3605d134abfSMaxime Ripard
3615d134abfSMaxime Ripard regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
3625d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_VTTC |
3635d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_VTTD_MASK,
3645d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_VTTC |
3655d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_VTTD(lanes_mask));
3665d134abfSMaxime Ripard udelay(1);
3675d134abfSMaxime Ripard
3685d134abfSMaxime Ripard regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
3695d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_DIV,
3705d134abfSMaxime Ripard SUN6I_DPHY_ANA3_EN_DIV);
3715d134abfSMaxime Ripard udelay(1);
3725d134abfSMaxime Ripard
3735d134abfSMaxime Ripard regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
3745d134abfSMaxime Ripard SUN6I_DPHY_ANA2_EN_CK_CPU,
3755d134abfSMaxime Ripard SUN6I_DPHY_ANA2_EN_CK_CPU);
3765d134abfSMaxime Ripard udelay(1);
3775d134abfSMaxime Ripard
3785d134abfSMaxime Ripard regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
3795d134abfSMaxime Ripard SUN6I_DPHY_ANA1_REG_VTTMODE,
3805d134abfSMaxime Ripard SUN6I_DPHY_ANA1_REG_VTTMODE);
3815d134abfSMaxime Ripard
3825d134abfSMaxime Ripard regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
3835d134abfSMaxime Ripard SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
3845d134abfSMaxime Ripard SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
3855d134abfSMaxime Ripard
386cb7f49a3SSamuel Holland regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
387cb7f49a3SSamuel Holland SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
388cb7f49a3SSamuel Holland SUN6I_DPHY_GCTL_EN);
389cb7f49a3SSamuel Holland
3905d134abfSMaxime Ripard return 0;
3915d134abfSMaxime Ripard }
3925d134abfSMaxime Ripard
sun6i_dphy_rx_power_on(struct sun6i_dphy * dphy)39374d0cd47SPaul Kocialkowski static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
39474d0cd47SPaul Kocialkowski {
39574d0cd47SPaul Kocialkowski /* Physical clock rate is actually half of symbol rate with DDR. */
39674d0cd47SPaul Kocialkowski unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
39774d0cd47SPaul Kocialkowski unsigned long dphy_clk_rate;
39874d0cd47SPaul Kocialkowski unsigned int rx_dly;
39974d0cd47SPaul Kocialkowski unsigned int lprst_dly;
40074d0cd47SPaul Kocialkowski u32 value;
40174d0cd47SPaul Kocialkowski
40274d0cd47SPaul Kocialkowski dphy_clk_rate = clk_get_rate(dphy->mod_clk);
40374d0cd47SPaul Kocialkowski if (!dphy_clk_rate)
40474d0cd47SPaul Kocialkowski return -EINVAL;
40574d0cd47SPaul Kocialkowski
40674d0cd47SPaul Kocialkowski /* Hardcoded timing parameters from the Allwinner BSP. */
40774d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
40874d0cd47SPaul Kocialkowski SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
40974d0cd47SPaul Kocialkowski SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
41074d0cd47SPaul Kocialkowski SUN6I_DPHY_RX_TIME0_LP_RX(255));
41174d0cd47SPaul Kocialkowski
41274d0cd47SPaul Kocialkowski /*
41374d0cd47SPaul Kocialkowski * Formula from the Allwinner BSP, with hardcoded coefficients
41474d0cd47SPaul Kocialkowski * (probably internal divider/multiplier).
41574d0cd47SPaul Kocialkowski */
41674d0cd47SPaul Kocialkowski rx_dly = 8 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 8));
41774d0cd47SPaul Kocialkowski
41874d0cd47SPaul Kocialkowski /*
41974d0cd47SPaul Kocialkowski * The Allwinner BSP has an alternative formula for LP_RX_ULPS_WP:
42074d0cd47SPaul Kocialkowski * lp_ulps_wp_cnt = lp_ulps_wp_ms * lp_clk / 1000
42174d0cd47SPaul Kocialkowski * but does not use it and hardcodes 255 instead.
42274d0cd47SPaul Kocialkowski */
42374d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME1_REG,
42474d0cd47SPaul Kocialkowski SUN6I_DPHY_RX_TIME1_RX_DLY(rx_dly) |
42574d0cd47SPaul Kocialkowski SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(255));
42674d0cd47SPaul Kocialkowski
42774d0cd47SPaul Kocialkowski /* HS_RX_ANA0 value is hardcoded in the Allwinner BSP. */
42874d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME2_REG,
42974d0cd47SPaul Kocialkowski SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(4));
43074d0cd47SPaul Kocialkowski
43174d0cd47SPaul Kocialkowski /*
43274d0cd47SPaul Kocialkowski * Formula from the Allwinner BSP, with hardcoded coefficients
43374d0cd47SPaul Kocialkowski * (probably internal divider/multiplier).
43474d0cd47SPaul Kocialkowski */
43574d0cd47SPaul Kocialkowski lprst_dly = 4 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 2));
43674d0cd47SPaul Kocialkowski
43774d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME3_REG,
43874d0cd47SPaul Kocialkowski SUN6I_DPHY_RX_TIME3_LPRST_DLY(lprst_dly));
43974d0cd47SPaul Kocialkowski
44074d0cd47SPaul Kocialkowski /* Analog parameters are hardcoded in the Allwinner BSP. */
44174d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
44274d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA0_REG_PWS |
44374d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA0_REG_SLV(7) |
44474d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA0_REG_SFB(2));
44574d0cd47SPaul Kocialkowski
44674d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
44774d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA1_REG_SVTT(4));
44874d0cd47SPaul Kocialkowski
44974d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
45074d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA4_REG_DMPLVC |
45174d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA4_REG_DMPLVD(1));
45274d0cd47SPaul Kocialkowski
45374d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
45474d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA2_REG_ENIB);
45574d0cd47SPaul Kocialkowski
45674d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
45774d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA3_EN_LDOR |
45874d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA3_EN_LDOC |
45974d0cd47SPaul Kocialkowski SUN6I_DPHY_ANA3_EN_LDOD);
46074d0cd47SPaul Kocialkowski
46174d0cd47SPaul Kocialkowski /*
46274d0cd47SPaul Kocialkowski * Delay comes from the Allwinner BSP, likely for internal regulator
46374d0cd47SPaul Kocialkowski * ramp-up.
46474d0cd47SPaul Kocialkowski */
46574d0cd47SPaul Kocialkowski udelay(3);
46674d0cd47SPaul Kocialkowski
46774d0cd47SPaul Kocialkowski value = SUN6I_DPHY_RX_CTL_EN_DBC | SUN6I_DPHY_RX_CTL_RX_CLK_FORCE;
46874d0cd47SPaul Kocialkowski
46974d0cd47SPaul Kocialkowski /*
47074d0cd47SPaul Kocialkowski * Rx data lane force-enable bits are used as regular RX enable by the
47174d0cd47SPaul Kocialkowski * Allwinner BSP.
47274d0cd47SPaul Kocialkowski */
47374d0cd47SPaul Kocialkowski if (dphy->config.lanes >= 1)
47474d0cd47SPaul Kocialkowski value |= SUN6I_DPHY_RX_CTL_RX_D0_FORCE;
47574d0cd47SPaul Kocialkowski if (dphy->config.lanes >= 2)
47674d0cd47SPaul Kocialkowski value |= SUN6I_DPHY_RX_CTL_RX_D1_FORCE;
47774d0cd47SPaul Kocialkowski if (dphy->config.lanes >= 3)
47874d0cd47SPaul Kocialkowski value |= SUN6I_DPHY_RX_CTL_RX_D2_FORCE;
47974d0cd47SPaul Kocialkowski if (dphy->config.lanes == 4)
48074d0cd47SPaul Kocialkowski value |= SUN6I_DPHY_RX_CTL_RX_D3_FORCE;
48174d0cd47SPaul Kocialkowski
48274d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_RX_CTL_REG, value);
48374d0cd47SPaul Kocialkowski
48474d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
48574d0cd47SPaul Kocialkowski SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
48674d0cd47SPaul Kocialkowski SUN6I_DPHY_GCTL_EN);
48774d0cd47SPaul Kocialkowski
48874d0cd47SPaul Kocialkowski return 0;
48974d0cd47SPaul Kocialkowski }
49074d0cd47SPaul Kocialkowski
sun6i_dphy_power_on(struct phy * phy)49174d0cd47SPaul Kocialkowski static int sun6i_dphy_power_on(struct phy *phy)
49274d0cd47SPaul Kocialkowski {
49374d0cd47SPaul Kocialkowski struct sun6i_dphy *dphy = phy_get_drvdata(phy);
49474d0cd47SPaul Kocialkowski
49574d0cd47SPaul Kocialkowski switch (dphy->direction) {
49674d0cd47SPaul Kocialkowski case SUN6I_DPHY_DIRECTION_TX:
49774d0cd47SPaul Kocialkowski return sun6i_dphy_tx_power_on(dphy);
49874d0cd47SPaul Kocialkowski case SUN6I_DPHY_DIRECTION_RX:
49974d0cd47SPaul Kocialkowski return sun6i_dphy_rx_power_on(dphy);
50074d0cd47SPaul Kocialkowski default:
50174d0cd47SPaul Kocialkowski return -EINVAL;
50274d0cd47SPaul Kocialkowski }
50374d0cd47SPaul Kocialkowski }
50474d0cd47SPaul Kocialkowski
sun6i_dphy_power_off(struct phy * phy)5055d134abfSMaxime Ripard static int sun6i_dphy_power_off(struct phy *phy)
5065d134abfSMaxime Ripard {
5075d134abfSMaxime Ripard struct sun6i_dphy *dphy = phy_get_drvdata(phy);
5085d134abfSMaxime Ripard
50974d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, 0);
51074d0cd47SPaul Kocialkowski
51174d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, 0);
51274d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, 0);
51374d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, 0);
51474d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 0);
51574d0cd47SPaul Kocialkowski regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 0);
5165d134abfSMaxime Ripard
5175d134abfSMaxime Ripard return 0;
5185d134abfSMaxime Ripard }
5195d134abfSMaxime Ripard
sun6i_dphy_exit(struct phy * phy)5205d134abfSMaxime Ripard static int sun6i_dphy_exit(struct phy *phy)
5215d134abfSMaxime Ripard {
5225d134abfSMaxime Ripard struct sun6i_dphy *dphy = phy_get_drvdata(phy);
5235d134abfSMaxime Ripard
5245d134abfSMaxime Ripard clk_rate_exclusive_put(dphy->mod_clk);
5255d134abfSMaxime Ripard clk_disable_unprepare(dphy->mod_clk);
5265d134abfSMaxime Ripard reset_control_assert(dphy->reset);
5275d134abfSMaxime Ripard
5285d134abfSMaxime Ripard return 0;
5295d134abfSMaxime Ripard }
5305d134abfSMaxime Ripard
5315d134abfSMaxime Ripard
53282c8d386SRikard Falkeborn static const struct phy_ops sun6i_dphy_ops = {
5335d134abfSMaxime Ripard .configure = sun6i_dphy_configure,
5345d134abfSMaxime Ripard .power_on = sun6i_dphy_power_on,
5355d134abfSMaxime Ripard .power_off = sun6i_dphy_power_off,
5365d134abfSMaxime Ripard .init = sun6i_dphy_init,
5375d134abfSMaxime Ripard .exit = sun6i_dphy_exit,
5385d134abfSMaxime Ripard };
5395d134abfSMaxime Ripard
54082c8d386SRikard Falkeborn static const struct regmap_config sun6i_dphy_regmap_config = {
5415d134abfSMaxime Ripard .reg_bits = 32,
5425d134abfSMaxime Ripard .val_bits = 32,
5435d134abfSMaxime Ripard .reg_stride = 4,
544*4d0c2165SSamuel Holland .max_register = SUN50I_COMBO_PHY_REG2,
5455d134abfSMaxime Ripard .name = "mipi-dphy",
5465d134abfSMaxime Ripard };
5475d134abfSMaxime Ripard
sun6i_dphy_probe(struct platform_device * pdev)5485d134abfSMaxime Ripard static int sun6i_dphy_probe(struct platform_device *pdev)
5495d134abfSMaxime Ripard {
5505d134abfSMaxime Ripard struct phy_provider *phy_provider;
5515d134abfSMaxime Ripard struct sun6i_dphy *dphy;
55274d0cd47SPaul Kocialkowski const char *direction;
5535d134abfSMaxime Ripard void __iomem *regs;
55474d0cd47SPaul Kocialkowski int ret;
5555d134abfSMaxime Ripard
5565d134abfSMaxime Ripard dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
5575d134abfSMaxime Ripard if (!dphy)
5585d134abfSMaxime Ripard return -ENOMEM;
5595d134abfSMaxime Ripard
560a709ae51SSamuel Holland dphy->variant = device_get_match_data(&pdev->dev);
561a709ae51SSamuel Holland if (!dphy->variant)
562a709ae51SSamuel Holland return -EINVAL;
563a709ae51SSamuel Holland
56408d4dedaSChunfeng Yun regs = devm_platform_ioremap_resource(pdev, 0);
5655d134abfSMaxime Ripard if (IS_ERR(regs)) {
5665d134abfSMaxime Ripard dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
5675d134abfSMaxime Ripard return PTR_ERR(regs);
5685d134abfSMaxime Ripard }
5695d134abfSMaxime Ripard
5705d134abfSMaxime Ripard dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
5715d134abfSMaxime Ripard regs, &sun6i_dphy_regmap_config);
5725d134abfSMaxime Ripard if (IS_ERR(dphy->regs)) {
5735d134abfSMaxime Ripard dev_err(&pdev->dev, "Couldn't create the DPHY encoder regmap\n");
5745d134abfSMaxime Ripard return PTR_ERR(dphy->regs);
5755d134abfSMaxime Ripard }
5765d134abfSMaxime Ripard
5775d134abfSMaxime Ripard dphy->reset = devm_reset_control_get_shared(&pdev->dev, NULL);
5785d134abfSMaxime Ripard if (IS_ERR(dphy->reset)) {
5795d134abfSMaxime Ripard dev_err(&pdev->dev, "Couldn't get our reset line\n");
5805d134abfSMaxime Ripard return PTR_ERR(dphy->reset);
5815d134abfSMaxime Ripard }
5825d134abfSMaxime Ripard
5835d134abfSMaxime Ripard dphy->mod_clk = devm_clk_get(&pdev->dev, "mod");
5845d134abfSMaxime Ripard if (IS_ERR(dphy->mod_clk)) {
5855d134abfSMaxime Ripard dev_err(&pdev->dev, "Couldn't get the DPHY mod clock\n");
5865d134abfSMaxime Ripard return PTR_ERR(dphy->mod_clk);
5875d134abfSMaxime Ripard }
5885d134abfSMaxime Ripard
5895d134abfSMaxime Ripard dphy->phy = devm_phy_create(&pdev->dev, NULL, &sun6i_dphy_ops);
5905d134abfSMaxime Ripard if (IS_ERR(dphy->phy)) {
5915d134abfSMaxime Ripard dev_err(&pdev->dev, "failed to create PHY\n");
5925d134abfSMaxime Ripard return PTR_ERR(dphy->phy);
5935d134abfSMaxime Ripard }
5945d134abfSMaxime Ripard
59574d0cd47SPaul Kocialkowski dphy->direction = SUN6I_DPHY_DIRECTION_TX;
59674d0cd47SPaul Kocialkowski
59774d0cd47SPaul Kocialkowski ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
59874d0cd47SPaul Kocialkowski &direction);
59974d0cd47SPaul Kocialkowski
600a709ae51SSamuel Holland if (!ret && !strncmp(direction, "rx", 2)) {
601a709ae51SSamuel Holland if (!dphy->variant->rx_supported) {
602a709ae51SSamuel Holland dev_err(&pdev->dev, "RX not supported on this variant\n");
603a709ae51SSamuel Holland return -EOPNOTSUPP;
604a709ae51SSamuel Holland }
605a709ae51SSamuel Holland
60674d0cd47SPaul Kocialkowski dphy->direction = SUN6I_DPHY_DIRECTION_RX;
607a709ae51SSamuel Holland }
60874d0cd47SPaul Kocialkowski
6095d134abfSMaxime Ripard phy_set_drvdata(dphy->phy, dphy);
6105d134abfSMaxime Ripard phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
6115d134abfSMaxime Ripard
6125d134abfSMaxime Ripard return PTR_ERR_OR_ZERO(phy_provider);
6135d134abfSMaxime Ripard }
6145d134abfSMaxime Ripard
615a709ae51SSamuel Holland static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
6163fd490a7SSamuel Holland .tx_power_on = sun6i_a31_mipi_dphy_tx_power_on,
617a709ae51SSamuel Holland .rx_supported = true,
618a709ae51SSamuel Holland };
619a709ae51SSamuel Holland
620*4d0c2165SSamuel Holland static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
621*4d0c2165SSamuel Holland .tx_power_on = sun50i_a100_mipi_dphy_tx_power_on,
622*4d0c2165SSamuel Holland };
623*4d0c2165SSamuel Holland
6245d134abfSMaxime Ripard static const struct of_device_id sun6i_dphy_of_table[] = {
625a709ae51SSamuel Holland {
626a709ae51SSamuel Holland .compatible = "allwinner,sun6i-a31-mipi-dphy",
627a709ae51SSamuel Holland .data = &sun6i_a31_mipi_dphy_variant,
628a709ae51SSamuel Holland },
629*4d0c2165SSamuel Holland {
630*4d0c2165SSamuel Holland .compatible = "allwinner,sun50i-a100-mipi-dphy",
631*4d0c2165SSamuel Holland .data = &sun50i_a100_mipi_dphy_variant,
632*4d0c2165SSamuel Holland },
6335d134abfSMaxime Ripard { }
6345d134abfSMaxime Ripard };
6355d134abfSMaxime Ripard MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
6365d134abfSMaxime Ripard
6375d134abfSMaxime Ripard static struct platform_driver sun6i_dphy_platform_driver = {
6385d134abfSMaxime Ripard .probe = sun6i_dphy_probe,
6395d134abfSMaxime Ripard .driver = {
6405d134abfSMaxime Ripard .name = "sun6i-mipi-dphy",
6415d134abfSMaxime Ripard .of_match_table = sun6i_dphy_of_table,
6425d134abfSMaxime Ripard },
6435d134abfSMaxime Ripard };
6445d134abfSMaxime Ripard module_platform_driver(sun6i_dphy_platform_driver);
6455d134abfSMaxime Ripard
6465d134abfSMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin>");
6475d134abfSMaxime Ripard MODULE_DESCRIPTION("Allwinner A31 MIPI D-PHY Driver");
6485d134abfSMaxime Ripard MODULE_LICENSE("GPL");
649