1a228890fSIcenowy Zheng // SPDX-License-Identifier: GPL-2.0+ 2a228890fSIcenowy Zheng /* 3a228890fSIcenowy Zheng * Allwinner sun50i(H6) USB 3.0 phy driver 4a228890fSIcenowy Zheng * 5a228890fSIcenowy Zheng * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 6a228890fSIcenowy Zheng * 7a228890fSIcenowy Zheng * Based on phy-sun9i-usb.c, which is: 8a228890fSIcenowy Zheng * 9a228890fSIcenowy Zheng * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org> 10a228890fSIcenowy Zheng * 11a228890fSIcenowy Zheng * Based on code from Allwinner BSP, which is: 12a228890fSIcenowy Zheng * 13a228890fSIcenowy Zheng * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. 14a228890fSIcenowy Zheng */ 15a228890fSIcenowy Zheng 16a228890fSIcenowy Zheng #include <linux/clk.h> 17a228890fSIcenowy Zheng #include <linux/err.h> 18a228890fSIcenowy Zheng #include <linux/io.h> 19a228890fSIcenowy Zheng #include <linux/module.h> 20a228890fSIcenowy Zheng #include <linux/phy/phy.h> 21a228890fSIcenowy Zheng #include <linux/platform_device.h> 22a228890fSIcenowy Zheng #include <linux/reset.h> 23a228890fSIcenowy Zheng 24a228890fSIcenowy Zheng /* Interface Status and Control Registers */ 25a228890fSIcenowy Zheng #define SUNXI_ISCR 0x00 26a228890fSIcenowy Zheng #define SUNXI_PIPE_CLOCK_CONTROL 0x14 27a228890fSIcenowy Zheng #define SUNXI_PHY_TUNE_LOW 0x18 28a228890fSIcenowy Zheng #define SUNXI_PHY_TUNE_HIGH 0x1c 29a228890fSIcenowy Zheng #define SUNXI_PHY_EXTERNAL_CONTROL 0x20 30a228890fSIcenowy Zheng 31a228890fSIcenowy Zheng /* USB2.0 Interface Status and Control Register */ 32a228890fSIcenowy Zheng #define SUNXI_ISCR_FORCE_VBUS (3 << 12) 33a228890fSIcenowy Zheng 34a228890fSIcenowy Zheng /* PIPE Clock Control Register */ 35a228890fSIcenowy Zheng #define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) 36a228890fSIcenowy Zheng 37a228890fSIcenowy Zheng /* PHY External Control Register */ 38a228890fSIcenowy Zheng #define SUNXI_PEC_EXTERN_VBUS (3 << 1) 39a228890fSIcenowy Zheng #define SUNXI_PEC_SSC_EN (1 << 24) 40a228890fSIcenowy Zheng #define SUNXI_PEC_REF_SSP_EN (1 << 26) 41a228890fSIcenowy Zheng 42a228890fSIcenowy Zheng /* PHY Tune High Register */ 43a228890fSIcenowy Zheng #define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) 44a228890fSIcenowy Zheng #define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) 45a228890fSIcenowy Zheng #define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) 46a228890fSIcenowy Zheng #define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) 47a228890fSIcenowy Zheng #define SUNXI_TX_SWING_FULL(n) ((n) << 6) 48a228890fSIcenowy Zheng #define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) 49a228890fSIcenowy Zheng #define SUNXI_LOS_BIAS(n) ((n) << 3) 50a228890fSIcenowy Zheng #define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) 51a228890fSIcenowy Zheng #define SUNXI_TXVBOOSTLVL(n) ((n) << 0) 52a228890fSIcenowy Zheng #define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2) 53a228890fSIcenowy Zheng 54a228890fSIcenowy Zheng struct sun50i_usb3_phy { 55a228890fSIcenowy Zheng struct phy *phy; 56a228890fSIcenowy Zheng void __iomem *regs; 57a228890fSIcenowy Zheng struct reset_control *reset; 58a228890fSIcenowy Zheng struct clk *clk; 59a228890fSIcenowy Zheng }; 60a228890fSIcenowy Zheng 61a228890fSIcenowy Zheng static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy) 62a228890fSIcenowy Zheng { 63a228890fSIcenowy Zheng u32 val; 64a228890fSIcenowy Zheng 65a228890fSIcenowy Zheng val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); 66a228890fSIcenowy Zheng val |= SUNXI_PEC_EXTERN_VBUS; 67a228890fSIcenowy Zheng val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; 68a228890fSIcenowy Zheng writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); 69a228890fSIcenowy Zheng 70a228890fSIcenowy Zheng val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); 71a228890fSIcenowy Zheng val |= SUNXI_PCC_PIPE_CLK_OPEN; 72a228890fSIcenowy Zheng writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); 73a228890fSIcenowy Zheng 74a228890fSIcenowy Zheng val = readl(phy->regs + SUNXI_ISCR); 75a228890fSIcenowy Zheng val |= SUNXI_ISCR_FORCE_VBUS; 76a228890fSIcenowy Zheng writel(val, phy->regs + SUNXI_ISCR); 77a228890fSIcenowy Zheng 78a228890fSIcenowy Zheng /* 79a228890fSIcenowy Zheng * All the magic numbers written to the PHY_TUNE_{LOW_HIGH} 80a228890fSIcenowy Zheng * registers are directly taken from the BSP USB3 driver from 81a228890fSIcenowy Zheng * Allwiner. 82a228890fSIcenowy Zheng */ 83a228890fSIcenowy Zheng writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); 84a228890fSIcenowy Zheng 85a228890fSIcenowy Zheng val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); 86a228890fSIcenowy Zheng val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | 87a228890fSIcenowy Zheng SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | 88a228890fSIcenowy Zheng SUNXI_TX_DEEMPH_3P5DB_MASK); 89a228890fSIcenowy Zheng val |= SUNXI_TXVBOOSTLVL(0x7); 90a228890fSIcenowy Zheng val |= SUNXI_LOS_BIAS(0x7); 91a228890fSIcenowy Zheng val |= SUNXI_TX_SWING_FULL(0x55); 92a228890fSIcenowy Zheng val |= SUNXI_TX_DEEMPH_6DB(0x20); 93a228890fSIcenowy Zheng val |= SUNXI_TX_DEEMPH_3P5DB(0x15); 94a228890fSIcenowy Zheng writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); 95a228890fSIcenowy Zheng } 96a228890fSIcenowy Zheng 97a228890fSIcenowy Zheng static int sun50i_usb3_phy_init(struct phy *_phy) 98a228890fSIcenowy Zheng { 99a228890fSIcenowy Zheng struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); 100a228890fSIcenowy Zheng int ret; 101a228890fSIcenowy Zheng 102a228890fSIcenowy Zheng ret = clk_prepare_enable(phy->clk); 103a228890fSIcenowy Zheng if (ret) 104a228890fSIcenowy Zheng return ret; 105a228890fSIcenowy Zheng 106a228890fSIcenowy Zheng ret = reset_control_deassert(phy->reset); 107a228890fSIcenowy Zheng if (ret) { 108a228890fSIcenowy Zheng clk_disable_unprepare(phy->clk); 109a228890fSIcenowy Zheng return ret; 110a228890fSIcenowy Zheng } 111a228890fSIcenowy Zheng 112a228890fSIcenowy Zheng sun50i_usb3_phy_open(phy); 113a228890fSIcenowy Zheng return 0; 114a228890fSIcenowy Zheng } 115a228890fSIcenowy Zheng 116a228890fSIcenowy Zheng static int sun50i_usb3_phy_exit(struct phy *_phy) 117a228890fSIcenowy Zheng { 118a228890fSIcenowy Zheng struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); 119a228890fSIcenowy Zheng 120a228890fSIcenowy Zheng reset_control_assert(phy->reset); 121a228890fSIcenowy Zheng clk_disable_unprepare(phy->clk); 122a228890fSIcenowy Zheng 123a228890fSIcenowy Zheng return 0; 124a228890fSIcenowy Zheng } 125a228890fSIcenowy Zheng 126a228890fSIcenowy Zheng static const struct phy_ops sun50i_usb3_phy_ops = { 127a228890fSIcenowy Zheng .init = sun50i_usb3_phy_init, 128a228890fSIcenowy Zheng .exit = sun50i_usb3_phy_exit, 129a228890fSIcenowy Zheng .owner = THIS_MODULE, 130a228890fSIcenowy Zheng }; 131a228890fSIcenowy Zheng 132a228890fSIcenowy Zheng static int sun50i_usb3_phy_probe(struct platform_device *pdev) 133a228890fSIcenowy Zheng { 134a228890fSIcenowy Zheng struct sun50i_usb3_phy *phy; 135a228890fSIcenowy Zheng struct device *dev = &pdev->dev; 136a228890fSIcenowy Zheng struct phy_provider *phy_provider; 137a228890fSIcenowy Zheng struct resource *res; 138a228890fSIcenowy Zheng 139a228890fSIcenowy Zheng phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 140a228890fSIcenowy Zheng if (!phy) 141a228890fSIcenowy Zheng return -ENOMEM; 142a228890fSIcenowy Zheng 143a228890fSIcenowy Zheng phy->clk = devm_clk_get(dev, NULL); 144a228890fSIcenowy Zheng if (IS_ERR(phy->clk)) { 145a228890fSIcenowy Zheng if (PTR_ERR(phy->clk) != -EPROBE_DEFER) 146a228890fSIcenowy Zheng dev_err(dev, "failed to get phy clock\n"); 147a228890fSIcenowy Zheng return PTR_ERR(phy->clk); 148a228890fSIcenowy Zheng } 149a228890fSIcenowy Zheng 150a228890fSIcenowy Zheng phy->reset = devm_reset_control_get(dev, NULL); 151a228890fSIcenowy Zheng if (IS_ERR(phy->reset)) { 152a228890fSIcenowy Zheng dev_err(dev, "failed to get reset control\n"); 153a228890fSIcenowy Zheng return PTR_ERR(phy->reset); 154a228890fSIcenowy Zheng } 155a228890fSIcenowy Zheng 156a228890fSIcenowy Zheng res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 157a228890fSIcenowy Zheng phy->regs = devm_ioremap_resource(dev, res); 158a228890fSIcenowy Zheng if (IS_ERR(phy->regs)) 159a228890fSIcenowy Zheng return PTR_ERR(phy->regs); 160a228890fSIcenowy Zheng 161a228890fSIcenowy Zheng phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops); 162a228890fSIcenowy Zheng if (IS_ERR(phy->phy)) { 163a228890fSIcenowy Zheng dev_err(dev, "failed to create PHY\n"); 164a228890fSIcenowy Zheng return PTR_ERR(phy->phy); 165a228890fSIcenowy Zheng } 166a228890fSIcenowy Zheng 167a228890fSIcenowy Zheng phy_set_drvdata(phy->phy, phy); 168a228890fSIcenowy Zheng phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 169a228890fSIcenowy Zheng 170a228890fSIcenowy Zheng return PTR_ERR_OR_ZERO(phy_provider); 171a228890fSIcenowy Zheng } 172a228890fSIcenowy Zheng 173a228890fSIcenowy Zheng static const struct of_device_id sun50i_usb3_phy_of_match[] = { 174a228890fSIcenowy Zheng { .compatible = "allwinner,sun50i-h6-usb3-phy" }, 175a228890fSIcenowy Zheng { }, 176a228890fSIcenowy Zheng }; 177a228890fSIcenowy Zheng MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match); 178a228890fSIcenowy Zheng 179a228890fSIcenowy Zheng static struct platform_driver sun50i_usb3_phy_driver = { 180a228890fSIcenowy Zheng .probe = sun50i_usb3_phy_probe, 181a228890fSIcenowy Zheng .driver = { 182a228890fSIcenowy Zheng .of_match_table = sun50i_usb3_phy_of_match, 183a228890fSIcenowy Zheng .name = "sun50i-usb3-phy", 184a228890fSIcenowy Zheng } 185a228890fSIcenowy Zheng }; 186a228890fSIcenowy Zheng module_platform_driver(sun50i_usb3_phy_driver); 187a228890fSIcenowy Zheng 188a228890fSIcenowy Zheng MODULE_DESCRIPTION("Allwinner H6 USB 3.0 phy driver"); 189a228890fSIcenowy Zheng MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); 190a228890fSIcenowy Zheng MODULE_LICENSE("GPL"); 191