1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Allwinner sun4i USB phy driver
4  *
5  * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
6  *
7  * Based on code from
8  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9  *
10  * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
11  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
12  * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
13  */
14 
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/extcon-provider.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/io.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mutex.h>
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/phy/phy.h>
30 #include <linux/phy/phy-sun4i-usb.h>
31 #include <linux/platform_device.h>
32 #include <linux/power_supply.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/reset.h>
35 #include <linux/spinlock.h>
36 #include <linux/usb/of.h>
37 #include <linux/workqueue.h>
38 
39 #define REG_ISCR			0x00
40 #define REG_PHYCTL_A10			0x04
41 #define REG_PHYBIST			0x08
42 #define REG_PHYTUNE			0x0c
43 #define REG_PHYCTL_A33			0x10
44 #define REG_PHY_OTGCTL			0x20
45 
46 #define REG_HCI_PHY_CTL			0x10
47 
48 #define PHYCTL_DATA			BIT(7)
49 
50 #define OTGCTL_ROUTE_MUSB		BIT(0)
51 
52 #define SUNXI_AHB_ICHR8_EN		BIT(10)
53 #define SUNXI_AHB_INCR4_BURST_EN	BIT(9)
54 #define SUNXI_AHB_INCRX_ALIGN_EN	BIT(8)
55 #define SUNXI_ULPI_BYPASS_EN		BIT(0)
56 
57 /* ISCR, Interface Status and Control bits */
58 #define ISCR_ID_PULLUP_EN		(1 << 17)
59 #define ISCR_DPDM_PULLUP_EN	(1 << 16)
60 /* sunxi has the phy id/vbus pins not connected, so we use the force bits */
61 #define ISCR_FORCE_ID_MASK	(3 << 14)
62 #define ISCR_FORCE_ID_LOW		(2 << 14)
63 #define ISCR_FORCE_ID_HIGH	(3 << 14)
64 #define ISCR_FORCE_VBUS_MASK	(3 << 12)
65 #define ISCR_FORCE_VBUS_LOW	(2 << 12)
66 #define ISCR_FORCE_VBUS_HIGH	(3 << 12)
67 
68 /* Common Control Bits for Both PHYs */
69 #define PHY_PLL_BW			0x03
70 #define PHY_RES45_CAL_EN		0x0c
71 
72 /* Private Control Bits for Each PHY */
73 #define PHY_TX_AMPLITUDE_TUNE		0x20
74 #define PHY_TX_SLEWRATE_TUNE		0x22
75 #define PHY_VBUSVALID_TH_SEL		0x25
76 #define PHY_PULLUP_RES_SEL		0x27
77 #define PHY_OTG_FUNC_EN			0x28
78 #define PHY_VBUS_DET_EN			0x29
79 #define PHY_DISCON_TH_SEL		0x2a
80 #define PHY_SQUELCH_DETECT		0x3c
81 
82 /* A83T specific control bits for PHY0 */
83 #define PHY_CTL_VBUSVLDEXT		BIT(5)
84 #define PHY_CTL_SIDDQ			BIT(3)
85 #define PHY_CTL_H3_SIDDQ		BIT(1)
86 
87 /* A83T specific control bits for PHY2 HSIC */
88 #define SUNXI_EHCI_HS_FORCE		BIT(20)
89 #define SUNXI_HSIC_CONNECT_DET		BIT(17)
90 #define SUNXI_HSIC_CONNECT_INT		BIT(16)
91 #define SUNXI_HSIC			BIT(1)
92 
93 #define MAX_PHYS			4
94 
95 /*
96  * Note do not raise the debounce time, we must report Vusb high within 100ms
97  * otherwise we get Vbus errors
98  */
99 #define DEBOUNCE_TIME			msecs_to_jiffies(50)
100 #define POLL_TIME			msecs_to_jiffies(250)
101 
102 struct sun4i_usb_phy_cfg {
103 	int num_phys;
104 	int hsic_index;
105 	u32 disc_thresh;
106 	u32 hci_phy_ctl_clear;
107 	u8 phyctl_offset;
108 	bool dedicated_clocks;
109 	bool phy0_dual_route;
110 	bool needs_phy2_siddq;
111 	bool siddq_in_base;
112 	bool poll_vbusen;
113 	int missing_phys;
114 };
115 
116 struct sun4i_usb_phy_data {
117 	void __iomem *base;
118 	const struct sun4i_usb_phy_cfg *cfg;
119 	enum usb_dr_mode dr_mode;
120 	spinlock_t reg_lock; /* guard access to phyctl reg */
121 	struct sun4i_usb_phy {
122 		struct phy *phy;
123 		void __iomem *pmu;
124 		struct regulator *vbus;
125 		struct reset_control *reset;
126 		struct clk *clk;
127 		struct clk *clk2;
128 		bool regulator_on;
129 		int index;
130 	} phys[MAX_PHYS];
131 	/* phy0 / otg related variables */
132 	struct extcon_dev *extcon;
133 	bool phy0_init;
134 	struct gpio_desc *id_det_gpio;
135 	struct gpio_desc *vbus_det_gpio;
136 	struct power_supply *vbus_power_supply;
137 	struct notifier_block vbus_power_nb;
138 	bool vbus_power_nb_registered;
139 	bool force_session_end;
140 	int id_det_irq;
141 	int vbus_det_irq;
142 	int id_det;
143 	int vbus_det;
144 	struct delayed_work detect;
145 };
146 
147 #define to_sun4i_usb_phy_data(phy) \
148 	container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
149 
150 static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set)
151 {
152 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
153 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
154 	u32 iscr;
155 
156 	iscr = readl(data->base + REG_ISCR);
157 	iscr &= ~clr;
158 	iscr |= set;
159 	writel(iscr, data->base + REG_ISCR);
160 }
161 
162 static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val)
163 {
164 	if (val)
165 		val = ISCR_FORCE_ID_HIGH;
166 	else
167 		val = ISCR_FORCE_ID_LOW;
168 
169 	sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val);
170 }
171 
172 static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val)
173 {
174 	if (val)
175 		val = ISCR_FORCE_VBUS_HIGH;
176 	else
177 		val = ISCR_FORCE_VBUS_LOW;
178 
179 	sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val);
180 }
181 
182 static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
183 				int len)
184 {
185 	struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
186 	u32 temp, usbc_bit = BIT(phy->index * 2);
187 	void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
188 	unsigned long flags;
189 	int i;
190 
191 	spin_lock_irqsave(&phy_data->reg_lock, flags);
192 
193 	if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
194 		/* SoCs newer than A33 need us to set phyctl to 0 explicitly */
195 		writel(0, phyctl);
196 	}
197 
198 	for (i = 0; i < len; i++) {
199 		temp = readl(phyctl);
200 
201 		/* clear the address portion */
202 		temp &= ~(0xff << 8);
203 
204 		/* set the address */
205 		temp |= ((addr + i) << 8);
206 		writel(temp, phyctl);
207 
208 		/* set the data bit and clear usbc bit*/
209 		temp = readb(phyctl);
210 		if (data & 0x1)
211 			temp |= PHYCTL_DATA;
212 		else
213 			temp &= ~PHYCTL_DATA;
214 		temp &= ~usbc_bit;
215 		writeb(temp, phyctl);
216 
217 		/* pulse usbc_bit */
218 		temp = readb(phyctl);
219 		temp |= usbc_bit;
220 		writeb(temp, phyctl);
221 
222 		temp = readb(phyctl);
223 		temp &= ~usbc_bit;
224 		writeb(temp, phyctl);
225 
226 		data >>= 1;
227 	}
228 
229 	spin_unlock_irqrestore(&phy_data->reg_lock, flags);
230 }
231 
232 static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
233 {
234 	struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
235 	u32 bits, reg_value;
236 
237 	if (!phy->pmu)
238 		return;
239 
240 	bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
241 		SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
242 
243 	/* A83T USB2 is HSIC */
244 	if (phy_data->cfg->hsic_index &&
245 	    phy->index == phy_data->cfg->hsic_index)
246 		bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
247 			SUNXI_HSIC;
248 
249 	reg_value = readl(phy->pmu);
250 
251 	if (enable)
252 		reg_value |= bits;
253 	else
254 		reg_value &= ~bits;
255 
256 	writel(reg_value, phy->pmu);
257 }
258 
259 static int sun4i_usb_phy_init(struct phy *_phy)
260 {
261 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
262 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
263 	int ret;
264 	u32 val;
265 
266 	ret = clk_prepare_enable(phy->clk);
267 	if (ret)
268 		return ret;
269 
270 	ret = clk_prepare_enable(phy->clk2);
271 	if (ret) {
272 		clk_disable_unprepare(phy->clk);
273 		return ret;
274 	}
275 
276 	ret = reset_control_deassert(phy->reset);
277 	if (ret) {
278 		clk_disable_unprepare(phy->clk2);
279 		clk_disable_unprepare(phy->clk);
280 		return ret;
281 	}
282 
283 	/* Some PHYs on some SoCs need the help of PHY2 to work. */
284 	if (data->cfg->needs_phy2_siddq && phy->index != 2) {
285 		struct sun4i_usb_phy *phy2 = &data->phys[2];
286 
287 		ret = clk_prepare_enable(phy2->clk);
288 		if (ret) {
289 			reset_control_assert(phy->reset);
290 			clk_disable_unprepare(phy->clk2);
291 			clk_disable_unprepare(phy->clk);
292 			return ret;
293 		}
294 
295 		ret = reset_control_deassert(phy2->reset);
296 		if (ret) {
297 			clk_disable_unprepare(phy2->clk);
298 			reset_control_assert(phy->reset);
299 			clk_disable_unprepare(phy->clk2);
300 			clk_disable_unprepare(phy->clk);
301 			return ret;
302 		}
303 
304 		/*
305 		 * This extra clock is just needed to access the
306 		 * REG_HCI_PHY_CTL PMU register for PHY2.
307 		 */
308 		ret = clk_prepare_enable(phy2->clk2);
309 		if (ret) {
310 			reset_control_assert(phy2->reset);
311 			clk_disable_unprepare(phy2->clk);
312 			reset_control_assert(phy->reset);
313 			clk_disable_unprepare(phy->clk2);
314 			clk_disable_unprepare(phy->clk);
315 			return ret;
316 		}
317 
318 		if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
319 			val = readl(phy2->pmu + REG_HCI_PHY_CTL);
320 			val &= ~data->cfg->hci_phy_ctl_clear;
321 			writel(val, phy2->pmu + REG_HCI_PHY_CTL);
322 		}
323 
324 		clk_disable_unprepare(phy->clk2);
325 	}
326 
327 	if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
328 		val = readl(phy->pmu + REG_HCI_PHY_CTL);
329 		val &= ~data->cfg->hci_phy_ctl_clear;
330 		writel(val, phy->pmu + REG_HCI_PHY_CTL);
331 	}
332 
333 	if (data->cfg->siddq_in_base) {
334 		if (phy->index == 0) {
335 			val = readl(data->base + data->cfg->phyctl_offset);
336 			val |= PHY_CTL_VBUSVLDEXT;
337 			val &= ~PHY_CTL_SIDDQ;
338 			writel(val, data->base + data->cfg->phyctl_offset);
339 		}
340 	} else {
341 		/* Enable USB 45 Ohm resistor calibration */
342 		if (phy->index == 0)
343 			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
344 
345 		/* Adjust PHY's magnitude and rate */
346 		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
347 
348 		/* Disconnect threshold adjustment */
349 		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
350 				    data->cfg->disc_thresh, 2);
351 	}
352 
353 	sun4i_usb_phy_passby(phy, 1);
354 
355 	if (phy->index == 0) {
356 		data->phy0_init = true;
357 
358 		/* Enable pull-ups */
359 		sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
360 		sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
361 
362 		/* Force ISCR and cable state updates */
363 		data->id_det = -1;
364 		data->vbus_det = -1;
365 		queue_delayed_work(system_wq, &data->detect, 0);
366 	}
367 
368 	return 0;
369 }
370 
371 static int sun4i_usb_phy_exit(struct phy *_phy)
372 {
373 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
374 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
375 
376 	if (phy->index == 0) {
377 		if (data->cfg->siddq_in_base) {
378 			void __iomem *phyctl = data->base +
379 				data->cfg->phyctl_offset;
380 
381 			writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
382 		}
383 
384 		/* Disable pull-ups */
385 		sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
386 		sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
387 		data->phy0_init = false;
388 	}
389 
390 	if (data->cfg->needs_phy2_siddq && phy->index != 2) {
391 		struct sun4i_usb_phy *phy2 = &data->phys[2];
392 
393 		clk_disable_unprepare(phy2->clk);
394 		reset_control_assert(phy2->reset);
395 	}
396 
397 	sun4i_usb_phy_passby(phy, 0);
398 	reset_control_assert(phy->reset);
399 	clk_disable_unprepare(phy->clk2);
400 	clk_disable_unprepare(phy->clk);
401 
402 	return 0;
403 }
404 
405 static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
406 {
407 	switch (data->dr_mode) {
408 	case USB_DR_MODE_OTG:
409 		if (data->id_det_gpio)
410 			return gpiod_get_value_cansleep(data->id_det_gpio);
411 		else
412 			return 1; /* Fallback to peripheral mode */
413 	case USB_DR_MODE_HOST:
414 		return 0;
415 	case USB_DR_MODE_PERIPHERAL:
416 	default:
417 		return 1;
418 	}
419 }
420 
421 static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
422 {
423 	if (data->vbus_det_gpio)
424 		return gpiod_get_value_cansleep(data->vbus_det_gpio);
425 
426 	if (data->vbus_power_supply) {
427 		union power_supply_propval val;
428 		int r;
429 
430 		r = power_supply_get_property(data->vbus_power_supply,
431 					      POWER_SUPPLY_PROP_PRESENT, &val);
432 		if (r == 0)
433 			return val.intval;
434 	}
435 
436 	/* Fallback: report vbus as high */
437 	return 1;
438 }
439 
440 static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
441 {
442 	return data->vbus_det_gpio || data->vbus_power_supply;
443 }
444 
445 static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
446 {
447 	if ((data->id_det_gpio && data->id_det_irq <= 0) ||
448 	    (data->vbus_det_gpio && data->vbus_det_irq <= 0))
449 		return true;
450 
451 	/*
452 	 * The A31/A23/A33 companion pmics (AXP221/AXP223) do not
453 	 * generate vbus change interrupts when the board is driving
454 	 * vbus using the N_VBUSEN pin on the pmic, so we must poll
455 	 * when using the pmic for vbus-det _and_ we're driving vbus.
456 	 */
457 	if (data->cfg->poll_vbusen && data->vbus_power_supply &&
458 	    data->phys[0].regulator_on)
459 		return true;
460 
461 	return false;
462 }
463 
464 static int sun4i_usb_phy_power_on(struct phy *_phy)
465 {
466 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
467 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
468 	int ret;
469 
470 	if (!phy->vbus || phy->regulator_on)
471 		return 0;
472 
473 	/* For phy0 only turn on Vbus if we don't have an ext. Vbus */
474 	if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) &&
475 				data->vbus_det) {
476 		dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n");
477 		return 0;
478 	}
479 
480 	ret = regulator_enable(phy->vbus);
481 	if (ret)
482 		return ret;
483 
484 	phy->regulator_on = true;
485 
486 	/* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
487 	if (phy->index == 0 && sun4i_usb_phy0_poll(data))
488 		mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
489 
490 	return 0;
491 }
492 
493 static int sun4i_usb_phy_power_off(struct phy *_phy)
494 {
495 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
496 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
497 
498 	if (!phy->vbus || !phy->regulator_on)
499 		return 0;
500 
501 	regulator_disable(phy->vbus);
502 	phy->regulator_on = false;
503 
504 	/*
505 	 * phy0 vbus typically slowly discharges, sometimes this causes the
506 	 * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
507 	 */
508 	if (phy->index == 0 && !sun4i_usb_phy0_poll(data))
509 		mod_delayed_work(system_wq, &data->detect, POLL_TIME);
510 
511 	return 0;
512 }
513 
514 static int sun4i_usb_phy_set_mode(struct phy *_phy,
515 				  enum phy_mode mode, int submode)
516 {
517 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
518 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
519 	int new_mode;
520 
521 	if (phy->index != 0) {
522 		if (mode == PHY_MODE_USB_HOST)
523 			return 0;
524 		return -EINVAL;
525 	}
526 
527 	switch (mode) {
528 	case PHY_MODE_USB_HOST:
529 		new_mode = USB_DR_MODE_HOST;
530 		break;
531 	case PHY_MODE_USB_DEVICE:
532 		new_mode = USB_DR_MODE_PERIPHERAL;
533 		break;
534 	case PHY_MODE_USB_OTG:
535 		new_mode = USB_DR_MODE_OTG;
536 		break;
537 	default:
538 		return -EINVAL;
539 	}
540 
541 	if (new_mode != data->dr_mode) {
542 		dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode);
543 		data->dr_mode = new_mode;
544 	}
545 
546 	data->id_det = -1; /* Force reprocessing of id */
547 	data->force_session_end = true;
548 	queue_delayed_work(system_wq, &data->detect, 0);
549 
550 	return 0;
551 }
552 
553 void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
554 {
555 	struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
556 
557 	sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
558 }
559 EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
560 
561 static const struct phy_ops sun4i_usb_phy_ops = {
562 	.init		= sun4i_usb_phy_init,
563 	.exit		= sun4i_usb_phy_exit,
564 	.power_on	= sun4i_usb_phy_power_on,
565 	.power_off	= sun4i_usb_phy_power_off,
566 	.set_mode	= sun4i_usb_phy_set_mode,
567 	.owner		= THIS_MODULE,
568 };
569 
570 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
571 {
572 	u32 regval;
573 
574 	regval = readl(data->base + REG_PHY_OTGCTL);
575 	if (id_det == 0) {
576 		/* Host mode. Route phy0 to EHCI/OHCI */
577 		regval &= ~OTGCTL_ROUTE_MUSB;
578 	} else {
579 		/* Peripheral mode. Route phy0 to MUSB */
580 		regval |= OTGCTL_ROUTE_MUSB;
581 	}
582 	writel(regval, data->base + REG_PHY_OTGCTL);
583 }
584 
585 static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
586 {
587 	struct sun4i_usb_phy_data *data =
588 		container_of(work, struct sun4i_usb_phy_data, detect.work);
589 	struct phy *phy0 = data->phys[0].phy;
590 	struct sun4i_usb_phy *phy;
591 	bool force_session_end, id_notify = false, vbus_notify = false;
592 	int id_det, vbus_det;
593 
594 	if (!phy0)
595 		return;
596 
597 	phy = phy_get_drvdata(phy0);
598 	id_det = sun4i_usb_phy0_get_id_det(data);
599 	vbus_det = sun4i_usb_phy0_get_vbus_det(data);
600 
601 	mutex_lock(&phy0->mutex);
602 
603 	if (!data->phy0_init) {
604 		mutex_unlock(&phy0->mutex);
605 		return;
606 	}
607 
608 	force_session_end = data->force_session_end;
609 	data->force_session_end = false;
610 
611 	if (id_det != data->id_det) {
612 		/* id-change, force session end if we've no vbus detection */
613 		if (data->dr_mode == USB_DR_MODE_OTG &&
614 		    !sun4i_usb_phy0_have_vbus_det(data))
615 			force_session_end = true;
616 
617 		/* When entering host mode (id = 0) force end the session now */
618 		if (force_session_end && id_det == 0) {
619 			sun4i_usb_phy0_set_vbus_detect(phy0, 0);
620 			msleep(200);
621 			sun4i_usb_phy0_set_vbus_detect(phy0, 1);
622 		}
623 		sun4i_usb_phy0_set_id_detect(phy0, id_det);
624 		data->id_det = id_det;
625 		id_notify = true;
626 	}
627 
628 	if (vbus_det != data->vbus_det) {
629 		sun4i_usb_phy0_set_vbus_detect(phy0, vbus_det);
630 		data->vbus_det = vbus_det;
631 		vbus_notify = true;
632 	}
633 
634 	mutex_unlock(&phy0->mutex);
635 
636 	if (id_notify) {
637 		extcon_set_state_sync(data->extcon, EXTCON_USB_HOST,
638 					!id_det);
639 		/* When leaving host mode force end the session here */
640 		if (force_session_end && id_det == 1) {
641 			mutex_lock(&phy0->mutex);
642 			sun4i_usb_phy0_set_vbus_detect(phy0, 0);
643 			msleep(1000);
644 			sun4i_usb_phy0_set_vbus_detect(phy0, 1);
645 			mutex_unlock(&phy0->mutex);
646 		}
647 
648 		/* Enable PHY0 passby for host mode only. */
649 		sun4i_usb_phy_passby(phy, !id_det);
650 
651 		/* Re-route PHY0 if necessary */
652 		if (data->cfg->phy0_dual_route)
653 			sun4i_usb_phy0_reroute(data, id_det);
654 	}
655 
656 	if (vbus_notify)
657 		extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det);
658 
659 	if (sun4i_usb_phy0_poll(data))
660 		queue_delayed_work(system_wq, &data->detect, POLL_TIME);
661 }
662 
663 static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id)
664 {
665 	struct sun4i_usb_phy_data *data = dev_id;
666 
667 	/* vbus or id changed, let the pins settle and then scan them */
668 	mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
669 
670 	return IRQ_HANDLED;
671 }
672 
673 static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb,
674 				      unsigned long val, void *v)
675 {
676 	struct sun4i_usb_phy_data *data =
677 		container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb);
678 	struct power_supply *psy = v;
679 
680 	/* Properties on the vbus_power_supply changed, scan vbus_det */
681 	if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply)
682 		mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
683 
684 	return NOTIFY_OK;
685 }
686 
687 static struct phy *sun4i_usb_phy_xlate(struct device *dev,
688 					struct of_phandle_args *args)
689 {
690 	struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
691 
692 	if (args->args[0] >= data->cfg->num_phys)
693 		return ERR_PTR(-ENODEV);
694 
695 	if (data->cfg->missing_phys & BIT(args->args[0]))
696 		return ERR_PTR(-ENODEV);
697 
698 	return data->phys[args->args[0]].phy;
699 }
700 
701 static int sun4i_usb_phy_remove(struct platform_device *pdev)
702 {
703 	struct device *dev = &pdev->dev;
704 	struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
705 
706 	if (data->vbus_power_nb_registered)
707 		power_supply_unreg_notifier(&data->vbus_power_nb);
708 	if (data->id_det_irq > 0)
709 		devm_free_irq(dev, data->id_det_irq, data);
710 	if (data->vbus_det_irq > 0)
711 		devm_free_irq(dev, data->vbus_det_irq, data);
712 
713 	cancel_delayed_work_sync(&data->detect);
714 
715 	return 0;
716 }
717 
718 static const unsigned int sun4i_usb_phy0_cable[] = {
719 	EXTCON_USB,
720 	EXTCON_USB_HOST,
721 	EXTCON_NONE,
722 };
723 
724 static int sun4i_usb_phy_probe(struct platform_device *pdev)
725 {
726 	struct sun4i_usb_phy_data *data;
727 	struct device *dev = &pdev->dev;
728 	struct device_node *np = dev->of_node;
729 	struct phy_provider *phy_provider;
730 	int i, ret;
731 
732 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
733 	if (!data)
734 		return -ENOMEM;
735 
736 	spin_lock_init(&data->reg_lock);
737 	INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
738 	dev_set_drvdata(dev, data);
739 	data->cfg = of_device_get_match_data(dev);
740 	if (!data->cfg)
741 		return -EINVAL;
742 
743 	data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
744 	if (IS_ERR(data->base))
745 		return PTR_ERR(data->base);
746 
747 	data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
748 						    GPIOD_IN);
749 	if (IS_ERR(data->id_det_gpio)) {
750 		dev_err(dev, "Couldn't request ID GPIO\n");
751 		return PTR_ERR(data->id_det_gpio);
752 	}
753 
754 	data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
755 						      GPIOD_IN);
756 	if (IS_ERR(data->vbus_det_gpio)) {
757 		dev_err(dev, "Couldn't request VBUS detect GPIO\n");
758 		return PTR_ERR(data->vbus_det_gpio);
759 	}
760 
761 	if (of_find_property(np, "usb0_vbus_power-supply", NULL)) {
762 		data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
763 						     "usb0_vbus_power-supply");
764 		if (IS_ERR(data->vbus_power_supply)) {
765 			dev_err(dev, "Couldn't get the VBUS power supply\n");
766 			return PTR_ERR(data->vbus_power_supply);
767 		}
768 
769 		if (!data->vbus_power_supply)
770 			return -EPROBE_DEFER;
771 	}
772 
773 	data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
774 
775 	data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable);
776 	if (IS_ERR(data->extcon)) {
777 		dev_err(dev, "Couldn't allocate our extcon device\n");
778 		return PTR_ERR(data->extcon);
779 	}
780 
781 	ret = devm_extcon_dev_register(dev, data->extcon);
782 	if (ret) {
783 		dev_err(dev, "failed to register extcon: %d\n", ret);
784 		return ret;
785 	}
786 
787 	for (i = 0; i < data->cfg->num_phys; i++) {
788 		struct sun4i_usb_phy *phy = data->phys + i;
789 		char name[16];
790 
791 		if (data->cfg->missing_phys & BIT(i))
792 			continue;
793 
794 		snprintf(name, sizeof(name), "usb%d_vbus", i);
795 		phy->vbus = devm_regulator_get_optional(dev, name);
796 		if (IS_ERR(phy->vbus)) {
797 			if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
798 				dev_err(dev,
799 					"Couldn't get regulator %s... Deferring probe\n",
800 					name);
801 				return -EPROBE_DEFER;
802 			}
803 
804 			phy->vbus = NULL;
805 		}
806 
807 		if (data->cfg->dedicated_clocks)
808 			snprintf(name, sizeof(name), "usb%d_phy", i);
809 		else
810 			strscpy(name, "usb_phy", sizeof(name));
811 
812 		phy->clk = devm_clk_get(dev, name);
813 		if (IS_ERR(phy->clk)) {
814 			dev_err(dev, "failed to get clock %s\n", name);
815 			return PTR_ERR(phy->clk);
816 		}
817 
818 		/* The first PHY is always tied to OTG, and never HSIC */
819 		if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
820 			/* HSIC needs secondary clock */
821 			snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
822 			phy->clk2 = devm_clk_get(dev, name);
823 			if (IS_ERR(phy->clk2)) {
824 				dev_err(dev, "failed to get clock %s\n", name);
825 				return PTR_ERR(phy->clk2);
826 			}
827 		} else {
828 			snprintf(name, sizeof(name), "pmu%d_clk", i);
829 			phy->clk2 = devm_clk_get_optional(dev, name);
830 			if (IS_ERR(phy->clk2)) {
831 				dev_err(dev, "failed to get clock %s\n", name);
832 				return PTR_ERR(phy->clk2);
833 			}
834 		}
835 
836 		snprintf(name, sizeof(name), "usb%d_reset", i);
837 		phy->reset = devm_reset_control_get(dev, name);
838 		if (IS_ERR(phy->reset)) {
839 			dev_err(dev, "failed to get reset %s\n", name);
840 			return PTR_ERR(phy->reset);
841 		}
842 
843 		if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
844 			snprintf(name, sizeof(name), "pmu%d", i);
845 			phy->pmu = devm_platform_ioremap_resource_byname(pdev, name);
846 			if (IS_ERR(phy->pmu))
847 				return PTR_ERR(phy->pmu);
848 		}
849 
850 		phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
851 		if (IS_ERR(phy->phy)) {
852 			dev_err(dev, "failed to create PHY %d\n", i);
853 			return PTR_ERR(phy->phy);
854 		}
855 
856 		phy->index = i;
857 		phy_set_drvdata(phy->phy, &data->phys[i]);
858 	}
859 
860 	data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
861 	if (data->id_det_irq > 0) {
862 		ret = devm_request_irq(dev, data->id_det_irq,
863 				sun4i_usb_phy0_id_vbus_det_irq,
864 				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
865 				"usb0-id-det", data);
866 		if (ret) {
867 			dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
868 			return ret;
869 		}
870 	}
871 
872 	data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
873 	if (data->vbus_det_irq > 0) {
874 		ret = devm_request_irq(dev, data->vbus_det_irq,
875 				sun4i_usb_phy0_id_vbus_det_irq,
876 				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
877 				"usb0-vbus-det", data);
878 		if (ret) {
879 			dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
880 			data->vbus_det_irq = -1;
881 			sun4i_usb_phy_remove(pdev); /* Stop detect work */
882 			return ret;
883 		}
884 	}
885 
886 	if (data->vbus_power_supply) {
887 		data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify;
888 		data->vbus_power_nb.priority = 0;
889 		ret = power_supply_reg_notifier(&data->vbus_power_nb);
890 		if (ret) {
891 			sun4i_usb_phy_remove(pdev); /* Stop detect work */
892 			return ret;
893 		}
894 		data->vbus_power_nb_registered = true;
895 	}
896 
897 	phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
898 	if (IS_ERR(phy_provider)) {
899 		sun4i_usb_phy_remove(pdev); /* Stop detect work */
900 		return PTR_ERR(phy_provider);
901 	}
902 
903 	dev_dbg(dev, "successfully loaded\n");
904 
905 	return 0;
906 }
907 
908 static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
909 	.num_phys = 1,
910 	.disc_thresh = 3,
911 	.phyctl_offset = REG_PHYCTL_A10,
912 	.dedicated_clocks = true,
913 };
914 
915 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
916 	.num_phys = 3,
917 	.disc_thresh = 3,
918 	.phyctl_offset = REG_PHYCTL_A10,
919 	.dedicated_clocks = false,
920 };
921 
922 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
923 	.num_phys = 2,
924 	.disc_thresh = 2,
925 	.phyctl_offset = REG_PHYCTL_A10,
926 	.dedicated_clocks = false,
927 };
928 
929 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
930 	.num_phys = 3,
931 	.disc_thresh = 3,
932 	.phyctl_offset = REG_PHYCTL_A10,
933 	.dedicated_clocks = true,
934 	.poll_vbusen = true,
935 };
936 
937 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
938 	.num_phys = 3,
939 	.disc_thresh = 2,
940 	.phyctl_offset = REG_PHYCTL_A10,
941 	.dedicated_clocks = false,
942 };
943 
944 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
945 	.num_phys = 2,
946 	.disc_thresh = 3,
947 	.phyctl_offset = REG_PHYCTL_A10,
948 	.dedicated_clocks = true,
949 	.poll_vbusen = true,
950 };
951 
952 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
953 	.num_phys = 2,
954 	.disc_thresh = 3,
955 	.phyctl_offset = REG_PHYCTL_A33,
956 	.dedicated_clocks = true,
957 	.poll_vbusen = true,
958 };
959 
960 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
961 	.num_phys = 3,
962 	.hsic_index = 2,
963 	.phyctl_offset = REG_PHYCTL_A33,
964 	.dedicated_clocks = true,
965 	.siddq_in_base = true,
966 };
967 
968 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
969 	.num_phys = 4,
970 	.disc_thresh = 3,
971 	.phyctl_offset = REG_PHYCTL_A33,
972 	.dedicated_clocks = true,
973 	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
974 	.phy0_dual_route = true,
975 };
976 
977 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
978 	.num_phys = 3,
979 	.disc_thresh = 3,
980 	.phyctl_offset = REG_PHYCTL_A33,
981 	.dedicated_clocks = true,
982 	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
983 	.phy0_dual_route = true,
984 };
985 
986 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
987 	.num_phys = 1,
988 	.disc_thresh = 3,
989 	.phyctl_offset = REG_PHYCTL_A33,
990 	.dedicated_clocks = true,
991 	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
992 	.phy0_dual_route = true,
993 };
994 
995 static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
996 	.num_phys = 2,
997 	.phyctl_offset = REG_PHYCTL_A33,
998 	.dedicated_clocks = true,
999 	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1000 	.phy0_dual_route = true,
1001 	.siddq_in_base = true,
1002 };
1003 
1004 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
1005 	.num_phys = 2,
1006 	.disc_thresh = 3,
1007 	.phyctl_offset = REG_PHYCTL_A33,
1008 	.dedicated_clocks = true,
1009 	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
1010 	.phy0_dual_route = true,
1011 };
1012 
1013 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
1014 	.num_phys = 4,
1015 	.phyctl_offset = REG_PHYCTL_A33,
1016 	.dedicated_clocks = true,
1017 	.phy0_dual_route = true,
1018 	.missing_phys = BIT(1) | BIT(2),
1019 	.siddq_in_base = true,
1020 };
1021 
1022 static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
1023 	.num_phys = 4,
1024 	.disc_thresh = 3,
1025 	.phyctl_offset = REG_PHYCTL_A33,
1026 	.dedicated_clocks = true,
1027 	.phy0_dual_route = true,
1028 	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1029 	.needs_phy2_siddq = true,
1030 	.siddq_in_base = true,
1031 };
1032 
1033 static const struct of_device_id sun4i_usb_phy_of_match[] = {
1034 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
1035 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
1036 	{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
1037 	{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
1038 	{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
1039 	{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
1040 	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
1041 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
1042 	{ .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
1043 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
1044 	{ .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
1045 	{ .compatible = "allwinner,sun50i-a64-usb-phy",
1046 	  .data = &sun50i_a64_cfg},
1047 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
1048 	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
1049 	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
1050 	  .data = &suniv_f1c100s_cfg },
1051 	{ },
1052 };
1053 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
1054 
1055 static struct platform_driver sun4i_usb_phy_driver = {
1056 	.probe	= sun4i_usb_phy_probe,
1057 	.remove	= sun4i_usb_phy_remove,
1058 	.driver = {
1059 		.of_match_table	= sun4i_usb_phy_of_match,
1060 		.name  = "sun4i-usb-phy",
1061 	}
1062 };
1063 module_platform_driver(sun4i_usb_phy_driver);
1064 
1065 MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
1066 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
1067 MODULE_LICENSE("GPL v2");
1068