1 /* 2 * Allwinner sun4i USB phy driver 3 * 4 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com> 5 * 6 * Based on code from 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * 9 * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver 10 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 11 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 */ 23 24 #include <linux/clk.h> 25 #include <linux/delay.h> 26 #include <linux/err.h> 27 #include <linux/extcon-provider.h> 28 #include <linux/io.h> 29 #include <linux/interrupt.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/mutex.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_device.h> 36 #include <linux/of_gpio.h> 37 #include <linux/phy/phy.h> 38 #include <linux/phy/phy-sun4i-usb.h> 39 #include <linux/platform_device.h> 40 #include <linux/power_supply.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/reset.h> 43 #include <linux/spinlock.h> 44 #include <linux/usb/of.h> 45 #include <linux/workqueue.h> 46 47 #define REG_ISCR 0x00 48 #define REG_PHYCTL_A10 0x04 49 #define REG_PHYBIST 0x08 50 #define REG_PHYTUNE 0x0c 51 #define REG_PHYCTL_A33 0x10 52 #define REG_PHY_OTGCTL 0x20 53 54 #define REG_PMU_UNK1 0x10 55 56 #define PHYCTL_DATA BIT(7) 57 58 #define OTGCTL_ROUTE_MUSB BIT(0) 59 60 #define SUNXI_AHB_ICHR8_EN BIT(10) 61 #define SUNXI_AHB_INCR4_BURST_EN BIT(9) 62 #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8) 63 #define SUNXI_ULPI_BYPASS_EN BIT(0) 64 65 /* ISCR, Interface Status and Control bits */ 66 #define ISCR_ID_PULLUP_EN (1 << 17) 67 #define ISCR_DPDM_PULLUP_EN (1 << 16) 68 /* sunxi has the phy id/vbus pins not connected, so we use the force bits */ 69 #define ISCR_FORCE_ID_MASK (3 << 14) 70 #define ISCR_FORCE_ID_LOW (2 << 14) 71 #define ISCR_FORCE_ID_HIGH (3 << 14) 72 #define ISCR_FORCE_VBUS_MASK (3 << 12) 73 #define ISCR_FORCE_VBUS_LOW (2 << 12) 74 #define ISCR_FORCE_VBUS_HIGH (3 << 12) 75 76 /* Common Control Bits for Both PHYs */ 77 #define PHY_PLL_BW 0x03 78 #define PHY_RES45_CAL_EN 0x0c 79 80 /* Private Control Bits for Each PHY */ 81 #define PHY_TX_AMPLITUDE_TUNE 0x20 82 #define PHY_TX_SLEWRATE_TUNE 0x22 83 #define PHY_VBUSVALID_TH_SEL 0x25 84 #define PHY_PULLUP_RES_SEL 0x27 85 #define PHY_OTG_FUNC_EN 0x28 86 #define PHY_VBUS_DET_EN 0x29 87 #define PHY_DISCON_TH_SEL 0x2a 88 #define PHY_SQUELCH_DETECT 0x3c 89 90 /* A83T specific control bits for PHY0 */ 91 #define PHY_CTL_VBUSVLDEXT BIT(5) 92 #define PHY_CTL_SIDDQ BIT(3) 93 94 /* A83T specific control bits for PHY2 HSIC */ 95 #define SUNXI_EHCI_HS_FORCE BIT(20) 96 #define SUNXI_HSIC_CONNECT_DET BIT(17) 97 #define SUNXI_HSIC_CONNECT_INT BIT(16) 98 #define SUNXI_HSIC BIT(1) 99 100 #define MAX_PHYS 4 101 102 /* 103 * Note do not raise the debounce time, we must report Vusb high within 100ms 104 * otherwise we get Vbus errors 105 */ 106 #define DEBOUNCE_TIME msecs_to_jiffies(50) 107 #define POLL_TIME msecs_to_jiffies(250) 108 109 enum sun4i_usb_phy_type { 110 sun4i_a10_phy, 111 sun6i_a31_phy, 112 sun8i_a33_phy, 113 sun8i_a83t_phy, 114 sun8i_h3_phy, 115 sun8i_r40_phy, 116 sun8i_v3s_phy, 117 sun50i_a64_phy, 118 }; 119 120 struct sun4i_usb_phy_cfg { 121 int num_phys; 122 int hsic_index; 123 enum sun4i_usb_phy_type type; 124 u32 disc_thresh; 125 u8 phyctl_offset; 126 bool dedicated_clocks; 127 bool enable_pmu_unk1; 128 bool phy0_dual_route; 129 }; 130 131 struct sun4i_usb_phy_data { 132 void __iomem *base; 133 const struct sun4i_usb_phy_cfg *cfg; 134 enum usb_dr_mode dr_mode; 135 spinlock_t reg_lock; /* guard access to phyctl reg */ 136 struct sun4i_usb_phy { 137 struct phy *phy; 138 void __iomem *pmu; 139 struct regulator *vbus; 140 struct reset_control *reset; 141 struct clk *clk; 142 struct clk *clk2; 143 bool regulator_on; 144 int index; 145 } phys[MAX_PHYS]; 146 /* phy0 / otg related variables */ 147 struct extcon_dev *extcon; 148 bool phy0_init; 149 struct gpio_desc *id_det_gpio; 150 struct gpio_desc *vbus_det_gpio; 151 struct power_supply *vbus_power_supply; 152 struct notifier_block vbus_power_nb; 153 bool vbus_power_nb_registered; 154 bool force_session_end; 155 int id_det_irq; 156 int vbus_det_irq; 157 int id_det; 158 int vbus_det; 159 struct delayed_work detect; 160 }; 161 162 #define to_sun4i_usb_phy_data(phy) \ 163 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index]) 164 165 static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set) 166 { 167 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); 168 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); 169 u32 iscr; 170 171 iscr = readl(data->base + REG_ISCR); 172 iscr &= ~clr; 173 iscr |= set; 174 writel(iscr, data->base + REG_ISCR); 175 } 176 177 static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val) 178 { 179 if (val) 180 val = ISCR_FORCE_ID_HIGH; 181 else 182 val = ISCR_FORCE_ID_LOW; 183 184 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val); 185 } 186 187 static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val) 188 { 189 if (val) 190 val = ISCR_FORCE_VBUS_HIGH; 191 else 192 val = ISCR_FORCE_VBUS_LOW; 193 194 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val); 195 } 196 197 static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data, 198 int len) 199 { 200 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy); 201 u32 temp, usbc_bit = BIT(phy->index * 2); 202 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset; 203 unsigned long flags; 204 int i; 205 206 spin_lock_irqsave(&phy_data->reg_lock, flags); 207 208 if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) { 209 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */ 210 writel(0, phyctl); 211 } 212 213 for (i = 0; i < len; i++) { 214 temp = readl(phyctl); 215 216 /* clear the address portion */ 217 temp &= ~(0xff << 8); 218 219 /* set the address */ 220 temp |= ((addr + i) << 8); 221 writel(temp, phyctl); 222 223 /* set the data bit and clear usbc bit*/ 224 temp = readb(phyctl); 225 if (data & 0x1) 226 temp |= PHYCTL_DATA; 227 else 228 temp &= ~PHYCTL_DATA; 229 temp &= ~usbc_bit; 230 writeb(temp, phyctl); 231 232 /* pulse usbc_bit */ 233 temp = readb(phyctl); 234 temp |= usbc_bit; 235 writeb(temp, phyctl); 236 237 temp = readb(phyctl); 238 temp &= ~usbc_bit; 239 writeb(temp, phyctl); 240 241 data >>= 1; 242 } 243 244 spin_unlock_irqrestore(&phy_data->reg_lock, flags); 245 } 246 247 static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable) 248 { 249 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy); 250 u32 bits, reg_value; 251 252 if (!phy->pmu) 253 return; 254 255 bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN | 256 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN; 257 258 /* A83T USB2 is HSIC */ 259 if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2) 260 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT | 261 SUNXI_HSIC; 262 263 reg_value = readl(phy->pmu); 264 265 if (enable) 266 reg_value |= bits; 267 else 268 reg_value &= ~bits; 269 270 writel(reg_value, phy->pmu); 271 } 272 273 static int sun4i_usb_phy_init(struct phy *_phy) 274 { 275 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); 276 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); 277 int ret; 278 u32 val; 279 280 ret = clk_prepare_enable(phy->clk); 281 if (ret) 282 return ret; 283 284 ret = clk_prepare_enable(phy->clk2); 285 if (ret) { 286 clk_disable_unprepare(phy->clk); 287 return ret; 288 } 289 290 ret = reset_control_deassert(phy->reset); 291 if (ret) { 292 clk_disable_unprepare(phy->clk2); 293 clk_disable_unprepare(phy->clk); 294 return ret; 295 } 296 297 if (data->cfg->type == sun8i_a83t_phy) { 298 if (phy->index == 0) { 299 val = readl(data->base + data->cfg->phyctl_offset); 300 val |= PHY_CTL_VBUSVLDEXT; 301 val &= ~PHY_CTL_SIDDQ; 302 writel(val, data->base + data->cfg->phyctl_offset); 303 } 304 } else { 305 if (phy->pmu && data->cfg->enable_pmu_unk1) { 306 val = readl(phy->pmu + REG_PMU_UNK1); 307 writel(val & ~2, phy->pmu + REG_PMU_UNK1); 308 } 309 310 /* Enable USB 45 Ohm resistor calibration */ 311 if (phy->index == 0) 312 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); 313 314 /* Adjust PHY's magnitude and rate */ 315 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); 316 317 /* Disconnect threshold adjustment */ 318 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, 319 data->cfg->disc_thresh, 2); 320 } 321 322 sun4i_usb_phy_passby(phy, 1); 323 324 if (phy->index == 0) { 325 data->phy0_init = true; 326 327 /* Enable pull-ups */ 328 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN); 329 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN); 330 331 /* Force ISCR and cable state updates */ 332 data->id_det = -1; 333 data->vbus_det = -1; 334 queue_delayed_work(system_wq, &data->detect, 0); 335 } 336 337 return 0; 338 } 339 340 static int sun4i_usb_phy_exit(struct phy *_phy) 341 { 342 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); 343 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); 344 345 if (phy->index == 0) { 346 if (data->cfg->type == sun8i_a83t_phy) { 347 void __iomem *phyctl = data->base + 348 data->cfg->phyctl_offset; 349 350 writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl); 351 } 352 353 /* Disable pull-ups */ 354 sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0); 355 sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0); 356 data->phy0_init = false; 357 } 358 359 sun4i_usb_phy_passby(phy, 0); 360 reset_control_assert(phy->reset); 361 clk_disable_unprepare(phy->clk2); 362 clk_disable_unprepare(phy->clk); 363 364 return 0; 365 } 366 367 static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data) 368 { 369 switch (data->dr_mode) { 370 case USB_DR_MODE_OTG: 371 if (data->id_det_gpio) 372 return gpiod_get_value_cansleep(data->id_det_gpio); 373 else 374 return 1; /* Fallback to peripheral mode */ 375 case USB_DR_MODE_HOST: 376 return 0; 377 case USB_DR_MODE_PERIPHERAL: 378 default: 379 return 1; 380 } 381 } 382 383 static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data) 384 { 385 if (data->vbus_det_gpio) 386 return gpiod_get_value_cansleep(data->vbus_det_gpio); 387 388 if (data->vbus_power_supply) { 389 union power_supply_propval val; 390 int r; 391 392 r = power_supply_get_property(data->vbus_power_supply, 393 POWER_SUPPLY_PROP_PRESENT, &val); 394 if (r == 0) 395 return val.intval; 396 } 397 398 /* Fallback: report vbus as high */ 399 return 1; 400 } 401 402 static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data) 403 { 404 return data->vbus_det_gpio || data->vbus_power_supply; 405 } 406 407 static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data) 408 { 409 if ((data->id_det_gpio && data->id_det_irq <= 0) || 410 (data->vbus_det_gpio && data->vbus_det_irq <= 0)) 411 return true; 412 413 /* 414 * The A31/A23/A33 companion pmics (AXP221/AXP223) do not 415 * generate vbus change interrupts when the board is driving 416 * vbus using the N_VBUSEN pin on the pmic, so we must poll 417 * when using the pmic for vbus-det _and_ we're driving vbus. 418 */ 419 if ((data->cfg->type == sun6i_a31_phy || 420 data->cfg->type == sun8i_a33_phy) && 421 data->vbus_power_supply && data->phys[0].regulator_on) 422 return true; 423 424 return false; 425 } 426 427 static int sun4i_usb_phy_power_on(struct phy *_phy) 428 { 429 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); 430 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); 431 int ret; 432 433 if (!phy->vbus || phy->regulator_on) 434 return 0; 435 436 /* For phy0 only turn on Vbus if we don't have an ext. Vbus */ 437 if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) && 438 data->vbus_det) { 439 dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n"); 440 return 0; 441 } 442 443 ret = regulator_enable(phy->vbus); 444 if (ret) 445 return ret; 446 447 phy->regulator_on = true; 448 449 /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */ 450 if (phy->index == 0 && sun4i_usb_phy0_poll(data)) 451 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME); 452 453 return 0; 454 } 455 456 static int sun4i_usb_phy_power_off(struct phy *_phy) 457 { 458 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); 459 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); 460 461 if (!phy->vbus || !phy->regulator_on) 462 return 0; 463 464 regulator_disable(phy->vbus); 465 phy->regulator_on = false; 466 467 /* 468 * phy0 vbus typically slowly discharges, sometimes this causes the 469 * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan. 470 */ 471 if (phy->index == 0 && !sun4i_usb_phy0_poll(data)) 472 mod_delayed_work(system_wq, &data->detect, POLL_TIME); 473 474 return 0; 475 } 476 477 static int sun4i_usb_phy_set_mode(struct phy *_phy, enum phy_mode mode) 478 { 479 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); 480 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); 481 int new_mode; 482 483 if (phy->index != 0) 484 return -EINVAL; 485 486 switch (mode) { 487 case PHY_MODE_USB_HOST: 488 new_mode = USB_DR_MODE_HOST; 489 break; 490 case PHY_MODE_USB_DEVICE: 491 new_mode = USB_DR_MODE_PERIPHERAL; 492 break; 493 case PHY_MODE_USB_OTG: 494 new_mode = USB_DR_MODE_OTG; 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 if (new_mode != data->dr_mode) { 501 dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode); 502 data->dr_mode = new_mode; 503 } 504 505 data->id_det = -1; /* Force reprocessing of id */ 506 data->force_session_end = true; 507 queue_delayed_work(system_wq, &data->detect, 0); 508 509 return 0; 510 } 511 512 void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled) 513 { 514 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); 515 516 sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2); 517 } 518 EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect); 519 520 static const struct phy_ops sun4i_usb_phy_ops = { 521 .init = sun4i_usb_phy_init, 522 .exit = sun4i_usb_phy_exit, 523 .power_on = sun4i_usb_phy_power_on, 524 .power_off = sun4i_usb_phy_power_off, 525 .set_mode = sun4i_usb_phy_set_mode, 526 .owner = THIS_MODULE, 527 }; 528 529 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det) 530 { 531 u32 regval; 532 533 regval = readl(data->base + REG_PHY_OTGCTL); 534 if (id_det == 0) { 535 /* Host mode. Route phy0 to EHCI/OHCI */ 536 regval &= ~OTGCTL_ROUTE_MUSB; 537 } else { 538 /* Peripheral mode. Route phy0 to MUSB */ 539 regval |= OTGCTL_ROUTE_MUSB; 540 } 541 writel(regval, data->base + REG_PHY_OTGCTL); 542 } 543 544 static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work) 545 { 546 struct sun4i_usb_phy_data *data = 547 container_of(work, struct sun4i_usb_phy_data, detect.work); 548 struct phy *phy0 = data->phys[0].phy; 549 bool force_session_end, id_notify = false, vbus_notify = false; 550 int id_det, vbus_det; 551 552 if (phy0 == NULL) 553 return; 554 555 id_det = sun4i_usb_phy0_get_id_det(data); 556 vbus_det = sun4i_usb_phy0_get_vbus_det(data); 557 558 mutex_lock(&phy0->mutex); 559 560 if (!data->phy0_init) { 561 mutex_unlock(&phy0->mutex); 562 return; 563 } 564 565 force_session_end = data->force_session_end; 566 data->force_session_end = false; 567 568 if (id_det != data->id_det) { 569 /* id-change, force session end if we've no vbus detection */ 570 if (data->dr_mode == USB_DR_MODE_OTG && 571 !sun4i_usb_phy0_have_vbus_det(data)) 572 force_session_end = true; 573 574 /* When entering host mode (id = 0) force end the session now */ 575 if (force_session_end && id_det == 0) { 576 sun4i_usb_phy0_set_vbus_detect(phy0, 0); 577 msleep(200); 578 sun4i_usb_phy0_set_vbus_detect(phy0, 1); 579 } 580 sun4i_usb_phy0_set_id_detect(phy0, id_det); 581 data->id_det = id_det; 582 id_notify = true; 583 } 584 585 if (vbus_det != data->vbus_det) { 586 sun4i_usb_phy0_set_vbus_detect(phy0, vbus_det); 587 data->vbus_det = vbus_det; 588 vbus_notify = true; 589 } 590 591 mutex_unlock(&phy0->mutex); 592 593 if (id_notify) { 594 extcon_set_state_sync(data->extcon, EXTCON_USB_HOST, 595 !id_det); 596 /* When leaving host mode force end the session here */ 597 if (force_session_end && id_det == 1) { 598 mutex_lock(&phy0->mutex); 599 sun4i_usb_phy0_set_vbus_detect(phy0, 0); 600 msleep(1000); 601 sun4i_usb_phy0_set_vbus_detect(phy0, 1); 602 mutex_unlock(&phy0->mutex); 603 } 604 605 /* Re-route PHY0 if necessary */ 606 if (data->cfg->phy0_dual_route) 607 sun4i_usb_phy0_reroute(data, id_det); 608 } 609 610 if (vbus_notify) 611 extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det); 612 613 if (sun4i_usb_phy0_poll(data)) 614 queue_delayed_work(system_wq, &data->detect, POLL_TIME); 615 } 616 617 static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id) 618 { 619 struct sun4i_usb_phy_data *data = dev_id; 620 621 /* vbus or id changed, let the pins settle and then scan them */ 622 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME); 623 624 return IRQ_HANDLED; 625 } 626 627 static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb, 628 unsigned long val, void *v) 629 { 630 struct sun4i_usb_phy_data *data = 631 container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb); 632 struct power_supply *psy = v; 633 634 /* Properties on the vbus_power_supply changed, scan vbus_det */ 635 if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply) 636 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME); 637 638 return NOTIFY_OK; 639 } 640 641 static struct phy *sun4i_usb_phy_xlate(struct device *dev, 642 struct of_phandle_args *args) 643 { 644 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev); 645 646 if (args->args[0] >= data->cfg->num_phys) 647 return ERR_PTR(-ENODEV); 648 649 return data->phys[args->args[0]].phy; 650 } 651 652 static int sun4i_usb_phy_remove(struct platform_device *pdev) 653 { 654 struct device *dev = &pdev->dev; 655 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev); 656 657 if (data->vbus_power_nb_registered) 658 power_supply_unreg_notifier(&data->vbus_power_nb); 659 if (data->id_det_irq > 0) 660 devm_free_irq(dev, data->id_det_irq, data); 661 if (data->vbus_det_irq > 0) 662 devm_free_irq(dev, data->vbus_det_irq, data); 663 664 cancel_delayed_work_sync(&data->detect); 665 666 return 0; 667 } 668 669 static const unsigned int sun4i_usb_phy0_cable[] = { 670 EXTCON_USB, 671 EXTCON_USB_HOST, 672 EXTCON_NONE, 673 }; 674 675 static int sun4i_usb_phy_probe(struct platform_device *pdev) 676 { 677 struct sun4i_usb_phy_data *data; 678 struct device *dev = &pdev->dev; 679 struct device_node *np = dev->of_node; 680 struct phy_provider *phy_provider; 681 struct resource *res; 682 int i, ret; 683 684 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 685 if (!data) 686 return -ENOMEM; 687 688 spin_lock_init(&data->reg_lock); 689 INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan); 690 dev_set_drvdata(dev, data); 691 data->cfg = of_device_get_match_data(dev); 692 if (!data->cfg) 693 return -EINVAL; 694 695 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl"); 696 data->base = devm_ioremap_resource(dev, res); 697 if (IS_ERR(data->base)) 698 return PTR_ERR(data->base); 699 700 data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det", 701 GPIOD_IN); 702 if (IS_ERR(data->id_det_gpio)) { 703 dev_err(dev, "Couldn't request ID GPIO\n"); 704 return PTR_ERR(data->id_det_gpio); 705 } 706 707 data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det", 708 GPIOD_IN); 709 if (IS_ERR(data->vbus_det_gpio)) { 710 dev_err(dev, "Couldn't request VBUS detect GPIO\n"); 711 return PTR_ERR(data->vbus_det_gpio); 712 } 713 714 if (of_find_property(np, "usb0_vbus_power-supply", NULL)) { 715 data->vbus_power_supply = devm_power_supply_get_by_phandle(dev, 716 "usb0_vbus_power-supply"); 717 if (IS_ERR(data->vbus_power_supply)) { 718 dev_err(dev, "Couldn't get the VBUS power supply\n"); 719 return PTR_ERR(data->vbus_power_supply); 720 } 721 722 if (!data->vbus_power_supply) 723 return -EPROBE_DEFER; 724 } 725 726 data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0); 727 728 data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable); 729 if (IS_ERR(data->extcon)) { 730 dev_err(dev, "Couldn't allocate our extcon device\n"); 731 return PTR_ERR(data->extcon); 732 } 733 734 ret = devm_extcon_dev_register(dev, data->extcon); 735 if (ret) { 736 dev_err(dev, "failed to register extcon: %d\n", ret); 737 return ret; 738 } 739 740 for (i = 0; i < data->cfg->num_phys; i++) { 741 struct sun4i_usb_phy *phy = data->phys + i; 742 char name[16]; 743 744 snprintf(name, sizeof(name), "usb%d_vbus", i); 745 phy->vbus = devm_regulator_get_optional(dev, name); 746 if (IS_ERR(phy->vbus)) { 747 if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) { 748 dev_err(dev, 749 "Couldn't get regulator %s... Deferring probe\n", 750 name); 751 return -EPROBE_DEFER; 752 } 753 754 phy->vbus = NULL; 755 } 756 757 if (data->cfg->dedicated_clocks) 758 snprintf(name, sizeof(name), "usb%d_phy", i); 759 else 760 strlcpy(name, "usb_phy", sizeof(name)); 761 762 phy->clk = devm_clk_get(dev, name); 763 if (IS_ERR(phy->clk)) { 764 dev_err(dev, "failed to get clock %s\n", name); 765 return PTR_ERR(phy->clk); 766 } 767 768 /* The first PHY is always tied to OTG, and never HSIC */ 769 if (data->cfg->hsic_index && i == data->cfg->hsic_index) { 770 /* HSIC needs secondary clock */ 771 snprintf(name, sizeof(name), "usb%d_hsic_12M", i); 772 phy->clk2 = devm_clk_get(dev, name); 773 if (IS_ERR(phy->clk2)) { 774 dev_err(dev, "failed to get clock %s\n", name); 775 return PTR_ERR(phy->clk2); 776 } 777 } 778 779 snprintf(name, sizeof(name), "usb%d_reset", i); 780 phy->reset = devm_reset_control_get(dev, name); 781 if (IS_ERR(phy->reset)) { 782 dev_err(dev, "failed to get reset %s\n", name); 783 return PTR_ERR(phy->reset); 784 } 785 786 if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */ 787 snprintf(name, sizeof(name), "pmu%d", i); 788 res = platform_get_resource_byname(pdev, 789 IORESOURCE_MEM, name); 790 phy->pmu = devm_ioremap_resource(dev, res); 791 if (IS_ERR(phy->pmu)) 792 return PTR_ERR(phy->pmu); 793 } 794 795 phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops); 796 if (IS_ERR(phy->phy)) { 797 dev_err(dev, "failed to create PHY %d\n", i); 798 return PTR_ERR(phy->phy); 799 } 800 801 phy->index = i; 802 phy_set_drvdata(phy->phy, &data->phys[i]); 803 } 804 805 data->id_det_irq = gpiod_to_irq(data->id_det_gpio); 806 if (data->id_det_irq > 0) { 807 ret = devm_request_irq(dev, data->id_det_irq, 808 sun4i_usb_phy0_id_vbus_det_irq, 809 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 810 "usb0-id-det", data); 811 if (ret) { 812 dev_err(dev, "Err requesting id-det-irq: %d\n", ret); 813 return ret; 814 } 815 } 816 817 data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio); 818 if (data->vbus_det_irq > 0) { 819 ret = devm_request_irq(dev, data->vbus_det_irq, 820 sun4i_usb_phy0_id_vbus_det_irq, 821 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 822 "usb0-vbus-det", data); 823 if (ret) { 824 dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret); 825 data->vbus_det_irq = -1; 826 sun4i_usb_phy_remove(pdev); /* Stop detect work */ 827 return ret; 828 } 829 } 830 831 if (data->vbus_power_supply) { 832 data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify; 833 data->vbus_power_nb.priority = 0; 834 ret = power_supply_reg_notifier(&data->vbus_power_nb); 835 if (ret) { 836 sun4i_usb_phy_remove(pdev); /* Stop detect work */ 837 return ret; 838 } 839 data->vbus_power_nb_registered = true; 840 } 841 842 phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate); 843 if (IS_ERR(phy_provider)) { 844 sun4i_usb_phy_remove(pdev); /* Stop detect work */ 845 return PTR_ERR(phy_provider); 846 } 847 848 dev_dbg(dev, "successfully loaded\n"); 849 850 return 0; 851 } 852 853 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { 854 .num_phys = 3, 855 .type = sun4i_a10_phy, 856 .disc_thresh = 3, 857 .phyctl_offset = REG_PHYCTL_A10, 858 .dedicated_clocks = false, 859 .enable_pmu_unk1 = false, 860 }; 861 862 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { 863 .num_phys = 2, 864 .type = sun4i_a10_phy, 865 .disc_thresh = 2, 866 .phyctl_offset = REG_PHYCTL_A10, 867 .dedicated_clocks = false, 868 .enable_pmu_unk1 = false, 869 }; 870 871 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { 872 .num_phys = 3, 873 .type = sun6i_a31_phy, 874 .disc_thresh = 3, 875 .phyctl_offset = REG_PHYCTL_A10, 876 .dedicated_clocks = true, 877 .enable_pmu_unk1 = false, 878 }; 879 880 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { 881 .num_phys = 3, 882 .type = sun4i_a10_phy, 883 .disc_thresh = 2, 884 .phyctl_offset = REG_PHYCTL_A10, 885 .dedicated_clocks = false, 886 .enable_pmu_unk1 = false, 887 }; 888 889 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { 890 .num_phys = 2, 891 .type = sun6i_a31_phy, 892 .disc_thresh = 3, 893 .phyctl_offset = REG_PHYCTL_A10, 894 .dedicated_clocks = true, 895 .enable_pmu_unk1 = false, 896 }; 897 898 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { 899 .num_phys = 2, 900 .type = sun8i_a33_phy, 901 .disc_thresh = 3, 902 .phyctl_offset = REG_PHYCTL_A33, 903 .dedicated_clocks = true, 904 .enable_pmu_unk1 = false, 905 }; 906 907 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { 908 .num_phys = 3, 909 .hsic_index = 2, 910 .type = sun8i_a83t_phy, 911 .phyctl_offset = REG_PHYCTL_A33, 912 .dedicated_clocks = true, 913 }; 914 915 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { 916 .num_phys = 4, 917 .type = sun8i_h3_phy, 918 .disc_thresh = 3, 919 .phyctl_offset = REG_PHYCTL_A33, 920 .dedicated_clocks = true, 921 .enable_pmu_unk1 = true, 922 .phy0_dual_route = true, 923 }; 924 925 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { 926 .num_phys = 3, 927 .type = sun8i_r40_phy, 928 .disc_thresh = 3, 929 .phyctl_offset = REG_PHYCTL_A33, 930 .dedicated_clocks = true, 931 .enable_pmu_unk1 = true, 932 .phy0_dual_route = true, 933 }; 934 935 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { 936 .num_phys = 1, 937 .type = sun8i_v3s_phy, 938 .disc_thresh = 3, 939 .phyctl_offset = REG_PHYCTL_A33, 940 .dedicated_clocks = true, 941 .enable_pmu_unk1 = true, 942 .phy0_dual_route = true, 943 }; 944 945 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { 946 .num_phys = 2, 947 .type = sun50i_a64_phy, 948 .disc_thresh = 3, 949 .phyctl_offset = REG_PHYCTL_A33, 950 .dedicated_clocks = true, 951 .enable_pmu_unk1 = true, 952 .phy0_dual_route = true, 953 }; 954 955 static const struct of_device_id sun4i_usb_phy_of_match[] = { 956 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg }, 957 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg }, 958 { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg }, 959 { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg }, 960 { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg }, 961 { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg }, 962 { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg }, 963 { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg }, 964 { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg }, 965 { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg }, 966 { .compatible = "allwinner,sun50i-a64-usb-phy", 967 .data = &sun50i_a64_cfg}, 968 { }, 969 }; 970 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match); 971 972 static struct platform_driver sun4i_usb_phy_driver = { 973 .probe = sun4i_usb_phy_probe, 974 .remove = sun4i_usb_phy_remove, 975 .driver = { 976 .of_match_table = sun4i_usb_phy_of_match, 977 .name = "sun4i-usb-phy", 978 } 979 }; 980 module_platform_driver(sun4i_usb_phy_driver); 981 982 MODULE_DESCRIPTION("Allwinner sun4i USB phy driver"); 983 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 984 MODULE_LICENSE("GPL v2"); 985