1 /* 2 * APM X-Gene SoC PMU (Performance Monitor Unit) 3 * 4 * Copyright (c) 2016, Applied Micro Circuits Corporation 5 * Author: Hoan Tran <hotran@apm.com> 6 * Tai Nguyen <ttnguyen@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/acpi.h> 23 #include <linux/clk.h> 24 #include <linux/cpumask.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/module.h> 29 #include <linux/of_address.h> 30 #include <linux/of_fdt.h> 31 #include <linux/of_irq.h> 32 #include <linux/of_platform.h> 33 #include <linux/perf_event.h> 34 #include <linux/platform_device.h> 35 #include <linux/regmap.h> 36 #include <linux/slab.h> 37 38 #define CSW_CSWCR 0x0000 39 #define CSW_CSWCR_DUALMCB_MASK BIT(0) 40 #define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0x0C) >> 2) 41 #define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0x30) >> 4) 42 #define MCBADDRMR 0x0000 43 #define MCBADDRMR_DUALMCU_MODE_MASK BIT(2) 44 45 #define PCPPMU_INTSTATUS_REG 0x000 46 #define PCPPMU_INTMASK_REG 0x004 47 #define PCPPMU_INTMASK 0x0000000F 48 #define PCPPMU_INTENMASK 0xFFFFFFFF 49 #define PCPPMU_INTCLRMASK 0xFFFFFFF0 50 #define PCPPMU_INT_MCU BIT(0) 51 #define PCPPMU_INT_MCB BIT(1) 52 #define PCPPMU_INT_L3C BIT(2) 53 #define PCPPMU_INT_IOB BIT(3) 54 55 #define PCPPMU_V3_INTMASK 0x00FF33FF 56 #define PCPPMU_V3_INTENMASK 0xFFFFFFFF 57 #define PCPPMU_V3_INTCLRMASK 0xFF00CC00 58 #define PCPPMU_V3_INT_MCU 0x000000FF 59 #define PCPPMU_V3_INT_MCB 0x00000300 60 #define PCPPMU_V3_INT_L3C 0x00FF0000 61 #define PCPPMU_V3_INT_IOB 0x00003000 62 63 #define PMU_MAX_COUNTERS 4 64 #define PMU_CNT_MAX_PERIOD 0xFFFFFFFFULL 65 #define PMU_V3_CNT_MAX_PERIOD 0xFFFFFFFFFFFFFFFFULL 66 #define PMU_OVERFLOW_MASK 0xF 67 #define PMU_PMCR_E BIT(0) 68 #define PMU_PMCR_P BIT(1) 69 70 #define PMU_PMEVCNTR0 0x000 71 #define PMU_PMEVCNTR1 0x004 72 #define PMU_PMEVCNTR2 0x008 73 #define PMU_PMEVCNTR3 0x00C 74 #define PMU_PMEVTYPER0 0x400 75 #define PMU_PMEVTYPER1 0x404 76 #define PMU_PMEVTYPER2 0x408 77 #define PMU_PMEVTYPER3 0x40C 78 #define PMU_PMAMR0 0xA00 79 #define PMU_PMAMR1 0xA04 80 #define PMU_PMCNTENSET 0xC00 81 #define PMU_PMCNTENCLR 0xC20 82 #define PMU_PMINTENSET 0xC40 83 #define PMU_PMINTENCLR 0xC60 84 #define PMU_PMOVSR 0xC80 85 #define PMU_PMCR 0xE04 86 87 /* PMU registers for V3 */ 88 #define PMU_PMOVSCLR 0xC80 89 #define PMU_PMOVSSET 0xCC0 90 91 #define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu) 92 #define GET_CNTR(ev) (ev->hw.idx) 93 #define GET_EVENTID(ev) (ev->hw.config & 0xFFULL) 94 #define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL) 95 #define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL) 96 97 struct hw_pmu_info { 98 u32 type; 99 u32 enable_mask; 100 void __iomem *csr; 101 }; 102 103 struct xgene_pmu_dev { 104 struct hw_pmu_info *inf; 105 struct xgene_pmu *parent; 106 struct pmu pmu; 107 u8 max_counters; 108 DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS); 109 u64 max_period; 110 const struct attribute_group **attr_groups; 111 struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS]; 112 }; 113 114 struct xgene_pmu_ops { 115 void (*mask_int)(struct xgene_pmu *pmu); 116 void (*unmask_int)(struct xgene_pmu *pmu); 117 u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx); 118 void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val); 119 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val); 120 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val); 121 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val); 122 void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx); 123 void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx); 124 void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx); 125 void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx); 126 void (*reset_counters)(struct xgene_pmu_dev *pmu_dev); 127 void (*start_counters)(struct xgene_pmu_dev *pmu_dev); 128 void (*stop_counters)(struct xgene_pmu_dev *pmu_dev); 129 }; 130 131 struct xgene_pmu { 132 struct device *dev; 133 int version; 134 void __iomem *pcppmu_csr; 135 u32 mcb_active_mask; 136 u32 mc_active_mask; 137 u32 l3c_active_mask; 138 cpumask_t cpu; 139 raw_spinlock_t lock; 140 const struct xgene_pmu_ops *ops; 141 struct list_head l3cpmus; 142 struct list_head iobpmus; 143 struct list_head mcbpmus; 144 struct list_head mcpmus; 145 }; 146 147 struct xgene_pmu_dev_ctx { 148 char *name; 149 struct list_head next; 150 struct xgene_pmu_dev *pmu_dev; 151 struct hw_pmu_info inf; 152 }; 153 154 struct xgene_pmu_data { 155 int id; 156 u32 data; 157 }; 158 159 enum xgene_pmu_version { 160 PCP_PMU_V1 = 1, 161 PCP_PMU_V2, 162 PCP_PMU_V3, 163 }; 164 165 enum xgene_pmu_dev_type { 166 PMU_TYPE_L3C = 0, 167 PMU_TYPE_IOB, 168 PMU_TYPE_IOB_SLOW, 169 PMU_TYPE_MCB, 170 PMU_TYPE_MC, 171 }; 172 173 /* 174 * sysfs format attributes 175 */ 176 static ssize_t xgene_pmu_format_show(struct device *dev, 177 struct device_attribute *attr, char *buf) 178 { 179 struct dev_ext_attribute *eattr; 180 181 eattr = container_of(attr, struct dev_ext_attribute, attr); 182 return sprintf(buf, "%s\n", (char *) eattr->var); 183 } 184 185 #define XGENE_PMU_FORMAT_ATTR(_name, _config) \ 186 (&((struct dev_ext_attribute[]) { \ 187 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \ 188 .var = (void *) _config, } \ 189 })[0].attr.attr) 190 191 static struct attribute *l3c_pmu_format_attrs[] = { 192 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"), 193 XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"), 194 NULL, 195 }; 196 197 static struct attribute *iob_pmu_format_attrs[] = { 198 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"), 199 XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"), 200 NULL, 201 }; 202 203 static struct attribute *mcb_pmu_format_attrs[] = { 204 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"), 205 XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"), 206 NULL, 207 }; 208 209 static struct attribute *mc_pmu_format_attrs[] = { 210 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"), 211 NULL, 212 }; 213 214 static const struct attribute_group l3c_pmu_format_attr_group = { 215 .name = "format", 216 .attrs = l3c_pmu_format_attrs, 217 }; 218 219 static const struct attribute_group iob_pmu_format_attr_group = { 220 .name = "format", 221 .attrs = iob_pmu_format_attrs, 222 }; 223 224 static const struct attribute_group mcb_pmu_format_attr_group = { 225 .name = "format", 226 .attrs = mcb_pmu_format_attrs, 227 }; 228 229 static const struct attribute_group mc_pmu_format_attr_group = { 230 .name = "format", 231 .attrs = mc_pmu_format_attrs, 232 }; 233 234 static struct attribute *l3c_pmu_v3_format_attrs[] = { 235 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"), 236 NULL, 237 }; 238 239 static struct attribute *iob_pmu_v3_format_attrs[] = { 240 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"), 241 NULL, 242 }; 243 244 static struct attribute *iob_slow_pmu_v3_format_attrs[] = { 245 XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"), 246 NULL, 247 }; 248 249 static struct attribute *mcb_pmu_v3_format_attrs[] = { 250 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"), 251 NULL, 252 }; 253 254 static struct attribute *mc_pmu_v3_format_attrs[] = { 255 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"), 256 NULL, 257 }; 258 259 static const struct attribute_group l3c_pmu_v3_format_attr_group = { 260 .name = "format", 261 .attrs = l3c_pmu_v3_format_attrs, 262 }; 263 264 static const struct attribute_group iob_pmu_v3_format_attr_group = { 265 .name = "format", 266 .attrs = iob_pmu_v3_format_attrs, 267 }; 268 269 static const struct attribute_group iob_slow_pmu_v3_format_attr_group = { 270 .name = "format", 271 .attrs = iob_slow_pmu_v3_format_attrs, 272 }; 273 274 static const struct attribute_group mcb_pmu_v3_format_attr_group = { 275 .name = "format", 276 .attrs = mcb_pmu_v3_format_attrs, 277 }; 278 279 static const struct attribute_group mc_pmu_v3_format_attr_group = { 280 .name = "format", 281 .attrs = mc_pmu_v3_format_attrs, 282 }; 283 284 /* 285 * sysfs event attributes 286 */ 287 static ssize_t xgene_pmu_event_show(struct device *dev, 288 struct device_attribute *attr, char *buf) 289 { 290 struct dev_ext_attribute *eattr; 291 292 eattr = container_of(attr, struct dev_ext_attribute, attr); 293 return sprintf(buf, "config=0x%lx\n", (unsigned long) eattr->var); 294 } 295 296 #define XGENE_PMU_EVENT_ATTR(_name, _config) \ 297 (&((struct dev_ext_attribute[]) { \ 298 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_event_show, NULL), \ 299 .var = (void *) _config, } \ 300 })[0].attr.attr) 301 302 static struct attribute *l3c_pmu_events_attrs[] = { 303 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 304 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 305 XGENE_PMU_EVENT_ATTR(read-hit, 0x02), 306 XGENE_PMU_EVENT_ATTR(read-miss, 0x03), 307 XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06), 308 XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07), 309 XGENE_PMU_EVENT_ATTR(tq-full, 0x08), 310 XGENE_PMU_EVENT_ATTR(ackq-full, 0x09), 311 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a), 312 XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b), 313 XGENE_PMU_EVENT_ATTR(odb-full, 0x0c), 314 XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d), 315 XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e), 316 XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f), 317 NULL, 318 }; 319 320 static struct attribute *iob_pmu_events_attrs[] = { 321 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 322 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 323 XGENE_PMU_EVENT_ATTR(axi0-read, 0x02), 324 XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03), 325 XGENE_PMU_EVENT_ATTR(axi1-read, 0x04), 326 XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05), 327 XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06), 328 XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07), 329 XGENE_PMU_EVENT_ATTR(axi0-write, 0x10), 330 XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11), 331 XGENE_PMU_EVENT_ATTR(axi1-write, 0x13), 332 XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14), 333 XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16), 334 NULL, 335 }; 336 337 static struct attribute *mcb_pmu_events_attrs[] = { 338 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 339 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 340 XGENE_PMU_EVENT_ATTR(csw-read, 0x02), 341 XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03), 342 XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04), 343 XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05), 344 NULL, 345 }; 346 347 static struct attribute *mc_pmu_events_attrs[] = { 348 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 349 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 350 XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02), 351 XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03), 352 XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04), 353 XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05), 354 XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06), 355 XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07), 356 XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08), 357 XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09), 358 XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a), 359 XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b), 360 XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c), 361 XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d), 362 XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e), 363 XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f), 364 XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10), 365 XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11), 366 XGENE_PMU_EVENT_ATTR(mcu-request, 0x12), 367 XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13), 368 XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14), 369 XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15), 370 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16), 371 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17), 372 XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18), 373 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19), 374 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a), 375 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b), 376 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c), 377 NULL, 378 }; 379 380 static const struct attribute_group l3c_pmu_events_attr_group = { 381 .name = "events", 382 .attrs = l3c_pmu_events_attrs, 383 }; 384 385 static const struct attribute_group iob_pmu_events_attr_group = { 386 .name = "events", 387 .attrs = iob_pmu_events_attrs, 388 }; 389 390 static const struct attribute_group mcb_pmu_events_attr_group = { 391 .name = "events", 392 .attrs = mcb_pmu_events_attrs, 393 }; 394 395 static const struct attribute_group mc_pmu_events_attr_group = { 396 .name = "events", 397 .attrs = mc_pmu_events_attrs, 398 }; 399 400 static struct attribute *l3c_pmu_v3_events_attrs[] = { 401 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 402 XGENE_PMU_EVENT_ATTR(read-hit, 0x01), 403 XGENE_PMU_EVENT_ATTR(read-miss, 0x02), 404 XGENE_PMU_EVENT_ATTR(index-flush-eviction, 0x03), 405 XGENE_PMU_EVENT_ATTR(write-caused-replacement, 0x04), 406 XGENE_PMU_EVENT_ATTR(write-not-caused-replacement, 0x05), 407 XGENE_PMU_EVENT_ATTR(clean-eviction, 0x06), 408 XGENE_PMU_EVENT_ATTR(dirty-eviction, 0x07), 409 XGENE_PMU_EVENT_ATTR(read, 0x08), 410 XGENE_PMU_EVENT_ATTR(write, 0x09), 411 XGENE_PMU_EVENT_ATTR(request, 0x0a), 412 XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b), 413 XGENE_PMU_EVENT_ATTR(tq-full, 0x0c), 414 XGENE_PMU_EVENT_ATTR(ackq-full, 0x0d), 415 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0e), 416 XGENE_PMU_EVENT_ATTR(odb-full, 0x10), 417 XGENE_PMU_EVENT_ATTR(wbq-full, 0x11), 418 XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall, 0x12), 419 XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall, 0x13), 420 XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall, 0x14), 421 XGENE_PMU_EVENT_ATTR(total-insertion, 0x15), 422 XGENE_PMU_EVENT_ATTR(sip-insertions-r-set, 0x16), 423 XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear, 0x17), 424 XGENE_PMU_EVENT_ATTR(dip-insertions-r-set, 0x18), 425 XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear, 0x19), 426 XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set, 0x1a), 427 XGENE_PMU_EVENT_ATTR(egression, 0x1b), 428 XGENE_PMU_EVENT_ATTR(replacement, 0x1c), 429 XGENE_PMU_EVENT_ATTR(old-replacement, 0x1d), 430 XGENE_PMU_EVENT_ATTR(young-replacement, 0x1e), 431 XGENE_PMU_EVENT_ATTR(r-set-replacement, 0x1f), 432 XGENE_PMU_EVENT_ATTR(r-clear-replacement, 0x20), 433 XGENE_PMU_EVENT_ATTR(old-r-replacement, 0x21), 434 XGENE_PMU_EVENT_ATTR(old-nr-replacement, 0x22), 435 XGENE_PMU_EVENT_ATTR(young-r-replacement, 0x23), 436 XGENE_PMU_EVENT_ATTR(young-nr-replacement, 0x24), 437 XGENE_PMU_EVENT_ATTR(bloomfilter-clearing, 0x25), 438 XGENE_PMU_EVENT_ATTR(generation-flip, 0x26), 439 XGENE_PMU_EVENT_ATTR(vcc-droop-detected, 0x27), 440 NULL, 441 }; 442 443 static struct attribute *iob_fast_pmu_v3_events_attrs[] = { 444 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 445 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all, 0x01), 446 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd, 0x02), 447 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr, 0x03), 448 XGENE_PMU_EVENT_ATTR(pa-all-cp-req, 0x04), 449 XGENE_PMU_EVENT_ATTR(pa-cp-blk-req, 0x05), 450 XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req, 0x06), 451 XGENE_PMU_EVENT_ATTR(pa-cp-rd-req, 0x07), 452 XGENE_PMU_EVENT_ATTR(pa-cp-wr-req, 0x08), 453 XGENE_PMU_EVENT_ATTR(ba-all-req, 0x09), 454 XGENE_PMU_EVENT_ATTR(ba-rd-req, 0x0a), 455 XGENE_PMU_EVENT_ATTR(ba-wr-req, 0x0b), 456 XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued, 0x10), 457 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued, 0x11), 458 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12), 459 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13), 460 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable, 0x14), 461 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15), 462 XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req, 0x16), 463 XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req, 0x17), 464 XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data, 0x18), 465 XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS, 0x1b), 466 XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c), 467 XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d), 468 XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops, 0x20), 469 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop, 0x21), 470 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit, 0x22), 471 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop, 0x23), 472 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit, 0x24), 473 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop, 0x25), 474 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit, 0x26), 475 XGENE_PMU_EVENT_ATTR(pa-req-buffer-full, 0x28), 476 XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full, 0x29), 477 XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a), 478 XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full, 0x2b), 479 XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c), 480 XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full, 0x2d), 481 XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e), 482 XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure, 0x2f), 483 NULL, 484 }; 485 486 static struct attribute *iob_slow_pmu_v3_events_attrs[] = { 487 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 488 XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req, 0x01), 489 XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req, 0x02), 490 XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req, 0x03), 491 XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req, 0x04), 492 XGENE_PMU_EVENT_ATTR(ba-all-axi-req, 0x07), 493 XGENE_PMU_EVENT_ATTR(ba-axi-rd-req, 0x08), 494 XGENE_PMU_EVENT_ATTR(ba-axi-wr-req, 0x09), 495 XGENE_PMU_EVENT_ATTR(ba-free-list-empty, 0x10), 496 NULL, 497 }; 498 499 static struct attribute *mcb_pmu_v3_events_attrs[] = { 500 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 501 XGENE_PMU_EVENT_ATTR(req-receive, 0x01), 502 XGENE_PMU_EVENT_ATTR(rd-req-recv, 0x02), 503 XGENE_PMU_EVENT_ATTR(rd-req-recv-2, 0x03), 504 XGENE_PMU_EVENT_ATTR(wr-req-recv, 0x04), 505 XGENE_PMU_EVENT_ATTR(wr-req-recv-2, 0x05), 506 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu, 0x06), 507 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2, 0x07), 508 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu, 0x08), 509 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2, 0x09), 510 XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a), 511 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b), 512 XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c), 513 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req, 0x0d), 514 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2, 0x0e), 515 XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu, 0x0f), 516 XGENE_PMU_EVENT_ATTR(gack-recv, 0x10), 517 XGENE_PMU_EVENT_ATTR(rd-gack-recv, 0x11), 518 XGENE_PMU_EVENT_ATTR(wr-gack-recv, 0x12), 519 XGENE_PMU_EVENT_ATTR(cancel-rd-gack, 0x13), 520 XGENE_PMU_EVENT_ATTR(cancel-wr-gack, 0x14), 521 XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall, 0x15), 522 XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked, 0x16), 523 XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall, 0x17), 524 XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked, 0x18), 525 XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked, 0x19), 526 XGENE_PMU_EVENT_ATTR(mcu-req-table-full, 0x1a), 527 XGENE_PMU_EVENT_ATTR(mcu-stat-table-full, 0x1b), 528 XGENE_PMU_EVENT_ATTR(mcu-wr-table-full, 0x1c), 529 XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp, 0x1d), 530 XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp, 0x1e), 531 XGENE_PMU_EVENT_ATTR(mcu-retryack-resp, 0x1f), 532 XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp, 0x20), 533 XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload, 0x21), 534 XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass, 0x22), 535 XGENE_PMU_EVENT_ATTR(volt-droop-detect, 0x23), 536 NULL, 537 }; 538 539 static struct attribute *mc_pmu_v3_events_attrs[] = { 540 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 541 XGENE_PMU_EVENT_ATTR(act-sent, 0x01), 542 XGENE_PMU_EVENT_ATTR(pre-sent, 0x02), 543 XGENE_PMU_EVENT_ATTR(rd-sent, 0x03), 544 XGENE_PMU_EVENT_ATTR(rda-sent, 0x04), 545 XGENE_PMU_EVENT_ATTR(wr-sent, 0x05), 546 XGENE_PMU_EVENT_ATTR(wra-sent, 0x06), 547 XGENE_PMU_EVENT_ATTR(pd-entry-vld, 0x07), 548 XGENE_PMU_EVENT_ATTR(sref-entry-vld, 0x08), 549 XGENE_PMU_EVENT_ATTR(prea-sent, 0x09), 550 XGENE_PMU_EVENT_ATTR(ref-sent, 0x0a), 551 XGENE_PMU_EVENT_ATTR(rd-rda-sent, 0x0b), 552 XGENE_PMU_EVENT_ATTR(wr-wra-sent, 0x0c), 553 XGENE_PMU_EVENT_ATTR(raw-hazard, 0x0d), 554 XGENE_PMU_EVENT_ATTR(war-hazard, 0x0e), 555 XGENE_PMU_EVENT_ATTR(waw-hazard, 0x0f), 556 XGENE_PMU_EVENT_ATTR(rar-hazard, 0x10), 557 XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard, 0x11), 558 XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld, 0x12), 559 XGENE_PMU_EVENT_ATTR(lprd-req-vld, 0x13), 560 XGENE_PMU_EVENT_ATTR(hprd-req-vld, 0x14), 561 XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld, 0x15), 562 XGENE_PMU_EVENT_ATTR(wr-req-vld, 0x16), 563 XGENE_PMU_EVENT_ATTR(partial-wr-req-vld, 0x17), 564 XGENE_PMU_EVENT_ATTR(rd-retry, 0x18), 565 XGENE_PMU_EVENT_ATTR(wr-retry, 0x19), 566 XGENE_PMU_EVENT_ATTR(retry-gnt, 0x1a), 567 XGENE_PMU_EVENT_ATTR(rank-change, 0x1b), 568 XGENE_PMU_EVENT_ATTR(dir-change, 0x1c), 569 XGENE_PMU_EVENT_ATTR(rank-dir-change, 0x1d), 570 XGENE_PMU_EVENT_ATTR(rank-active, 0x1e), 571 XGENE_PMU_EVENT_ATTR(rank-idle, 0x1f), 572 XGENE_PMU_EVENT_ATTR(rank-pd, 0x20), 573 XGENE_PMU_EVENT_ATTR(rank-sref, 0x21), 574 XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh, 0x22), 575 XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh, 0x23), 576 XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh, 0x24), 577 XGENE_PMU_EVENT_ATTR(phy-updt-complt, 0x25), 578 XGENE_PMU_EVENT_ATTR(tz-fail, 0x26), 579 XGENE_PMU_EVENT_ATTR(dram-errc, 0x27), 580 XGENE_PMU_EVENT_ATTR(dram-errd, 0x28), 581 XGENE_PMU_EVENT_ATTR(rd-enq, 0x29), 582 XGENE_PMU_EVENT_ATTR(wr-enq, 0x2a), 583 XGENE_PMU_EVENT_ATTR(tmac-limit-reached, 0x2b), 584 XGENE_PMU_EVENT_ATTR(tmaw-tracker-full, 0x2c), 585 NULL, 586 }; 587 588 static const struct attribute_group l3c_pmu_v3_events_attr_group = { 589 .name = "events", 590 .attrs = l3c_pmu_v3_events_attrs, 591 }; 592 593 static const struct attribute_group iob_fast_pmu_v3_events_attr_group = { 594 .name = "events", 595 .attrs = iob_fast_pmu_v3_events_attrs, 596 }; 597 598 static const struct attribute_group iob_slow_pmu_v3_events_attr_group = { 599 .name = "events", 600 .attrs = iob_slow_pmu_v3_events_attrs, 601 }; 602 603 static const struct attribute_group mcb_pmu_v3_events_attr_group = { 604 .name = "events", 605 .attrs = mcb_pmu_v3_events_attrs, 606 }; 607 608 static const struct attribute_group mc_pmu_v3_events_attr_group = { 609 .name = "events", 610 .attrs = mc_pmu_v3_events_attrs, 611 }; 612 613 /* 614 * sysfs cpumask attributes 615 */ 616 static ssize_t xgene_pmu_cpumask_show(struct device *dev, 617 struct device_attribute *attr, char *buf) 618 { 619 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev)); 620 621 return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu); 622 } 623 624 static DEVICE_ATTR(cpumask, S_IRUGO, xgene_pmu_cpumask_show, NULL); 625 626 static struct attribute *xgene_pmu_cpumask_attrs[] = { 627 &dev_attr_cpumask.attr, 628 NULL, 629 }; 630 631 static const struct attribute_group pmu_cpumask_attr_group = { 632 .attrs = xgene_pmu_cpumask_attrs, 633 }; 634 635 /* 636 * Per PMU device attribute groups of PMU v1 and v2 637 */ 638 static const struct attribute_group *l3c_pmu_attr_groups[] = { 639 &l3c_pmu_format_attr_group, 640 &pmu_cpumask_attr_group, 641 &l3c_pmu_events_attr_group, 642 NULL 643 }; 644 645 static const struct attribute_group *iob_pmu_attr_groups[] = { 646 &iob_pmu_format_attr_group, 647 &pmu_cpumask_attr_group, 648 &iob_pmu_events_attr_group, 649 NULL 650 }; 651 652 static const struct attribute_group *mcb_pmu_attr_groups[] = { 653 &mcb_pmu_format_attr_group, 654 &pmu_cpumask_attr_group, 655 &mcb_pmu_events_attr_group, 656 NULL 657 }; 658 659 static const struct attribute_group *mc_pmu_attr_groups[] = { 660 &mc_pmu_format_attr_group, 661 &pmu_cpumask_attr_group, 662 &mc_pmu_events_attr_group, 663 NULL 664 }; 665 666 /* 667 * Per PMU device attribute groups of PMU v3 668 */ 669 static const struct attribute_group *l3c_pmu_v3_attr_groups[] = { 670 &l3c_pmu_v3_format_attr_group, 671 &pmu_cpumask_attr_group, 672 &l3c_pmu_v3_events_attr_group, 673 NULL 674 }; 675 676 static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = { 677 &iob_pmu_v3_format_attr_group, 678 &pmu_cpumask_attr_group, 679 &iob_fast_pmu_v3_events_attr_group, 680 NULL 681 }; 682 683 static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = { 684 &iob_slow_pmu_v3_format_attr_group, 685 &pmu_cpumask_attr_group, 686 &iob_slow_pmu_v3_events_attr_group, 687 NULL 688 }; 689 690 static const struct attribute_group *mcb_pmu_v3_attr_groups[] = { 691 &mcb_pmu_v3_format_attr_group, 692 &pmu_cpumask_attr_group, 693 &mcb_pmu_v3_events_attr_group, 694 NULL 695 }; 696 697 static const struct attribute_group *mc_pmu_v3_attr_groups[] = { 698 &mc_pmu_v3_format_attr_group, 699 &pmu_cpumask_attr_group, 700 &mc_pmu_v3_events_attr_group, 701 NULL 702 }; 703 704 static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev) 705 { 706 int cntr; 707 708 cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask, 709 pmu_dev->max_counters); 710 if (cntr == pmu_dev->max_counters) 711 return -ENOSPC; 712 set_bit(cntr, pmu_dev->cntr_assign_mask); 713 714 return cntr; 715 } 716 717 static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr) 718 { 719 clear_bit(cntr, pmu_dev->cntr_assign_mask); 720 } 721 722 static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu) 723 { 724 writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 725 } 726 727 static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu) 728 { 729 writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 730 } 731 732 static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu) 733 { 734 writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 735 } 736 737 static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu) 738 { 739 writel(PCPPMU_V3_INTCLRMASK, 740 xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 741 } 742 743 static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev, 744 int idx) 745 { 746 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); 747 } 748 749 static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev, 750 int idx) 751 { 752 u32 lo, hi; 753 754 /* 755 * v3 has 64-bit counter registers composed by 2 32-bit registers 756 * This can be a problem if the counter increases and carries 757 * out of bit [31] between 2 reads. The extra reads would help 758 * to prevent this issue. 759 */ 760 do { 761 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1); 762 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx); 763 } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1)); 764 765 return (((u64)hi << 32) | lo); 766 } 767 768 static inline void 769 xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) 770 { 771 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); 772 } 773 774 static inline void 775 xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) 776 { 777 u32 cnt_lo, cnt_hi; 778 779 cnt_hi = upper_32_bits(val); 780 cnt_lo = lower_32_bits(val); 781 782 /* v3 has 64-bit counter registers composed by 2 32-bit registers */ 783 xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo); 784 xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi); 785 } 786 787 static inline void 788 xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val) 789 { 790 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx)); 791 } 792 793 static inline void 794 xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) 795 { 796 writel(val, pmu_dev->inf->csr + PMU_PMAMR0); 797 } 798 799 static inline void 800 xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { } 801 802 static inline void 803 xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) 804 { 805 writel(val, pmu_dev->inf->csr + PMU_PMAMR1); 806 } 807 808 static inline void 809 xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { } 810 811 static inline void 812 xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx) 813 { 814 u32 val; 815 816 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET); 817 val |= 1 << idx; 818 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET); 819 } 820 821 static inline void 822 xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx) 823 { 824 u32 val; 825 826 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR); 827 val |= 1 << idx; 828 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR); 829 } 830 831 static inline void 832 xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx) 833 { 834 u32 val; 835 836 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET); 837 val |= 1 << idx; 838 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET); 839 } 840 841 static inline void 842 xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx) 843 { 844 u32 val; 845 846 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR); 847 val |= 1 << idx; 848 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR); 849 } 850 851 static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev) 852 { 853 u32 val; 854 855 val = readl(pmu_dev->inf->csr + PMU_PMCR); 856 val |= PMU_PMCR_P; 857 writel(val, pmu_dev->inf->csr + PMU_PMCR); 858 } 859 860 static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev) 861 { 862 u32 val; 863 864 val = readl(pmu_dev->inf->csr + PMU_PMCR); 865 val |= PMU_PMCR_E; 866 writel(val, pmu_dev->inf->csr + PMU_PMCR); 867 } 868 869 static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev) 870 { 871 u32 val; 872 873 val = readl(pmu_dev->inf->csr + PMU_PMCR); 874 val &= ~PMU_PMCR_E; 875 writel(val, pmu_dev->inf->csr + PMU_PMCR); 876 } 877 878 static void xgene_perf_pmu_enable(struct pmu *pmu) 879 { 880 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu); 881 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 882 int enabled = bitmap_weight(pmu_dev->cntr_assign_mask, 883 pmu_dev->max_counters); 884 885 if (!enabled) 886 return; 887 888 xgene_pmu->ops->start_counters(pmu_dev); 889 } 890 891 static void xgene_perf_pmu_disable(struct pmu *pmu) 892 { 893 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu); 894 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 895 896 xgene_pmu->ops->stop_counters(pmu_dev); 897 } 898 899 static int xgene_perf_event_init(struct perf_event *event) 900 { 901 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 902 struct hw_perf_event *hw = &event->hw; 903 struct perf_event *sibling; 904 905 /* Test the event attr type check for PMU enumeration */ 906 if (event->attr.type != event->pmu->type) 907 return -ENOENT; 908 909 /* 910 * SOC PMU counters are shared across all cores. 911 * Therefore, it does not support per-process mode. 912 * Also, it does not support event sampling mode. 913 */ 914 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 915 return -EINVAL; 916 917 /* SOC counters do not have usr/os/guest/host bits */ 918 if (event->attr.exclude_user || event->attr.exclude_kernel || 919 event->attr.exclude_host || event->attr.exclude_guest) 920 return -EINVAL; 921 922 if (event->cpu < 0) 923 return -EINVAL; 924 /* 925 * Many perf core operations (eg. events rotation) operate on a 926 * single CPU context. This is obvious for CPU PMUs, where one 927 * expects the same sets of events being observed on all CPUs, 928 * but can lead to issues for off-core PMUs, where each 929 * event could be theoretically assigned to a different CPU. To 930 * mitigate this, we enforce CPU assignment to one, selected 931 * processor (the one described in the "cpumask" attribute). 932 */ 933 event->cpu = cpumask_first(&pmu_dev->parent->cpu); 934 935 hw->config = event->attr.config; 936 /* 937 * Each bit of the config1 field represents an agent from which the 938 * request of the event come. The event is counted only if it's caused 939 * by a request of an agent has the bit cleared. 940 * By default, the event is counted for all agents. 941 */ 942 hw->config_base = event->attr.config1; 943 944 /* 945 * We must NOT create groups containing mixed PMUs, although software 946 * events are acceptable 947 */ 948 if (event->group_leader->pmu != event->pmu && 949 !is_software_event(event->group_leader)) 950 return -EINVAL; 951 952 for_each_sibling_event(sibling, event->group_leader) { 953 if (sibling->pmu != event->pmu && 954 !is_software_event(sibling)) 955 return -EINVAL; 956 } 957 958 return 0; 959 } 960 961 static void xgene_perf_enable_event(struct perf_event *event) 962 { 963 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 964 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 965 966 xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event), 967 GET_EVENTID(event)); 968 xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event))); 969 if (pmu_dev->inf->type == PMU_TYPE_IOB) 970 xgene_pmu->ops->write_agent1msk(pmu_dev, 971 ~((u32)GET_AGENT1ID(event))); 972 973 xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event)); 974 xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event)); 975 } 976 977 static void xgene_perf_disable_event(struct perf_event *event) 978 { 979 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 980 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 981 982 xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event)); 983 xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event)); 984 } 985 986 static void xgene_perf_event_set_period(struct perf_event *event) 987 { 988 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 989 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 990 struct hw_perf_event *hw = &event->hw; 991 /* 992 * For 32 bit counter, it has a period of 2^32. To account for the 993 * possibility of extreme interrupt latency we program for a period of 994 * half that. Hopefully, we can handle the interrupt before another 2^31 995 * events occur and the counter overtakes its previous value. 996 * For 64 bit counter, we don't expect it overflow. 997 */ 998 u64 val = 1ULL << 31; 999 1000 local64_set(&hw->prev_count, val); 1001 xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val); 1002 } 1003 1004 static void xgene_perf_event_update(struct perf_event *event) 1005 { 1006 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 1007 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 1008 struct hw_perf_event *hw = &event->hw; 1009 u64 delta, prev_raw_count, new_raw_count; 1010 1011 again: 1012 prev_raw_count = local64_read(&hw->prev_count); 1013 new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event)); 1014 1015 if (local64_cmpxchg(&hw->prev_count, prev_raw_count, 1016 new_raw_count) != prev_raw_count) 1017 goto again; 1018 1019 delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period; 1020 1021 local64_add(delta, &event->count); 1022 } 1023 1024 static void xgene_perf_read(struct perf_event *event) 1025 { 1026 xgene_perf_event_update(event); 1027 } 1028 1029 static void xgene_perf_start(struct perf_event *event, int flags) 1030 { 1031 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 1032 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 1033 struct hw_perf_event *hw = &event->hw; 1034 1035 if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED))) 1036 return; 1037 1038 WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE)); 1039 hw->state = 0; 1040 1041 xgene_perf_event_set_period(event); 1042 1043 if (flags & PERF_EF_RELOAD) { 1044 u64 prev_raw_count = local64_read(&hw->prev_count); 1045 1046 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event), 1047 prev_raw_count); 1048 } 1049 1050 xgene_perf_enable_event(event); 1051 perf_event_update_userpage(event); 1052 } 1053 1054 static void xgene_perf_stop(struct perf_event *event, int flags) 1055 { 1056 struct hw_perf_event *hw = &event->hw; 1057 u64 config; 1058 1059 if (hw->state & PERF_HES_UPTODATE) 1060 return; 1061 1062 xgene_perf_disable_event(event); 1063 WARN_ON_ONCE(hw->state & PERF_HES_STOPPED); 1064 hw->state |= PERF_HES_STOPPED; 1065 1066 if (hw->state & PERF_HES_UPTODATE) 1067 return; 1068 1069 config = hw->config; 1070 xgene_perf_read(event); 1071 hw->state |= PERF_HES_UPTODATE; 1072 } 1073 1074 static int xgene_perf_add(struct perf_event *event, int flags) 1075 { 1076 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 1077 struct hw_perf_event *hw = &event->hw; 1078 1079 hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1080 1081 /* Allocate an event counter */ 1082 hw->idx = get_next_avail_cntr(pmu_dev); 1083 if (hw->idx < 0) 1084 return -EAGAIN; 1085 1086 /* Update counter event pointer for Interrupt handler */ 1087 pmu_dev->pmu_counter_event[hw->idx] = event; 1088 1089 if (flags & PERF_EF_START) 1090 xgene_perf_start(event, PERF_EF_RELOAD); 1091 1092 return 0; 1093 } 1094 1095 static void xgene_perf_del(struct perf_event *event, int flags) 1096 { 1097 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 1098 struct hw_perf_event *hw = &event->hw; 1099 1100 xgene_perf_stop(event, PERF_EF_UPDATE); 1101 1102 /* clear the assigned counter */ 1103 clear_avail_cntr(pmu_dev, GET_CNTR(event)); 1104 1105 perf_event_update_userpage(event); 1106 pmu_dev->pmu_counter_event[hw->idx] = NULL; 1107 } 1108 1109 static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name) 1110 { 1111 struct xgene_pmu *xgene_pmu; 1112 1113 if (pmu_dev->parent->version == PCP_PMU_V3) 1114 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD; 1115 else 1116 pmu_dev->max_period = PMU_CNT_MAX_PERIOD; 1117 /* First version PMU supports only single event counter */ 1118 xgene_pmu = pmu_dev->parent; 1119 if (xgene_pmu->version == PCP_PMU_V1) 1120 pmu_dev->max_counters = 1; 1121 else 1122 pmu_dev->max_counters = PMU_MAX_COUNTERS; 1123 1124 /* Perf driver registration */ 1125 pmu_dev->pmu = (struct pmu) { 1126 .attr_groups = pmu_dev->attr_groups, 1127 .task_ctx_nr = perf_invalid_context, 1128 .pmu_enable = xgene_perf_pmu_enable, 1129 .pmu_disable = xgene_perf_pmu_disable, 1130 .event_init = xgene_perf_event_init, 1131 .add = xgene_perf_add, 1132 .del = xgene_perf_del, 1133 .start = xgene_perf_start, 1134 .stop = xgene_perf_stop, 1135 .read = xgene_perf_read, 1136 }; 1137 1138 /* Hardware counter init */ 1139 xgene_pmu->ops->stop_counters(pmu_dev); 1140 xgene_pmu->ops->reset_counters(pmu_dev); 1141 1142 return perf_pmu_register(&pmu_dev->pmu, name, -1); 1143 } 1144 1145 static int 1146 xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx) 1147 { 1148 struct device *dev = xgene_pmu->dev; 1149 struct xgene_pmu_dev *pmu; 1150 1151 pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL); 1152 if (!pmu) 1153 return -ENOMEM; 1154 pmu->parent = xgene_pmu; 1155 pmu->inf = &ctx->inf; 1156 ctx->pmu_dev = pmu; 1157 1158 switch (pmu->inf->type) { 1159 case PMU_TYPE_L3C: 1160 if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask)) 1161 return -ENODEV; 1162 if (xgene_pmu->version == PCP_PMU_V3) 1163 pmu->attr_groups = l3c_pmu_v3_attr_groups; 1164 else 1165 pmu->attr_groups = l3c_pmu_attr_groups; 1166 break; 1167 case PMU_TYPE_IOB: 1168 if (xgene_pmu->version == PCP_PMU_V3) 1169 pmu->attr_groups = iob_fast_pmu_v3_attr_groups; 1170 else 1171 pmu->attr_groups = iob_pmu_attr_groups; 1172 break; 1173 case PMU_TYPE_IOB_SLOW: 1174 if (xgene_pmu->version == PCP_PMU_V3) 1175 pmu->attr_groups = iob_slow_pmu_v3_attr_groups; 1176 break; 1177 case PMU_TYPE_MCB: 1178 if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask)) 1179 return -ENODEV; 1180 if (xgene_pmu->version == PCP_PMU_V3) 1181 pmu->attr_groups = mcb_pmu_v3_attr_groups; 1182 else 1183 pmu->attr_groups = mcb_pmu_attr_groups; 1184 break; 1185 case PMU_TYPE_MC: 1186 if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask)) 1187 return -ENODEV; 1188 if (xgene_pmu->version == PCP_PMU_V3) 1189 pmu->attr_groups = mc_pmu_v3_attr_groups; 1190 else 1191 pmu->attr_groups = mc_pmu_attr_groups; 1192 break; 1193 default: 1194 return -EINVAL; 1195 } 1196 1197 if (xgene_init_perf(pmu, ctx->name)) { 1198 dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name); 1199 return -ENODEV; 1200 } 1201 1202 dev_info(dev, "%s PMU registered\n", ctx->name); 1203 1204 return 0; 1205 } 1206 1207 static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev) 1208 { 1209 struct xgene_pmu *xgene_pmu = pmu_dev->parent; 1210 void __iomem *csr = pmu_dev->inf->csr; 1211 u32 pmovsr; 1212 int idx; 1213 1214 xgene_pmu->ops->stop_counters(pmu_dev); 1215 1216 if (xgene_pmu->version == PCP_PMU_V3) 1217 pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK; 1218 else 1219 pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK; 1220 1221 if (!pmovsr) 1222 goto out; 1223 1224 /* Clear interrupt flag */ 1225 if (xgene_pmu->version == PCP_PMU_V1) 1226 writel(0x0, csr + PMU_PMOVSR); 1227 else if (xgene_pmu->version == PCP_PMU_V2) 1228 writel(pmovsr, csr + PMU_PMOVSR); 1229 else 1230 writel(pmovsr, csr + PMU_PMOVSCLR); 1231 1232 for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) { 1233 struct perf_event *event = pmu_dev->pmu_counter_event[idx]; 1234 int overflowed = pmovsr & BIT(idx); 1235 1236 /* Ignore if we don't have an event. */ 1237 if (!event || !overflowed) 1238 continue; 1239 xgene_perf_event_update(event); 1240 xgene_perf_event_set_period(event); 1241 } 1242 1243 out: 1244 xgene_pmu->ops->start_counters(pmu_dev); 1245 } 1246 1247 static irqreturn_t xgene_pmu_isr(int irq, void *dev_id) 1248 { 1249 u32 intr_mcu, intr_mcb, intr_l3c, intr_iob; 1250 struct xgene_pmu_dev_ctx *ctx; 1251 struct xgene_pmu *xgene_pmu = dev_id; 1252 unsigned long flags; 1253 u32 val; 1254 1255 raw_spin_lock_irqsave(&xgene_pmu->lock, flags); 1256 1257 /* Get Interrupt PMU source */ 1258 val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG); 1259 if (xgene_pmu->version == PCP_PMU_V3) { 1260 intr_mcu = PCPPMU_V3_INT_MCU; 1261 intr_mcb = PCPPMU_V3_INT_MCB; 1262 intr_l3c = PCPPMU_V3_INT_L3C; 1263 intr_iob = PCPPMU_V3_INT_IOB; 1264 } else { 1265 intr_mcu = PCPPMU_INT_MCU; 1266 intr_mcb = PCPPMU_INT_MCB; 1267 intr_l3c = PCPPMU_INT_L3C; 1268 intr_iob = PCPPMU_INT_IOB; 1269 } 1270 if (val & intr_mcu) { 1271 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) { 1272 _xgene_pmu_isr(irq, ctx->pmu_dev); 1273 } 1274 } 1275 if (val & intr_mcb) { 1276 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) { 1277 _xgene_pmu_isr(irq, ctx->pmu_dev); 1278 } 1279 } 1280 if (val & intr_l3c) { 1281 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) { 1282 _xgene_pmu_isr(irq, ctx->pmu_dev); 1283 } 1284 } 1285 if (val & intr_iob) { 1286 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) { 1287 _xgene_pmu_isr(irq, ctx->pmu_dev); 1288 } 1289 } 1290 1291 raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags); 1292 1293 return IRQ_HANDLED; 1294 } 1295 1296 static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1297 struct platform_device *pdev) 1298 { 1299 void __iomem *csw_csr, *mcba_csr, *mcbb_csr; 1300 struct resource *res; 1301 unsigned int reg; 1302 1303 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1304 csw_csr = devm_ioremap_resource(&pdev->dev, res); 1305 if (IS_ERR(csw_csr)) { 1306 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n"); 1307 return PTR_ERR(csw_csr); 1308 } 1309 1310 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1311 mcba_csr = devm_ioremap_resource(&pdev->dev, res); 1312 if (IS_ERR(mcba_csr)) { 1313 dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n"); 1314 return PTR_ERR(mcba_csr); 1315 } 1316 1317 res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1318 mcbb_csr = devm_ioremap_resource(&pdev->dev, res); 1319 if (IS_ERR(mcbb_csr)) { 1320 dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n"); 1321 return PTR_ERR(mcbb_csr); 1322 } 1323 1324 xgene_pmu->l3c_active_mask = 0x1; 1325 1326 reg = readl(csw_csr + CSW_CSWCR); 1327 if (reg & CSW_CSWCR_DUALMCB_MASK) { 1328 /* Dual MCB active */ 1329 xgene_pmu->mcb_active_mask = 0x3; 1330 /* Probe all active MC(s) */ 1331 reg = readl(mcbb_csr + CSW_CSWCR); 1332 xgene_pmu->mc_active_mask = 1333 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; 1334 } else { 1335 /* Single MCB active */ 1336 xgene_pmu->mcb_active_mask = 0x1; 1337 /* Probe all active MC(s) */ 1338 reg = readl(mcba_csr + CSW_CSWCR); 1339 xgene_pmu->mc_active_mask = 1340 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1347 struct platform_device *pdev) 1348 { 1349 void __iomem *csw_csr; 1350 struct resource *res; 1351 unsigned int reg; 1352 u32 mcb0routing; 1353 u32 mcb1routing; 1354 1355 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1356 csw_csr = devm_ioremap_resource(&pdev->dev, res); 1357 if (IS_ERR(csw_csr)) { 1358 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n"); 1359 return PTR_ERR(csw_csr); 1360 } 1361 1362 reg = readl(csw_csr + CSW_CSWCR); 1363 mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg); 1364 mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg); 1365 if (reg & CSW_CSWCR_DUALMCB_MASK) { 1366 /* Dual MCB active */ 1367 xgene_pmu->mcb_active_mask = 0x3; 1368 /* Probe all active L3C(s), maximum is 8 */ 1369 xgene_pmu->l3c_active_mask = 0xFF; 1370 /* Probe all active MC(s), maximum is 8 */ 1371 if ((mcb0routing == 0x2) && (mcb1routing == 0x2)) 1372 xgene_pmu->mc_active_mask = 0xFF; 1373 else if ((mcb0routing == 0x1) && (mcb1routing == 0x1)) 1374 xgene_pmu->mc_active_mask = 0x33; 1375 else 1376 xgene_pmu->mc_active_mask = 0x11; 1377 } else { 1378 /* Single MCB active */ 1379 xgene_pmu->mcb_active_mask = 0x1; 1380 /* Probe all active L3C(s), maximum is 4 */ 1381 xgene_pmu->l3c_active_mask = 0x0F; 1382 /* Probe all active MC(s), maximum is 4 */ 1383 if (mcb0routing == 0x2) 1384 xgene_pmu->mc_active_mask = 0x0F; 1385 else if (mcb0routing == 0x1) 1386 xgene_pmu->mc_active_mask = 0x03; 1387 else 1388 xgene_pmu->mc_active_mask = 0x01; 1389 } 1390 1391 return 0; 1392 } 1393 1394 static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1395 struct platform_device *pdev) 1396 { 1397 struct regmap *csw_map, *mcba_map, *mcbb_map; 1398 struct device_node *np = pdev->dev.of_node; 1399 unsigned int reg; 1400 1401 csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw"); 1402 if (IS_ERR(csw_map)) { 1403 dev_err(&pdev->dev, "unable to get syscon regmap csw\n"); 1404 return PTR_ERR(csw_map); 1405 } 1406 1407 mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba"); 1408 if (IS_ERR(mcba_map)) { 1409 dev_err(&pdev->dev, "unable to get syscon regmap mcba\n"); 1410 return PTR_ERR(mcba_map); 1411 } 1412 1413 mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb"); 1414 if (IS_ERR(mcbb_map)) { 1415 dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n"); 1416 return PTR_ERR(mcbb_map); 1417 } 1418 1419 xgene_pmu->l3c_active_mask = 0x1; 1420 if (regmap_read(csw_map, CSW_CSWCR, ®)) 1421 return -EINVAL; 1422 1423 if (reg & CSW_CSWCR_DUALMCB_MASK) { 1424 /* Dual MCB active */ 1425 xgene_pmu->mcb_active_mask = 0x3; 1426 /* Probe all active MC(s) */ 1427 if (regmap_read(mcbb_map, MCBADDRMR, ®)) 1428 return 0; 1429 xgene_pmu->mc_active_mask = 1430 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; 1431 } else { 1432 /* Single MCB active */ 1433 xgene_pmu->mcb_active_mask = 0x1; 1434 /* Probe all active MC(s) */ 1435 if (regmap_read(mcba_map, MCBADDRMR, ®)) 1436 return 0; 1437 xgene_pmu->mc_active_mask = 1438 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; 1439 } 1440 1441 return 0; 1442 } 1443 1444 static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1445 struct platform_device *pdev) 1446 { 1447 if (has_acpi_companion(&pdev->dev)) { 1448 if (xgene_pmu->version == PCP_PMU_V3) 1449 return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu, 1450 pdev); 1451 else 1452 return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, 1453 pdev); 1454 } 1455 return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev); 1456 } 1457 1458 static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id) 1459 { 1460 switch (type) { 1461 case PMU_TYPE_L3C: 1462 return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id); 1463 case PMU_TYPE_IOB: 1464 return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id); 1465 case PMU_TYPE_IOB_SLOW: 1466 return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d", id); 1467 case PMU_TYPE_MCB: 1468 return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id); 1469 case PMU_TYPE_MC: 1470 return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id); 1471 default: 1472 return devm_kasprintf(dev, GFP_KERNEL, "unknown"); 1473 } 1474 } 1475 1476 #if defined(CONFIG_ACPI) 1477 static int acpi_pmu_dev_add_resource(struct acpi_resource *ares, void *data) 1478 { 1479 struct resource *res = data; 1480 1481 if (ares->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) 1482 acpi_dev_resource_memory(ares, res); 1483 1484 /* Always tell the ACPI core to skip this resource */ 1485 return 1; 1486 } 1487 1488 static struct 1489 xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu, 1490 struct acpi_device *adev, u32 type) 1491 { 1492 struct device *dev = xgene_pmu->dev; 1493 struct list_head resource_list; 1494 struct xgene_pmu_dev_ctx *ctx; 1495 const union acpi_object *obj; 1496 struct hw_pmu_info *inf; 1497 void __iomem *dev_csr; 1498 struct resource res; 1499 int enable_bit; 1500 int rc; 1501 1502 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1503 if (!ctx) 1504 return NULL; 1505 1506 INIT_LIST_HEAD(&resource_list); 1507 rc = acpi_dev_get_resources(adev, &resource_list, 1508 acpi_pmu_dev_add_resource, &res); 1509 acpi_dev_free_resource_list(&resource_list); 1510 if (rc < 0) { 1511 dev_err(dev, "PMU type %d: No resource address found\n", type); 1512 return NULL; 1513 } 1514 1515 dev_csr = devm_ioremap_resource(dev, &res); 1516 if (IS_ERR(dev_csr)) { 1517 dev_err(dev, "PMU type %d: Fail to map resource\n", type); 1518 return NULL; 1519 } 1520 1521 /* A PMU device node without enable-bit-index is always enabled */ 1522 rc = acpi_dev_get_property(adev, "enable-bit-index", 1523 ACPI_TYPE_INTEGER, &obj); 1524 if (rc < 0) 1525 enable_bit = 0; 1526 else 1527 enable_bit = (int) obj->integer.value; 1528 1529 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); 1530 if (!ctx->name) { 1531 dev_err(dev, "PMU type %d: Fail to get device name\n", type); 1532 return NULL; 1533 } 1534 inf = &ctx->inf; 1535 inf->type = type; 1536 inf->csr = dev_csr; 1537 inf->enable_mask = 1 << enable_bit; 1538 1539 return ctx; 1540 } 1541 1542 static const struct acpi_device_id xgene_pmu_acpi_type_match[] = { 1543 {"APMC0D5D", PMU_TYPE_L3C}, 1544 {"APMC0D5E", PMU_TYPE_IOB}, 1545 {"APMC0D5F", PMU_TYPE_MCB}, 1546 {"APMC0D60", PMU_TYPE_MC}, 1547 {"APMC0D84", PMU_TYPE_L3C}, 1548 {"APMC0D85", PMU_TYPE_IOB}, 1549 {"APMC0D86", PMU_TYPE_IOB_SLOW}, 1550 {"APMC0D87", PMU_TYPE_MCB}, 1551 {"APMC0D88", PMU_TYPE_MC}, 1552 {}, 1553 }; 1554 1555 static const struct acpi_device_id *xgene_pmu_acpi_match_type( 1556 const struct acpi_device_id *ids, 1557 struct acpi_device *adev) 1558 { 1559 const struct acpi_device_id *match_id = NULL; 1560 const struct acpi_device_id *id; 1561 1562 for (id = ids; id->id[0] || id->cls; id++) { 1563 if (!acpi_match_device_ids(adev, id)) 1564 match_id = id; 1565 else if (match_id) 1566 break; 1567 } 1568 1569 return match_id; 1570 } 1571 1572 static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level, 1573 void *data, void **return_value) 1574 { 1575 const struct acpi_device_id *acpi_id; 1576 struct xgene_pmu *xgene_pmu = data; 1577 struct xgene_pmu_dev_ctx *ctx; 1578 struct acpi_device *adev; 1579 1580 if (acpi_bus_get_device(handle, &adev)) 1581 return AE_OK; 1582 if (acpi_bus_get_status(adev) || !adev->status.present) 1583 return AE_OK; 1584 1585 acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev); 1586 if (!acpi_id) 1587 return AE_OK; 1588 1589 ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data); 1590 if (!ctx) 1591 return AE_OK; 1592 1593 if (xgene_pmu_dev_add(xgene_pmu, ctx)) { 1594 /* Can't add the PMU device, skip it */ 1595 devm_kfree(xgene_pmu->dev, ctx); 1596 return AE_OK; 1597 } 1598 1599 switch (ctx->inf.type) { 1600 case PMU_TYPE_L3C: 1601 list_add(&ctx->next, &xgene_pmu->l3cpmus); 1602 break; 1603 case PMU_TYPE_IOB: 1604 list_add(&ctx->next, &xgene_pmu->iobpmus); 1605 break; 1606 case PMU_TYPE_IOB_SLOW: 1607 list_add(&ctx->next, &xgene_pmu->iobpmus); 1608 break; 1609 case PMU_TYPE_MCB: 1610 list_add(&ctx->next, &xgene_pmu->mcbpmus); 1611 break; 1612 case PMU_TYPE_MC: 1613 list_add(&ctx->next, &xgene_pmu->mcpmus); 1614 break; 1615 } 1616 return AE_OK; 1617 } 1618 1619 static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1620 struct platform_device *pdev) 1621 { 1622 struct device *dev = xgene_pmu->dev; 1623 acpi_handle handle; 1624 acpi_status status; 1625 1626 handle = ACPI_HANDLE(dev); 1627 if (!handle) 1628 return -EINVAL; 1629 1630 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1, 1631 acpi_pmu_dev_add, NULL, xgene_pmu, NULL); 1632 if (ACPI_FAILURE(status)) { 1633 dev_err(dev, "failed to probe PMU devices\n"); 1634 return -ENODEV; 1635 } 1636 1637 return 0; 1638 } 1639 #else 1640 static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1641 struct platform_device *pdev) 1642 { 1643 return 0; 1644 } 1645 #endif 1646 1647 static struct 1648 xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu, 1649 struct device_node *np, u32 type) 1650 { 1651 struct device *dev = xgene_pmu->dev; 1652 struct xgene_pmu_dev_ctx *ctx; 1653 struct hw_pmu_info *inf; 1654 void __iomem *dev_csr; 1655 struct resource res; 1656 int enable_bit; 1657 1658 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1659 if (!ctx) 1660 return NULL; 1661 1662 if (of_address_to_resource(np, 0, &res) < 0) { 1663 dev_err(dev, "PMU type %d: No resource address found\n", type); 1664 return NULL; 1665 } 1666 1667 dev_csr = devm_ioremap_resource(dev, &res); 1668 if (IS_ERR(dev_csr)) { 1669 dev_err(dev, "PMU type %d: Fail to map resource\n", type); 1670 return NULL; 1671 } 1672 1673 /* A PMU device node without enable-bit-index is always enabled */ 1674 if (of_property_read_u32(np, "enable-bit-index", &enable_bit)) 1675 enable_bit = 0; 1676 1677 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); 1678 if (!ctx->name) { 1679 dev_err(dev, "PMU type %d: Fail to get device name\n", type); 1680 return NULL; 1681 } 1682 1683 inf = &ctx->inf; 1684 inf->type = type; 1685 inf->csr = dev_csr; 1686 inf->enable_mask = 1 << enable_bit; 1687 1688 return ctx; 1689 } 1690 1691 static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1692 struct platform_device *pdev) 1693 { 1694 struct xgene_pmu_dev_ctx *ctx; 1695 struct device_node *np; 1696 1697 for_each_child_of_node(pdev->dev.of_node, np) { 1698 if (!of_device_is_available(np)) 1699 continue; 1700 1701 if (of_device_is_compatible(np, "apm,xgene-pmu-l3c")) 1702 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C); 1703 else if (of_device_is_compatible(np, "apm,xgene-pmu-iob")) 1704 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB); 1705 else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb")) 1706 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB); 1707 else if (of_device_is_compatible(np, "apm,xgene-pmu-mc")) 1708 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC); 1709 else 1710 ctx = NULL; 1711 1712 if (!ctx) 1713 continue; 1714 1715 if (xgene_pmu_dev_add(xgene_pmu, ctx)) { 1716 /* Can't add the PMU device, skip it */ 1717 devm_kfree(xgene_pmu->dev, ctx); 1718 continue; 1719 } 1720 1721 switch (ctx->inf.type) { 1722 case PMU_TYPE_L3C: 1723 list_add(&ctx->next, &xgene_pmu->l3cpmus); 1724 break; 1725 case PMU_TYPE_IOB: 1726 list_add(&ctx->next, &xgene_pmu->iobpmus); 1727 break; 1728 case PMU_TYPE_IOB_SLOW: 1729 list_add(&ctx->next, &xgene_pmu->iobpmus); 1730 break; 1731 case PMU_TYPE_MCB: 1732 list_add(&ctx->next, &xgene_pmu->mcbpmus); 1733 break; 1734 case PMU_TYPE_MC: 1735 list_add(&ctx->next, &xgene_pmu->mcpmus); 1736 break; 1737 } 1738 } 1739 1740 return 0; 1741 } 1742 1743 static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1744 struct platform_device *pdev) 1745 { 1746 if (has_acpi_companion(&pdev->dev)) 1747 return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev); 1748 return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev); 1749 } 1750 1751 static const struct xgene_pmu_data xgene_pmu_data = { 1752 .id = PCP_PMU_V1, 1753 }; 1754 1755 static const struct xgene_pmu_data xgene_pmu_v2_data = { 1756 .id = PCP_PMU_V2, 1757 }; 1758 1759 static const struct xgene_pmu_ops xgene_pmu_ops = { 1760 .mask_int = xgene_pmu_mask_int, 1761 .unmask_int = xgene_pmu_unmask_int, 1762 .read_counter = xgene_pmu_read_counter32, 1763 .write_counter = xgene_pmu_write_counter32, 1764 .write_evttype = xgene_pmu_write_evttype, 1765 .write_agentmsk = xgene_pmu_write_agentmsk, 1766 .write_agent1msk = xgene_pmu_write_agent1msk, 1767 .enable_counter = xgene_pmu_enable_counter, 1768 .disable_counter = xgene_pmu_disable_counter, 1769 .enable_counter_int = xgene_pmu_enable_counter_int, 1770 .disable_counter_int = xgene_pmu_disable_counter_int, 1771 .reset_counters = xgene_pmu_reset_counters, 1772 .start_counters = xgene_pmu_start_counters, 1773 .stop_counters = xgene_pmu_stop_counters, 1774 }; 1775 1776 static const struct xgene_pmu_ops xgene_pmu_v3_ops = { 1777 .mask_int = xgene_pmu_v3_mask_int, 1778 .unmask_int = xgene_pmu_v3_unmask_int, 1779 .read_counter = xgene_pmu_read_counter64, 1780 .write_counter = xgene_pmu_write_counter64, 1781 .write_evttype = xgene_pmu_write_evttype, 1782 .write_agentmsk = xgene_pmu_v3_write_agentmsk, 1783 .write_agent1msk = xgene_pmu_v3_write_agent1msk, 1784 .enable_counter = xgene_pmu_enable_counter, 1785 .disable_counter = xgene_pmu_disable_counter, 1786 .enable_counter_int = xgene_pmu_enable_counter_int, 1787 .disable_counter_int = xgene_pmu_disable_counter_int, 1788 .reset_counters = xgene_pmu_reset_counters, 1789 .start_counters = xgene_pmu_start_counters, 1790 .stop_counters = xgene_pmu_stop_counters, 1791 }; 1792 1793 static const struct of_device_id xgene_pmu_of_match[] = { 1794 { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data }, 1795 { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data }, 1796 {}, 1797 }; 1798 MODULE_DEVICE_TABLE(of, xgene_pmu_of_match); 1799 #ifdef CONFIG_ACPI 1800 static const struct acpi_device_id xgene_pmu_acpi_match[] = { 1801 {"APMC0D5B", PCP_PMU_V1}, 1802 {"APMC0D5C", PCP_PMU_V2}, 1803 {"APMC0D83", PCP_PMU_V3}, 1804 {}, 1805 }; 1806 MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match); 1807 #endif 1808 1809 static int xgene_pmu_probe(struct platform_device *pdev) 1810 { 1811 const struct xgene_pmu_data *dev_data; 1812 const struct of_device_id *of_id; 1813 struct xgene_pmu *xgene_pmu; 1814 struct resource *res; 1815 int irq, rc; 1816 int version; 1817 1818 xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL); 1819 if (!xgene_pmu) 1820 return -ENOMEM; 1821 xgene_pmu->dev = &pdev->dev; 1822 platform_set_drvdata(pdev, xgene_pmu); 1823 1824 version = -EINVAL; 1825 of_id = of_match_device(xgene_pmu_of_match, &pdev->dev); 1826 if (of_id) { 1827 dev_data = (const struct xgene_pmu_data *) of_id->data; 1828 version = dev_data->id; 1829 } 1830 1831 #ifdef CONFIG_ACPI 1832 if (ACPI_COMPANION(&pdev->dev)) { 1833 const struct acpi_device_id *acpi_id; 1834 1835 acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev); 1836 if (acpi_id) 1837 version = (int) acpi_id->driver_data; 1838 } 1839 #endif 1840 if (version < 0) 1841 return -ENODEV; 1842 1843 if (version == PCP_PMU_V3) 1844 xgene_pmu->ops = &xgene_pmu_v3_ops; 1845 else 1846 xgene_pmu->ops = &xgene_pmu_ops; 1847 1848 INIT_LIST_HEAD(&xgene_pmu->l3cpmus); 1849 INIT_LIST_HEAD(&xgene_pmu->iobpmus); 1850 INIT_LIST_HEAD(&xgene_pmu->mcbpmus); 1851 INIT_LIST_HEAD(&xgene_pmu->mcpmus); 1852 1853 xgene_pmu->version = version; 1854 dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version); 1855 1856 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1857 xgene_pmu->pcppmu_csr = devm_ioremap_resource(&pdev->dev, res); 1858 if (IS_ERR(xgene_pmu->pcppmu_csr)) { 1859 dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n"); 1860 return PTR_ERR(xgene_pmu->pcppmu_csr); 1861 } 1862 1863 irq = platform_get_irq(pdev, 0); 1864 if (irq < 0) { 1865 dev_err(&pdev->dev, "No IRQ resource\n"); 1866 return -EINVAL; 1867 } 1868 rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr, 1869 IRQF_NOBALANCING | IRQF_NO_THREAD, 1870 dev_name(&pdev->dev), xgene_pmu); 1871 if (rc) { 1872 dev_err(&pdev->dev, "Could not request IRQ %d\n", irq); 1873 return rc; 1874 } 1875 1876 raw_spin_lock_init(&xgene_pmu->lock); 1877 1878 /* Check for active MCBs and MCUs */ 1879 rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev); 1880 if (rc) { 1881 dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n"); 1882 xgene_pmu->mcb_active_mask = 0x1; 1883 xgene_pmu->mc_active_mask = 0x1; 1884 } 1885 1886 /* Pick one core to use for cpumask attributes */ 1887 cpumask_set_cpu(smp_processor_id(), &xgene_pmu->cpu); 1888 1889 /* Make sure that the overflow interrupt is handled by this CPU */ 1890 rc = irq_set_affinity(irq, &xgene_pmu->cpu); 1891 if (rc) { 1892 dev_err(&pdev->dev, "Failed to set interrupt affinity!\n"); 1893 return rc; 1894 } 1895 1896 /* Walk through the tree for all PMU perf devices */ 1897 rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev); 1898 if (rc) { 1899 dev_err(&pdev->dev, "No PMU perf devices found!\n"); 1900 return rc; 1901 } 1902 1903 /* Enable interrupt */ 1904 xgene_pmu->ops->unmask_int(xgene_pmu); 1905 1906 return 0; 1907 } 1908 1909 static void 1910 xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus) 1911 { 1912 struct xgene_pmu_dev_ctx *ctx; 1913 1914 list_for_each_entry(ctx, pmus, next) { 1915 perf_pmu_unregister(&ctx->pmu_dev->pmu); 1916 } 1917 } 1918 1919 static int xgene_pmu_remove(struct platform_device *pdev) 1920 { 1921 struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev); 1922 1923 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus); 1924 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus); 1925 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus); 1926 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus); 1927 1928 return 0; 1929 } 1930 1931 static struct platform_driver xgene_pmu_driver = { 1932 .probe = xgene_pmu_probe, 1933 .remove = xgene_pmu_remove, 1934 .driver = { 1935 .name = "xgene-pmu", 1936 .of_match_table = xgene_pmu_of_match, 1937 .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match), 1938 }, 1939 }; 1940 1941 builtin_platform_driver(xgene_pmu_driver); 1942