1832c927dSTai Nguyen /* 2832c927dSTai Nguyen * APM X-Gene SoC PMU (Performance Monitor Unit) 3832c927dSTai Nguyen * 4832c927dSTai Nguyen * Copyright (c) 2016, Applied Micro Circuits Corporation 5832c927dSTai Nguyen * Author: Hoan Tran <hotran@apm.com> 6832c927dSTai Nguyen * Tai Nguyen <ttnguyen@apm.com> 7832c927dSTai Nguyen * 8832c927dSTai Nguyen * This program is free software; you can redistribute it and/or modify it 9832c927dSTai Nguyen * under the terms of the GNU General Public License as published by the 10832c927dSTai Nguyen * Free Software Foundation; either version 2 of the License, or (at your 11832c927dSTai Nguyen * option) any later version. 12832c927dSTai Nguyen * 13832c927dSTai Nguyen * This program is distributed in the hope that it will be useful, 14832c927dSTai Nguyen * but WITHOUT ANY WARRANTY; without even the implied warranty of 15832c927dSTai Nguyen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16832c927dSTai Nguyen * GNU General Public License for more details. 17832c927dSTai Nguyen * 18832c927dSTai Nguyen * You should have received a copy of the GNU General Public License 19832c927dSTai Nguyen * along with this program. If not, see <http://www.gnu.org/licenses/>. 20832c927dSTai Nguyen */ 21832c927dSTai Nguyen 22832c927dSTai Nguyen #include <linux/acpi.h> 23832c927dSTai Nguyen #include <linux/clk.h> 24832c927dSTai Nguyen #include <linux/cpumask.h> 25832c927dSTai Nguyen #include <linux/interrupt.h> 26832c927dSTai Nguyen #include <linux/io.h> 27832c927dSTai Nguyen #include <linux/mfd/syscon.h> 28c0bfc549SStephen Boyd #include <linux/module.h> 29832c927dSTai Nguyen #include <linux/of_address.h> 30832c927dSTai Nguyen #include <linux/of_fdt.h> 31832c927dSTai Nguyen #include <linux/of_irq.h> 32832c927dSTai Nguyen #include <linux/of_platform.h> 33832c927dSTai Nguyen #include <linux/perf_event.h> 34832c927dSTai Nguyen #include <linux/platform_device.h> 35832c927dSTai Nguyen #include <linux/regmap.h> 36832c927dSTai Nguyen #include <linux/slab.h> 37832c927dSTai Nguyen 38832c927dSTai Nguyen #define CSW_CSWCR 0x0000 39832c927dSTai Nguyen #define CSW_CSWCR_DUALMCB_MASK BIT(0) 40832c927dSTai Nguyen #define MCBADDRMR 0x0000 41832c927dSTai Nguyen #define MCBADDRMR_DUALMCU_MODE_MASK BIT(2) 42832c927dSTai Nguyen 43832c927dSTai Nguyen #define PCPPMU_INTSTATUS_REG 0x000 44832c927dSTai Nguyen #define PCPPMU_INTMASK_REG 0x004 45832c927dSTai Nguyen #define PCPPMU_INTMASK 0x0000000F 46832c927dSTai Nguyen #define PCPPMU_INTENMASK 0xFFFFFFFF 47832c927dSTai Nguyen #define PCPPMU_INTCLRMASK 0xFFFFFFF0 48832c927dSTai Nguyen #define PCPPMU_INT_MCU BIT(0) 49832c927dSTai Nguyen #define PCPPMU_INT_MCB BIT(1) 50832c927dSTai Nguyen #define PCPPMU_INT_L3C BIT(2) 51832c927dSTai Nguyen #define PCPPMU_INT_IOB BIT(3) 52832c927dSTai Nguyen 53832c927dSTai Nguyen #define PMU_MAX_COUNTERS 4 54832c927dSTai Nguyen #define PMU_CNT_MAX_PERIOD 0x100000000ULL 55832c927dSTai Nguyen #define PMU_OVERFLOW_MASK 0xF 56832c927dSTai Nguyen #define PMU_PMCR_E BIT(0) 57832c927dSTai Nguyen #define PMU_PMCR_P BIT(1) 58832c927dSTai Nguyen 59832c927dSTai Nguyen #define PMU_PMEVCNTR0 0x000 60832c927dSTai Nguyen #define PMU_PMEVCNTR1 0x004 61832c927dSTai Nguyen #define PMU_PMEVCNTR2 0x008 62832c927dSTai Nguyen #define PMU_PMEVCNTR3 0x00C 63832c927dSTai Nguyen #define PMU_PMEVTYPER0 0x400 64832c927dSTai Nguyen #define PMU_PMEVTYPER1 0x404 65832c927dSTai Nguyen #define PMU_PMEVTYPER2 0x408 66832c927dSTai Nguyen #define PMU_PMEVTYPER3 0x40C 67832c927dSTai Nguyen #define PMU_PMAMR0 0xA00 68832c927dSTai Nguyen #define PMU_PMAMR1 0xA04 69832c927dSTai Nguyen #define PMU_PMCNTENSET 0xC00 70832c927dSTai Nguyen #define PMU_PMCNTENCLR 0xC20 71832c927dSTai Nguyen #define PMU_PMINTENSET 0xC40 72832c927dSTai Nguyen #define PMU_PMINTENCLR 0xC60 73832c927dSTai Nguyen #define PMU_PMOVSR 0xC80 74832c927dSTai Nguyen #define PMU_PMCR 0xE04 75832c927dSTai Nguyen 76832c927dSTai Nguyen #define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu) 77832c927dSTai Nguyen #define GET_CNTR(ev) (ev->hw.idx) 78832c927dSTai Nguyen #define GET_EVENTID(ev) (ev->hw.config & 0xFFULL) 79832c927dSTai Nguyen #define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL) 80832c927dSTai Nguyen #define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL) 81832c927dSTai Nguyen 82832c927dSTai Nguyen struct hw_pmu_info { 83832c927dSTai Nguyen u32 type; 84832c927dSTai Nguyen u32 enable_mask; 85832c927dSTai Nguyen void __iomem *csr; 86832c927dSTai Nguyen }; 87832c927dSTai Nguyen 88832c927dSTai Nguyen struct xgene_pmu_dev { 89832c927dSTai Nguyen struct hw_pmu_info *inf; 90832c927dSTai Nguyen struct xgene_pmu *parent; 91832c927dSTai Nguyen struct pmu pmu; 92832c927dSTai Nguyen u8 max_counters; 93832c927dSTai Nguyen DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS); 94832c927dSTai Nguyen u64 max_period; 95832c927dSTai Nguyen const struct attribute_group **attr_groups; 96832c927dSTai Nguyen struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS]; 97832c927dSTai Nguyen }; 98832c927dSTai Nguyen 99e35e0a04SHoan Tran struct xgene_pmu_ops { 100e35e0a04SHoan Tran void (*mask_int)(struct xgene_pmu *pmu); 101e35e0a04SHoan Tran void (*unmask_int)(struct xgene_pmu *pmu); 102e35e0a04SHoan Tran u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx); 103e35e0a04SHoan Tran void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val); 104e35e0a04SHoan Tran void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val); 105e35e0a04SHoan Tran void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val); 106e35e0a04SHoan Tran void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val); 107e35e0a04SHoan Tran void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx); 108e35e0a04SHoan Tran void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx); 109e35e0a04SHoan Tran void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx); 110e35e0a04SHoan Tran void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx); 111e35e0a04SHoan Tran void (*reset_counters)(struct xgene_pmu_dev *pmu_dev); 112e35e0a04SHoan Tran void (*start_counters)(struct xgene_pmu_dev *pmu_dev); 113e35e0a04SHoan Tran void (*stop_counters)(struct xgene_pmu_dev *pmu_dev); 114e35e0a04SHoan Tran }; 115e35e0a04SHoan Tran 116832c927dSTai Nguyen struct xgene_pmu { 117832c927dSTai Nguyen struct device *dev; 118832c927dSTai Nguyen int version; 119832c927dSTai Nguyen void __iomem *pcppmu_csr; 120832c927dSTai Nguyen u32 mcb_active_mask; 121832c927dSTai Nguyen u32 mc_active_mask; 122832c927dSTai Nguyen cpumask_t cpu; 123832c927dSTai Nguyen raw_spinlock_t lock; 124e35e0a04SHoan Tran const struct xgene_pmu_ops *ops; 125832c927dSTai Nguyen struct list_head l3cpmus; 126832c927dSTai Nguyen struct list_head iobpmus; 127832c927dSTai Nguyen struct list_head mcbpmus; 128832c927dSTai Nguyen struct list_head mcpmus; 129832c927dSTai Nguyen }; 130832c927dSTai Nguyen 131832c927dSTai Nguyen struct xgene_pmu_dev_ctx { 132832c927dSTai Nguyen char *name; 133832c927dSTai Nguyen struct list_head next; 134832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev; 135832c927dSTai Nguyen struct hw_pmu_info inf; 136832c927dSTai Nguyen }; 137832c927dSTai Nguyen 138832c927dSTai Nguyen struct xgene_pmu_data { 139832c927dSTai Nguyen int id; 140832c927dSTai Nguyen u32 data; 141832c927dSTai Nguyen }; 142832c927dSTai Nguyen 143832c927dSTai Nguyen enum xgene_pmu_version { 144832c927dSTai Nguyen PCP_PMU_V1 = 1, 145832c927dSTai Nguyen PCP_PMU_V2, 146832c927dSTai Nguyen }; 147832c927dSTai Nguyen 148832c927dSTai Nguyen enum xgene_pmu_dev_type { 149832c927dSTai Nguyen PMU_TYPE_L3C = 0, 150832c927dSTai Nguyen PMU_TYPE_IOB, 151832c927dSTai Nguyen PMU_TYPE_MCB, 152832c927dSTai Nguyen PMU_TYPE_MC, 153832c927dSTai Nguyen }; 154832c927dSTai Nguyen 155832c927dSTai Nguyen /* 156832c927dSTai Nguyen * sysfs format attributes 157832c927dSTai Nguyen */ 158832c927dSTai Nguyen static ssize_t xgene_pmu_format_show(struct device *dev, 159832c927dSTai Nguyen struct device_attribute *attr, char *buf) 160832c927dSTai Nguyen { 161832c927dSTai Nguyen struct dev_ext_attribute *eattr; 162832c927dSTai Nguyen 163832c927dSTai Nguyen eattr = container_of(attr, struct dev_ext_attribute, attr); 164832c927dSTai Nguyen return sprintf(buf, "%s\n", (char *) eattr->var); 165832c927dSTai Nguyen } 166832c927dSTai Nguyen 167832c927dSTai Nguyen #define XGENE_PMU_FORMAT_ATTR(_name, _config) \ 168832c927dSTai Nguyen (&((struct dev_ext_attribute[]) { \ 169832c927dSTai Nguyen { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \ 170832c927dSTai Nguyen .var = (void *) _config, } \ 171832c927dSTai Nguyen })[0].attr.attr) 172832c927dSTai Nguyen 173832c927dSTai Nguyen static struct attribute *l3c_pmu_format_attrs[] = { 174832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"), 175832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"), 176832c927dSTai Nguyen NULL, 177832c927dSTai Nguyen }; 178832c927dSTai Nguyen 179832c927dSTai Nguyen static struct attribute *iob_pmu_format_attrs[] = { 180832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"), 181832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"), 182832c927dSTai Nguyen NULL, 183832c927dSTai Nguyen }; 184832c927dSTai Nguyen 185832c927dSTai Nguyen static struct attribute *mcb_pmu_format_attrs[] = { 186832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"), 187832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"), 188832c927dSTai Nguyen NULL, 189832c927dSTai Nguyen }; 190832c927dSTai Nguyen 191832c927dSTai Nguyen static struct attribute *mc_pmu_format_attrs[] = { 192832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"), 193832c927dSTai Nguyen NULL, 194832c927dSTai Nguyen }; 195832c927dSTai Nguyen 196832c927dSTai Nguyen static const struct attribute_group l3c_pmu_format_attr_group = { 197832c927dSTai Nguyen .name = "format", 198832c927dSTai Nguyen .attrs = l3c_pmu_format_attrs, 199832c927dSTai Nguyen }; 200832c927dSTai Nguyen 201832c927dSTai Nguyen static const struct attribute_group iob_pmu_format_attr_group = { 202832c927dSTai Nguyen .name = "format", 203832c927dSTai Nguyen .attrs = iob_pmu_format_attrs, 204832c927dSTai Nguyen }; 205832c927dSTai Nguyen 206832c927dSTai Nguyen static const struct attribute_group mcb_pmu_format_attr_group = { 207832c927dSTai Nguyen .name = "format", 208832c927dSTai Nguyen .attrs = mcb_pmu_format_attrs, 209832c927dSTai Nguyen }; 210832c927dSTai Nguyen 211832c927dSTai Nguyen static const struct attribute_group mc_pmu_format_attr_group = { 212832c927dSTai Nguyen .name = "format", 213832c927dSTai Nguyen .attrs = mc_pmu_format_attrs, 214832c927dSTai Nguyen }; 215832c927dSTai Nguyen 216832c927dSTai Nguyen /* 217832c927dSTai Nguyen * sysfs event attributes 218832c927dSTai Nguyen */ 219832c927dSTai Nguyen static ssize_t xgene_pmu_event_show(struct device *dev, 220832c927dSTai Nguyen struct device_attribute *attr, char *buf) 221832c927dSTai Nguyen { 222832c927dSTai Nguyen struct dev_ext_attribute *eattr; 223832c927dSTai Nguyen 224832c927dSTai Nguyen eattr = container_of(attr, struct dev_ext_attribute, attr); 225832c927dSTai Nguyen return sprintf(buf, "config=0x%lx\n", (unsigned long) eattr->var); 226832c927dSTai Nguyen } 227832c927dSTai Nguyen 228832c927dSTai Nguyen #define XGENE_PMU_EVENT_ATTR(_name, _config) \ 229832c927dSTai Nguyen (&((struct dev_ext_attribute[]) { \ 230832c927dSTai Nguyen { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_event_show, NULL), \ 231832c927dSTai Nguyen .var = (void *) _config, } \ 232832c927dSTai Nguyen })[0].attr.attr) 233832c927dSTai Nguyen 234832c927dSTai Nguyen static struct attribute *l3c_pmu_events_attrs[] = { 235832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 236832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 237832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(read-hit, 0x02), 238832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(read-miss, 0x03), 239832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06), 240832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07), 241832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(tq-full, 0x08), 242832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(ackq-full, 0x09), 243832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a), 244832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b), 245832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(odb-full, 0x0c), 246832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d), 247832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e), 248832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f), 249832c927dSTai Nguyen NULL, 250832c927dSTai Nguyen }; 251832c927dSTai Nguyen 252832c927dSTai Nguyen static struct attribute *iob_pmu_events_attrs[] = { 253832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 254832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 255832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-read, 0x02), 256832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03), 257832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-read, 0x04), 258832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05), 259832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06), 260832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07), 261832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-write, 0x10), 262832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11), 263832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-write, 0x13), 264832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14), 265832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16), 266832c927dSTai Nguyen NULL, 267832c927dSTai Nguyen }; 268832c927dSTai Nguyen 269832c927dSTai Nguyen static struct attribute *mcb_pmu_events_attrs[] = { 270832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 271832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 272832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-read, 0x02), 273832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03), 274832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04), 275832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05), 276832c927dSTai Nguyen NULL, 277832c927dSTai Nguyen }; 278832c927dSTai Nguyen 279832c927dSTai Nguyen static struct attribute *mc_pmu_events_attrs[] = { 280832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 281832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 282832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02), 283832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03), 284832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04), 285832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05), 286832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06), 287832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07), 288832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08), 289832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09), 290832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a), 291832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b), 292832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c), 293832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d), 294832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e), 295832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f), 296832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10), 297832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11), 298832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-request, 0x12), 299832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13), 300832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14), 301832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15), 302832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16), 303832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17), 304832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18), 305832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19), 306832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a), 307832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b), 308832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c), 309832c927dSTai Nguyen NULL, 310832c927dSTai Nguyen }; 311832c927dSTai Nguyen 312832c927dSTai Nguyen static const struct attribute_group l3c_pmu_events_attr_group = { 313832c927dSTai Nguyen .name = "events", 314832c927dSTai Nguyen .attrs = l3c_pmu_events_attrs, 315832c927dSTai Nguyen }; 316832c927dSTai Nguyen 317832c927dSTai Nguyen static const struct attribute_group iob_pmu_events_attr_group = { 318832c927dSTai Nguyen .name = "events", 319832c927dSTai Nguyen .attrs = iob_pmu_events_attrs, 320832c927dSTai Nguyen }; 321832c927dSTai Nguyen 322832c927dSTai Nguyen static const struct attribute_group mcb_pmu_events_attr_group = { 323832c927dSTai Nguyen .name = "events", 324832c927dSTai Nguyen .attrs = mcb_pmu_events_attrs, 325832c927dSTai Nguyen }; 326832c927dSTai Nguyen 327832c927dSTai Nguyen static const struct attribute_group mc_pmu_events_attr_group = { 328832c927dSTai Nguyen .name = "events", 329832c927dSTai Nguyen .attrs = mc_pmu_events_attrs, 330832c927dSTai Nguyen }; 331832c927dSTai Nguyen 332832c927dSTai Nguyen /* 333832c927dSTai Nguyen * sysfs cpumask attributes 334832c927dSTai Nguyen */ 335832c927dSTai Nguyen static ssize_t xgene_pmu_cpumask_show(struct device *dev, 336832c927dSTai Nguyen struct device_attribute *attr, char *buf) 337832c927dSTai Nguyen { 338832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev)); 339832c927dSTai Nguyen 340832c927dSTai Nguyen return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu); 341832c927dSTai Nguyen } 342832c927dSTai Nguyen 343832c927dSTai Nguyen static DEVICE_ATTR(cpumask, S_IRUGO, xgene_pmu_cpumask_show, NULL); 344832c927dSTai Nguyen 345832c927dSTai Nguyen static struct attribute *xgene_pmu_cpumask_attrs[] = { 346832c927dSTai Nguyen &dev_attr_cpumask.attr, 347832c927dSTai Nguyen NULL, 348832c927dSTai Nguyen }; 349832c927dSTai Nguyen 350832c927dSTai Nguyen static const struct attribute_group pmu_cpumask_attr_group = { 351832c927dSTai Nguyen .attrs = xgene_pmu_cpumask_attrs, 352832c927dSTai Nguyen }; 353832c927dSTai Nguyen 354832c927dSTai Nguyen /* 355832c927dSTai Nguyen * Per PMU device attribute groups 356832c927dSTai Nguyen */ 357832c927dSTai Nguyen static const struct attribute_group *l3c_pmu_attr_groups[] = { 358832c927dSTai Nguyen &l3c_pmu_format_attr_group, 359832c927dSTai Nguyen &pmu_cpumask_attr_group, 360832c927dSTai Nguyen &l3c_pmu_events_attr_group, 361832c927dSTai Nguyen NULL 362832c927dSTai Nguyen }; 363832c927dSTai Nguyen 364832c927dSTai Nguyen static const struct attribute_group *iob_pmu_attr_groups[] = { 365832c927dSTai Nguyen &iob_pmu_format_attr_group, 366832c927dSTai Nguyen &pmu_cpumask_attr_group, 367832c927dSTai Nguyen &iob_pmu_events_attr_group, 368832c927dSTai Nguyen NULL 369832c927dSTai Nguyen }; 370832c927dSTai Nguyen 371832c927dSTai Nguyen static const struct attribute_group *mcb_pmu_attr_groups[] = { 372832c927dSTai Nguyen &mcb_pmu_format_attr_group, 373832c927dSTai Nguyen &pmu_cpumask_attr_group, 374832c927dSTai Nguyen &mcb_pmu_events_attr_group, 375832c927dSTai Nguyen NULL 376832c927dSTai Nguyen }; 377832c927dSTai Nguyen 378832c927dSTai Nguyen static const struct attribute_group *mc_pmu_attr_groups[] = { 379832c927dSTai Nguyen &mc_pmu_format_attr_group, 380832c927dSTai Nguyen &pmu_cpumask_attr_group, 381832c927dSTai Nguyen &mc_pmu_events_attr_group, 382832c927dSTai Nguyen NULL 383832c927dSTai Nguyen }; 384832c927dSTai Nguyen 385832c927dSTai Nguyen static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev) 386832c927dSTai Nguyen { 387832c927dSTai Nguyen int cntr; 388832c927dSTai Nguyen 389832c927dSTai Nguyen cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask, 390832c927dSTai Nguyen pmu_dev->max_counters); 391832c927dSTai Nguyen if (cntr == pmu_dev->max_counters) 392832c927dSTai Nguyen return -ENOSPC; 393832c927dSTai Nguyen set_bit(cntr, pmu_dev->cntr_assign_mask); 394832c927dSTai Nguyen 395832c927dSTai Nguyen return cntr; 396832c927dSTai Nguyen } 397832c927dSTai Nguyen 398832c927dSTai Nguyen static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr) 399832c927dSTai Nguyen { 400832c927dSTai Nguyen clear_bit(cntr, pmu_dev->cntr_assign_mask); 401832c927dSTai Nguyen } 402832c927dSTai Nguyen 403832c927dSTai Nguyen static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu) 404832c927dSTai Nguyen { 405832c927dSTai Nguyen writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 406832c927dSTai Nguyen } 407832c927dSTai Nguyen 408832c927dSTai Nguyen static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu) 409832c927dSTai Nguyen { 410832c927dSTai Nguyen writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 411832c927dSTai Nguyen } 412832c927dSTai Nguyen 413e35e0a04SHoan Tran static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev, 414e35e0a04SHoan Tran int idx) 415832c927dSTai Nguyen { 416832c927dSTai Nguyen return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); 417832c927dSTai Nguyen } 418832c927dSTai Nguyen 419832c927dSTai Nguyen static inline void 420e35e0a04SHoan Tran xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) 421832c927dSTai Nguyen { 422832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); 423832c927dSTai Nguyen } 424832c927dSTai Nguyen 425832c927dSTai Nguyen static inline void 426832c927dSTai Nguyen xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val) 427832c927dSTai Nguyen { 428832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx)); 429832c927dSTai Nguyen } 430832c927dSTai Nguyen 431832c927dSTai Nguyen static inline void 432832c927dSTai Nguyen xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) 433832c927dSTai Nguyen { 434832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMAMR0); 435832c927dSTai Nguyen } 436832c927dSTai Nguyen 437832c927dSTai Nguyen static inline void 438832c927dSTai Nguyen xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) 439832c927dSTai Nguyen { 440832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMAMR1); 441832c927dSTai Nguyen } 442832c927dSTai Nguyen 443832c927dSTai Nguyen static inline void 444832c927dSTai Nguyen xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx) 445832c927dSTai Nguyen { 446832c927dSTai Nguyen u32 val; 447832c927dSTai Nguyen 448832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET); 449832c927dSTai Nguyen val |= 1 << idx; 450832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET); 451832c927dSTai Nguyen } 452832c927dSTai Nguyen 453832c927dSTai Nguyen static inline void 454832c927dSTai Nguyen xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx) 455832c927dSTai Nguyen { 456832c927dSTai Nguyen u32 val; 457832c927dSTai Nguyen 458832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR); 459832c927dSTai Nguyen val |= 1 << idx; 460832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR); 461832c927dSTai Nguyen } 462832c927dSTai Nguyen 463832c927dSTai Nguyen static inline void 464832c927dSTai Nguyen xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx) 465832c927dSTai Nguyen { 466832c927dSTai Nguyen u32 val; 467832c927dSTai Nguyen 468832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMINTENSET); 469832c927dSTai Nguyen val |= 1 << idx; 470832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMINTENSET); 471832c927dSTai Nguyen } 472832c927dSTai Nguyen 473832c927dSTai Nguyen static inline void 474832c927dSTai Nguyen xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx) 475832c927dSTai Nguyen { 476832c927dSTai Nguyen u32 val; 477832c927dSTai Nguyen 478832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR); 479832c927dSTai Nguyen val |= 1 << idx; 480832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR); 481832c927dSTai Nguyen } 482832c927dSTai Nguyen 483832c927dSTai Nguyen static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev) 484832c927dSTai Nguyen { 485832c927dSTai Nguyen u32 val; 486832c927dSTai Nguyen 487832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCR); 488832c927dSTai Nguyen val |= PMU_PMCR_P; 489832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCR); 490832c927dSTai Nguyen } 491832c927dSTai Nguyen 492832c927dSTai Nguyen static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev) 493832c927dSTai Nguyen { 494832c927dSTai Nguyen u32 val; 495832c927dSTai Nguyen 496832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCR); 497832c927dSTai Nguyen val |= PMU_PMCR_E; 498832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCR); 499832c927dSTai Nguyen } 500832c927dSTai Nguyen 501832c927dSTai Nguyen static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev) 502832c927dSTai Nguyen { 503832c927dSTai Nguyen u32 val; 504832c927dSTai Nguyen 505832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCR); 506832c927dSTai Nguyen val &= ~PMU_PMCR_E; 507832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCR); 508832c927dSTai Nguyen } 509832c927dSTai Nguyen 510832c927dSTai Nguyen static void xgene_perf_pmu_enable(struct pmu *pmu) 511832c927dSTai Nguyen { 512832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu); 513e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 514832c927dSTai Nguyen int enabled = bitmap_weight(pmu_dev->cntr_assign_mask, 515832c927dSTai Nguyen pmu_dev->max_counters); 516832c927dSTai Nguyen 517832c927dSTai Nguyen if (!enabled) 518832c927dSTai Nguyen return; 519832c927dSTai Nguyen 520e35e0a04SHoan Tran xgene_pmu->ops->start_counters(pmu_dev); 521832c927dSTai Nguyen } 522832c927dSTai Nguyen 523832c927dSTai Nguyen static void xgene_perf_pmu_disable(struct pmu *pmu) 524832c927dSTai Nguyen { 525832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu); 526e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 527832c927dSTai Nguyen 528e35e0a04SHoan Tran xgene_pmu->ops->stop_counters(pmu_dev); 529832c927dSTai Nguyen } 530832c927dSTai Nguyen 531832c927dSTai Nguyen static int xgene_perf_event_init(struct perf_event *event) 532832c927dSTai Nguyen { 533832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 534832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 535832c927dSTai Nguyen struct perf_event *sibling; 536832c927dSTai Nguyen 537832c927dSTai Nguyen /* Test the event attr type check for PMU enumeration */ 538832c927dSTai Nguyen if (event->attr.type != event->pmu->type) 539832c927dSTai Nguyen return -ENOENT; 540832c927dSTai Nguyen 541832c927dSTai Nguyen /* 542832c927dSTai Nguyen * SOC PMU counters are shared across all cores. 543832c927dSTai Nguyen * Therefore, it does not support per-process mode. 544832c927dSTai Nguyen * Also, it does not support event sampling mode. 545832c927dSTai Nguyen */ 546832c927dSTai Nguyen if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 547832c927dSTai Nguyen return -EINVAL; 548832c927dSTai Nguyen 549832c927dSTai Nguyen /* SOC counters do not have usr/os/guest/host bits */ 550832c927dSTai Nguyen if (event->attr.exclude_user || event->attr.exclude_kernel || 551832c927dSTai Nguyen event->attr.exclude_host || event->attr.exclude_guest) 552832c927dSTai Nguyen return -EINVAL; 553832c927dSTai Nguyen 554832c927dSTai Nguyen if (event->cpu < 0) 555832c927dSTai Nguyen return -EINVAL; 556832c927dSTai Nguyen /* 557832c927dSTai Nguyen * Many perf core operations (eg. events rotation) operate on a 558832c927dSTai Nguyen * single CPU context. This is obvious for CPU PMUs, where one 559832c927dSTai Nguyen * expects the same sets of events being observed on all CPUs, 560832c927dSTai Nguyen * but can lead to issues for off-core PMUs, where each 561832c927dSTai Nguyen * event could be theoretically assigned to a different CPU. To 562832c927dSTai Nguyen * mitigate this, we enforce CPU assignment to one, selected 563832c927dSTai Nguyen * processor (the one described in the "cpumask" attribute). 564832c927dSTai Nguyen */ 565832c927dSTai Nguyen event->cpu = cpumask_first(&pmu_dev->parent->cpu); 566832c927dSTai Nguyen 567832c927dSTai Nguyen hw->config = event->attr.config; 568832c927dSTai Nguyen /* 569832c927dSTai Nguyen * Each bit of the config1 field represents an agent from which the 570832c927dSTai Nguyen * request of the event come. The event is counted only if it's caused 571832c927dSTai Nguyen * by a request of an agent has the bit cleared. 572832c927dSTai Nguyen * By default, the event is counted for all agents. 573832c927dSTai Nguyen */ 574832c927dSTai Nguyen hw->config_base = event->attr.config1; 575832c927dSTai Nguyen 576832c927dSTai Nguyen /* 577832c927dSTai Nguyen * We must NOT create groups containing mixed PMUs, although software 578832c927dSTai Nguyen * events are acceptable 579832c927dSTai Nguyen */ 580832c927dSTai Nguyen if (event->group_leader->pmu != event->pmu && 581832c927dSTai Nguyen !is_software_event(event->group_leader)) 582832c927dSTai Nguyen return -EINVAL; 583832c927dSTai Nguyen 584832c927dSTai Nguyen list_for_each_entry(sibling, &event->group_leader->sibling_list, 585832c927dSTai Nguyen group_entry) 586832c927dSTai Nguyen if (sibling->pmu != event->pmu && 587832c927dSTai Nguyen !is_software_event(sibling)) 588832c927dSTai Nguyen return -EINVAL; 589832c927dSTai Nguyen 590832c927dSTai Nguyen return 0; 591832c927dSTai Nguyen } 592832c927dSTai Nguyen 593832c927dSTai Nguyen static void xgene_perf_enable_event(struct perf_event *event) 594832c927dSTai Nguyen { 595832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 596e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 597832c927dSTai Nguyen 598e35e0a04SHoan Tran xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event), 599e35e0a04SHoan Tran GET_EVENTID(event)); 600e35e0a04SHoan Tran xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event))); 601832c927dSTai Nguyen if (pmu_dev->inf->type == PMU_TYPE_IOB) 602e35e0a04SHoan Tran xgene_pmu->ops->write_agent1msk(pmu_dev, 603e35e0a04SHoan Tran ~((u32)GET_AGENT1ID(event))); 604832c927dSTai Nguyen 605e35e0a04SHoan Tran xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event)); 606e35e0a04SHoan Tran xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event)); 607832c927dSTai Nguyen } 608832c927dSTai Nguyen 609832c927dSTai Nguyen static void xgene_perf_disable_event(struct perf_event *event) 610832c927dSTai Nguyen { 611832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 612e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 613832c927dSTai Nguyen 614e35e0a04SHoan Tran xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event)); 615e35e0a04SHoan Tran xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event)); 616832c927dSTai Nguyen } 617832c927dSTai Nguyen 618832c927dSTai Nguyen static void xgene_perf_event_set_period(struct perf_event *event) 619832c927dSTai Nguyen { 620832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 621e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 622832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 623832c927dSTai Nguyen /* 624832c927dSTai Nguyen * The X-Gene PMU counters have a period of 2^32. To account for the 625832c927dSTai Nguyen * possiblity of extreme interrupt latency we program for a period of 626832c927dSTai Nguyen * half that. Hopefully we can handle the interrupt before another 2^31 627832c927dSTai Nguyen * events occur and the counter overtakes its previous value. 628832c927dSTai Nguyen */ 629832c927dSTai Nguyen u64 val = 1ULL << 31; 630832c927dSTai Nguyen 631832c927dSTai Nguyen local64_set(&hw->prev_count, val); 632e35e0a04SHoan Tran xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val); 633832c927dSTai Nguyen } 634832c927dSTai Nguyen 635832c927dSTai Nguyen static void xgene_perf_event_update(struct perf_event *event) 636832c927dSTai Nguyen { 637832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 638e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 639832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 640832c927dSTai Nguyen u64 delta, prev_raw_count, new_raw_count; 641832c927dSTai Nguyen 642832c927dSTai Nguyen again: 643832c927dSTai Nguyen prev_raw_count = local64_read(&hw->prev_count); 644e35e0a04SHoan Tran new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event)); 645832c927dSTai Nguyen 646832c927dSTai Nguyen if (local64_cmpxchg(&hw->prev_count, prev_raw_count, 647832c927dSTai Nguyen new_raw_count) != prev_raw_count) 648832c927dSTai Nguyen goto again; 649832c927dSTai Nguyen 650832c927dSTai Nguyen delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period; 651832c927dSTai Nguyen 652832c927dSTai Nguyen local64_add(delta, &event->count); 653832c927dSTai Nguyen } 654832c927dSTai Nguyen 655832c927dSTai Nguyen static void xgene_perf_read(struct perf_event *event) 656832c927dSTai Nguyen { 657832c927dSTai Nguyen xgene_perf_event_update(event); 658832c927dSTai Nguyen } 659832c927dSTai Nguyen 660832c927dSTai Nguyen static void xgene_perf_start(struct perf_event *event, int flags) 661832c927dSTai Nguyen { 662832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 663e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 664832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 665832c927dSTai Nguyen 666832c927dSTai Nguyen if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED))) 667832c927dSTai Nguyen return; 668832c927dSTai Nguyen 669832c927dSTai Nguyen WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE)); 670832c927dSTai Nguyen hw->state = 0; 671832c927dSTai Nguyen 672832c927dSTai Nguyen xgene_perf_event_set_period(event); 673832c927dSTai Nguyen 674832c927dSTai Nguyen if (flags & PERF_EF_RELOAD) { 675832c927dSTai Nguyen u64 prev_raw_count = local64_read(&hw->prev_count); 676832c927dSTai Nguyen 677e35e0a04SHoan Tran xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event), 678e35e0a04SHoan Tran prev_raw_count); 679832c927dSTai Nguyen } 680832c927dSTai Nguyen 681832c927dSTai Nguyen xgene_perf_enable_event(event); 682832c927dSTai Nguyen perf_event_update_userpage(event); 683832c927dSTai Nguyen } 684832c927dSTai Nguyen 685832c927dSTai Nguyen static void xgene_perf_stop(struct perf_event *event, int flags) 686832c927dSTai Nguyen { 687832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 688832c927dSTai Nguyen u64 config; 689832c927dSTai Nguyen 690832c927dSTai Nguyen if (hw->state & PERF_HES_UPTODATE) 691832c927dSTai Nguyen return; 692832c927dSTai Nguyen 693832c927dSTai Nguyen xgene_perf_disable_event(event); 694832c927dSTai Nguyen WARN_ON_ONCE(hw->state & PERF_HES_STOPPED); 695832c927dSTai Nguyen hw->state |= PERF_HES_STOPPED; 696832c927dSTai Nguyen 697832c927dSTai Nguyen if (hw->state & PERF_HES_UPTODATE) 698832c927dSTai Nguyen return; 699832c927dSTai Nguyen 700832c927dSTai Nguyen config = hw->config; 701832c927dSTai Nguyen xgene_perf_read(event); 702832c927dSTai Nguyen hw->state |= PERF_HES_UPTODATE; 703832c927dSTai Nguyen } 704832c927dSTai Nguyen 705832c927dSTai Nguyen static int xgene_perf_add(struct perf_event *event, int flags) 706832c927dSTai Nguyen { 707832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 708832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 709832c927dSTai Nguyen 710832c927dSTai Nguyen hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 711832c927dSTai Nguyen 712832c927dSTai Nguyen /* Allocate an event counter */ 713832c927dSTai Nguyen hw->idx = get_next_avail_cntr(pmu_dev); 714832c927dSTai Nguyen if (hw->idx < 0) 715832c927dSTai Nguyen return -EAGAIN; 716832c927dSTai Nguyen 717832c927dSTai Nguyen /* Update counter event pointer for Interrupt handler */ 718832c927dSTai Nguyen pmu_dev->pmu_counter_event[hw->idx] = event; 719832c927dSTai Nguyen 720832c927dSTai Nguyen if (flags & PERF_EF_START) 721832c927dSTai Nguyen xgene_perf_start(event, PERF_EF_RELOAD); 722832c927dSTai Nguyen 723832c927dSTai Nguyen return 0; 724832c927dSTai Nguyen } 725832c927dSTai Nguyen 726832c927dSTai Nguyen static void xgene_perf_del(struct perf_event *event, int flags) 727832c927dSTai Nguyen { 728832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 729832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 730832c927dSTai Nguyen 731832c927dSTai Nguyen xgene_perf_stop(event, PERF_EF_UPDATE); 732832c927dSTai Nguyen 733832c927dSTai Nguyen /* clear the assigned counter */ 734832c927dSTai Nguyen clear_avail_cntr(pmu_dev, GET_CNTR(event)); 735832c927dSTai Nguyen 736832c927dSTai Nguyen perf_event_update_userpage(event); 737832c927dSTai Nguyen pmu_dev->pmu_counter_event[hw->idx] = NULL; 738832c927dSTai Nguyen } 739832c927dSTai Nguyen 740832c927dSTai Nguyen static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name) 741832c927dSTai Nguyen { 742832c927dSTai Nguyen struct xgene_pmu *xgene_pmu; 743832c927dSTai Nguyen 744832c927dSTai Nguyen pmu_dev->max_period = PMU_CNT_MAX_PERIOD - 1; 745832c927dSTai Nguyen /* First version PMU supports only single event counter */ 746832c927dSTai Nguyen xgene_pmu = pmu_dev->parent; 747832c927dSTai Nguyen if (xgene_pmu->version == PCP_PMU_V1) 748832c927dSTai Nguyen pmu_dev->max_counters = 1; 749832c927dSTai Nguyen else 750832c927dSTai Nguyen pmu_dev->max_counters = PMU_MAX_COUNTERS; 751832c927dSTai Nguyen 752832c927dSTai Nguyen /* Perf driver registration */ 753832c927dSTai Nguyen pmu_dev->pmu = (struct pmu) { 754832c927dSTai Nguyen .attr_groups = pmu_dev->attr_groups, 755832c927dSTai Nguyen .task_ctx_nr = perf_invalid_context, 756832c927dSTai Nguyen .pmu_enable = xgene_perf_pmu_enable, 757832c927dSTai Nguyen .pmu_disable = xgene_perf_pmu_disable, 758832c927dSTai Nguyen .event_init = xgene_perf_event_init, 759832c927dSTai Nguyen .add = xgene_perf_add, 760832c927dSTai Nguyen .del = xgene_perf_del, 761832c927dSTai Nguyen .start = xgene_perf_start, 762832c927dSTai Nguyen .stop = xgene_perf_stop, 763832c927dSTai Nguyen .read = xgene_perf_read, 764832c927dSTai Nguyen }; 765832c927dSTai Nguyen 766832c927dSTai Nguyen /* Hardware counter init */ 767e35e0a04SHoan Tran xgene_pmu->ops->stop_counters(pmu_dev); 768e35e0a04SHoan Tran xgene_pmu->ops->reset_counters(pmu_dev); 769832c927dSTai Nguyen 770832c927dSTai Nguyen return perf_pmu_register(&pmu_dev->pmu, name, -1); 771832c927dSTai Nguyen } 772832c927dSTai Nguyen 773832c927dSTai Nguyen static int 774832c927dSTai Nguyen xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx) 775832c927dSTai Nguyen { 776832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 777832c927dSTai Nguyen struct xgene_pmu_dev *pmu; 778832c927dSTai Nguyen int rc; 779832c927dSTai Nguyen 780832c927dSTai Nguyen pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL); 781832c927dSTai Nguyen if (!pmu) 782832c927dSTai Nguyen return -ENOMEM; 783832c927dSTai Nguyen pmu->parent = xgene_pmu; 784832c927dSTai Nguyen pmu->inf = &ctx->inf; 785832c927dSTai Nguyen ctx->pmu_dev = pmu; 786832c927dSTai Nguyen 787832c927dSTai Nguyen switch (pmu->inf->type) { 788832c927dSTai Nguyen case PMU_TYPE_L3C: 789832c927dSTai Nguyen pmu->attr_groups = l3c_pmu_attr_groups; 790832c927dSTai Nguyen break; 791832c927dSTai Nguyen case PMU_TYPE_IOB: 792832c927dSTai Nguyen pmu->attr_groups = iob_pmu_attr_groups; 793832c927dSTai Nguyen break; 794832c927dSTai Nguyen case PMU_TYPE_MCB: 795832c927dSTai Nguyen if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask)) 796832c927dSTai Nguyen goto dev_err; 797832c927dSTai Nguyen pmu->attr_groups = mcb_pmu_attr_groups; 798832c927dSTai Nguyen break; 799832c927dSTai Nguyen case PMU_TYPE_MC: 800832c927dSTai Nguyen if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask)) 801832c927dSTai Nguyen goto dev_err; 802832c927dSTai Nguyen pmu->attr_groups = mc_pmu_attr_groups; 803832c927dSTai Nguyen break; 804832c927dSTai Nguyen default: 805832c927dSTai Nguyen return -EINVAL; 806832c927dSTai Nguyen } 807832c927dSTai Nguyen 808832c927dSTai Nguyen rc = xgene_init_perf(pmu, ctx->name); 809832c927dSTai Nguyen if (rc) { 810832c927dSTai Nguyen dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name); 811832c927dSTai Nguyen goto dev_err; 812832c927dSTai Nguyen } 813832c927dSTai Nguyen 814832c927dSTai Nguyen dev_info(dev, "%s PMU registered\n", ctx->name); 815832c927dSTai Nguyen 816832c927dSTai Nguyen return rc; 817832c927dSTai Nguyen 818832c927dSTai Nguyen dev_err: 819832c927dSTai Nguyen devm_kfree(dev, pmu); 820832c927dSTai Nguyen return -ENODEV; 821832c927dSTai Nguyen } 822832c927dSTai Nguyen 823832c927dSTai Nguyen static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev) 824832c927dSTai Nguyen { 825832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = pmu_dev->parent; 826832c927dSTai Nguyen u32 pmovsr; 827832c927dSTai Nguyen int idx; 828832c927dSTai Nguyen 829832c927dSTai Nguyen pmovsr = readl(pmu_dev->inf->csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK; 830832c927dSTai Nguyen if (!pmovsr) 831832c927dSTai Nguyen return; 832832c927dSTai Nguyen 833832c927dSTai Nguyen /* Clear interrupt flag */ 834832c927dSTai Nguyen if (xgene_pmu->version == PCP_PMU_V1) 835832c927dSTai Nguyen writel(0x0, pmu_dev->inf->csr + PMU_PMOVSR); 836832c927dSTai Nguyen else 837832c927dSTai Nguyen writel(pmovsr, pmu_dev->inf->csr + PMU_PMOVSR); 838832c927dSTai Nguyen 839832c927dSTai Nguyen for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) { 840832c927dSTai Nguyen struct perf_event *event = pmu_dev->pmu_counter_event[idx]; 841832c927dSTai Nguyen int overflowed = pmovsr & BIT(idx); 842832c927dSTai Nguyen 843832c927dSTai Nguyen /* Ignore if we don't have an event. */ 844832c927dSTai Nguyen if (!event || !overflowed) 845832c927dSTai Nguyen continue; 846832c927dSTai Nguyen xgene_perf_event_update(event); 847832c927dSTai Nguyen xgene_perf_event_set_period(event); 848832c927dSTai Nguyen } 849832c927dSTai Nguyen } 850832c927dSTai Nguyen 851832c927dSTai Nguyen static irqreturn_t xgene_pmu_isr(int irq, void *dev_id) 852832c927dSTai Nguyen { 853832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 854832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = dev_id; 855832c927dSTai Nguyen unsigned long flags; 856832c927dSTai Nguyen u32 val; 857832c927dSTai Nguyen 858832c927dSTai Nguyen raw_spin_lock_irqsave(&xgene_pmu->lock, flags); 859832c927dSTai Nguyen 860832c927dSTai Nguyen /* Get Interrupt PMU source */ 861832c927dSTai Nguyen val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG); 862832c927dSTai Nguyen if (val & PCPPMU_INT_MCU) { 863832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) { 864832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 865832c927dSTai Nguyen } 866832c927dSTai Nguyen } 867832c927dSTai Nguyen if (val & PCPPMU_INT_MCB) { 868832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) { 869832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 870832c927dSTai Nguyen } 871832c927dSTai Nguyen } 872832c927dSTai Nguyen if (val & PCPPMU_INT_L3C) { 873832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) { 874832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 875832c927dSTai Nguyen } 876832c927dSTai Nguyen } 877832c927dSTai Nguyen if (val & PCPPMU_INT_IOB) { 878832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) { 879832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 880832c927dSTai Nguyen } 881832c927dSTai Nguyen } 882832c927dSTai Nguyen 883832c927dSTai Nguyen raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags); 884832c927dSTai Nguyen 885832c927dSTai Nguyen return IRQ_HANDLED; 886832c927dSTai Nguyen } 887832c927dSTai Nguyen 888832c927dSTai Nguyen static int acpi_pmu_probe_active_mcb_mcu(struct xgene_pmu *xgene_pmu, 889832c927dSTai Nguyen struct platform_device *pdev) 890832c927dSTai Nguyen { 891832c927dSTai Nguyen void __iomem *csw_csr, *mcba_csr, *mcbb_csr; 892832c927dSTai Nguyen struct resource *res; 893832c927dSTai Nguyen unsigned int reg; 894832c927dSTai Nguyen 895832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 896832c927dSTai Nguyen csw_csr = devm_ioremap_resource(&pdev->dev, res); 897832c927dSTai Nguyen if (IS_ERR(csw_csr)) { 898832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n"); 899832c927dSTai Nguyen return PTR_ERR(csw_csr); 900832c927dSTai Nguyen } 901832c927dSTai Nguyen 902832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 903832c927dSTai Nguyen mcba_csr = devm_ioremap_resource(&pdev->dev, res); 904832c927dSTai Nguyen if (IS_ERR(mcba_csr)) { 905832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n"); 906832c927dSTai Nguyen return PTR_ERR(mcba_csr); 907832c927dSTai Nguyen } 908832c927dSTai Nguyen 909832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 910832c927dSTai Nguyen mcbb_csr = devm_ioremap_resource(&pdev->dev, res); 911832c927dSTai Nguyen if (IS_ERR(mcbb_csr)) { 912832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n"); 913832c927dSTai Nguyen return PTR_ERR(mcbb_csr); 914832c927dSTai Nguyen } 915832c927dSTai Nguyen 916832c927dSTai Nguyen reg = readl(csw_csr + CSW_CSWCR); 917832c927dSTai Nguyen if (reg & CSW_CSWCR_DUALMCB_MASK) { 918832c927dSTai Nguyen /* Dual MCB active */ 919832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x3; 920832c927dSTai Nguyen /* Probe all active MC(s) */ 921832c927dSTai Nguyen reg = readl(mcbb_csr + CSW_CSWCR); 922832c927dSTai Nguyen xgene_pmu->mc_active_mask = 923832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; 924832c927dSTai Nguyen } else { 925832c927dSTai Nguyen /* Single MCB active */ 926832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x1; 927832c927dSTai Nguyen /* Probe all active MC(s) */ 928832c927dSTai Nguyen reg = readl(mcba_csr + CSW_CSWCR); 929832c927dSTai Nguyen xgene_pmu->mc_active_mask = 930832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; 931832c927dSTai Nguyen } 932832c927dSTai Nguyen 933832c927dSTai Nguyen return 0; 934832c927dSTai Nguyen } 935832c927dSTai Nguyen 936832c927dSTai Nguyen static int fdt_pmu_probe_active_mcb_mcu(struct xgene_pmu *xgene_pmu, 937832c927dSTai Nguyen struct platform_device *pdev) 938832c927dSTai Nguyen { 939832c927dSTai Nguyen struct regmap *csw_map, *mcba_map, *mcbb_map; 940832c927dSTai Nguyen struct device_node *np = pdev->dev.of_node; 941832c927dSTai Nguyen unsigned int reg; 942832c927dSTai Nguyen 943832c927dSTai Nguyen csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw"); 944832c927dSTai Nguyen if (IS_ERR(csw_map)) { 945832c927dSTai Nguyen dev_err(&pdev->dev, "unable to get syscon regmap csw\n"); 946832c927dSTai Nguyen return PTR_ERR(csw_map); 947832c927dSTai Nguyen } 948832c927dSTai Nguyen 949832c927dSTai Nguyen mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba"); 950832c927dSTai Nguyen if (IS_ERR(mcba_map)) { 951832c927dSTai Nguyen dev_err(&pdev->dev, "unable to get syscon regmap mcba\n"); 952832c927dSTai Nguyen return PTR_ERR(mcba_map); 953832c927dSTai Nguyen } 954832c927dSTai Nguyen 955832c927dSTai Nguyen mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb"); 956832c927dSTai Nguyen if (IS_ERR(mcbb_map)) { 957832c927dSTai Nguyen dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n"); 958832c927dSTai Nguyen return PTR_ERR(mcbb_map); 959832c927dSTai Nguyen } 960832c927dSTai Nguyen 961832c927dSTai Nguyen if (regmap_read(csw_map, CSW_CSWCR, ®)) 962832c927dSTai Nguyen return -EINVAL; 963832c927dSTai Nguyen 964832c927dSTai Nguyen if (reg & CSW_CSWCR_DUALMCB_MASK) { 965832c927dSTai Nguyen /* Dual MCB active */ 966832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x3; 967832c927dSTai Nguyen /* Probe all active MC(s) */ 968832c927dSTai Nguyen if (regmap_read(mcbb_map, MCBADDRMR, ®)) 969832c927dSTai Nguyen return 0; 970832c927dSTai Nguyen xgene_pmu->mc_active_mask = 971832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; 972832c927dSTai Nguyen } else { 973832c927dSTai Nguyen /* Single MCB active */ 974832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x1; 975832c927dSTai Nguyen /* Probe all active MC(s) */ 976832c927dSTai Nguyen if (regmap_read(mcba_map, MCBADDRMR, ®)) 977832c927dSTai Nguyen return 0; 978832c927dSTai Nguyen xgene_pmu->mc_active_mask = 979832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; 980832c927dSTai Nguyen } 981832c927dSTai Nguyen 982832c927dSTai Nguyen return 0; 983832c927dSTai Nguyen } 984832c927dSTai Nguyen 985832c927dSTai Nguyen static int xgene_pmu_probe_active_mcb_mcu(struct xgene_pmu *xgene_pmu, 986832c927dSTai Nguyen struct platform_device *pdev) 987832c927dSTai Nguyen { 988832c927dSTai Nguyen if (has_acpi_companion(&pdev->dev)) 989832c927dSTai Nguyen return acpi_pmu_probe_active_mcb_mcu(xgene_pmu, pdev); 990832c927dSTai Nguyen return fdt_pmu_probe_active_mcb_mcu(xgene_pmu, pdev); 991832c927dSTai Nguyen } 992832c927dSTai Nguyen 993832c927dSTai Nguyen static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id) 994832c927dSTai Nguyen { 995832c927dSTai Nguyen switch (type) { 996832c927dSTai Nguyen case PMU_TYPE_L3C: 997832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id); 998832c927dSTai Nguyen case PMU_TYPE_IOB: 999832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id); 1000832c927dSTai Nguyen case PMU_TYPE_MCB: 1001832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id); 1002832c927dSTai Nguyen case PMU_TYPE_MC: 1003832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id); 1004832c927dSTai Nguyen default: 1005832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "unknown"); 1006832c927dSTai Nguyen } 1007832c927dSTai Nguyen } 1008832c927dSTai Nguyen 1009832c927dSTai Nguyen #if defined(CONFIG_ACPI) 1010832c927dSTai Nguyen static int acpi_pmu_dev_add_resource(struct acpi_resource *ares, void *data) 1011832c927dSTai Nguyen { 1012832c927dSTai Nguyen struct resource *res = data; 1013832c927dSTai Nguyen 1014832c927dSTai Nguyen if (ares->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) 1015832c927dSTai Nguyen acpi_dev_resource_memory(ares, res); 1016832c927dSTai Nguyen 1017832c927dSTai Nguyen /* Always tell the ACPI core to skip this resource */ 1018832c927dSTai Nguyen return 1; 1019832c927dSTai Nguyen } 1020832c927dSTai Nguyen 1021832c927dSTai Nguyen static struct 1022832c927dSTai Nguyen xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu, 1023832c927dSTai Nguyen struct acpi_device *adev, u32 type) 1024832c927dSTai Nguyen { 1025832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1026832c927dSTai Nguyen struct list_head resource_list; 1027832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1028832c927dSTai Nguyen const union acpi_object *obj; 1029832c927dSTai Nguyen struct hw_pmu_info *inf; 1030832c927dSTai Nguyen void __iomem *dev_csr; 1031832c927dSTai Nguyen struct resource res; 1032832c927dSTai Nguyen int enable_bit; 1033832c927dSTai Nguyen int rc; 1034832c927dSTai Nguyen 1035832c927dSTai Nguyen ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1036832c927dSTai Nguyen if (!ctx) 1037832c927dSTai Nguyen return NULL; 1038832c927dSTai Nguyen 1039832c927dSTai Nguyen INIT_LIST_HEAD(&resource_list); 1040832c927dSTai Nguyen rc = acpi_dev_get_resources(adev, &resource_list, 1041832c927dSTai Nguyen acpi_pmu_dev_add_resource, &res); 1042832c927dSTai Nguyen acpi_dev_free_resource_list(&resource_list); 10439a1a1f40STai Nguyen if (rc < 0) { 1044832c927dSTai Nguyen dev_err(dev, "PMU type %d: No resource address found\n", type); 1045832c927dSTai Nguyen goto err; 1046832c927dSTai Nguyen } 1047832c927dSTai Nguyen 1048832c927dSTai Nguyen dev_csr = devm_ioremap_resource(dev, &res); 1049832c927dSTai Nguyen if (IS_ERR(dev_csr)) { 1050832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to map resource\n", type); 1051832c927dSTai Nguyen goto err; 1052832c927dSTai Nguyen } 1053832c927dSTai Nguyen 1054832c927dSTai Nguyen /* A PMU device node without enable-bit-index is always enabled */ 1055832c927dSTai Nguyen rc = acpi_dev_get_property(adev, "enable-bit-index", 1056832c927dSTai Nguyen ACPI_TYPE_INTEGER, &obj); 1057832c927dSTai Nguyen if (rc < 0) 1058832c927dSTai Nguyen enable_bit = 0; 1059832c927dSTai Nguyen else 1060832c927dSTai Nguyen enable_bit = (int) obj->integer.value; 1061832c927dSTai Nguyen 1062832c927dSTai Nguyen ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); 1063832c927dSTai Nguyen if (!ctx->name) { 1064832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to get device name\n", type); 1065832c927dSTai Nguyen goto err; 1066832c927dSTai Nguyen } 1067832c927dSTai Nguyen inf = &ctx->inf; 1068832c927dSTai Nguyen inf->type = type; 1069832c927dSTai Nguyen inf->csr = dev_csr; 1070832c927dSTai Nguyen inf->enable_mask = 1 << enable_bit; 1071832c927dSTai Nguyen 1072832c927dSTai Nguyen return ctx; 1073832c927dSTai Nguyen err: 1074832c927dSTai Nguyen devm_kfree(dev, ctx); 1075832c927dSTai Nguyen return NULL; 1076832c927dSTai Nguyen } 1077832c927dSTai Nguyen 1078838955e2SHoan Tran static const struct acpi_device_id xgene_pmu_acpi_type_match[] = { 1079838955e2SHoan Tran {"APMC0D5D", PMU_TYPE_L3C}, 1080838955e2SHoan Tran {"APMC0D5E", PMU_TYPE_IOB}, 1081838955e2SHoan Tran {"APMC0D5F", PMU_TYPE_MCB}, 1082838955e2SHoan Tran {"APMC0D60", PMU_TYPE_MC}, 1083838955e2SHoan Tran {}, 1084838955e2SHoan Tran }; 1085838955e2SHoan Tran 1086838955e2SHoan Tran static const struct acpi_device_id *xgene_pmu_acpi_match_type( 1087838955e2SHoan Tran const struct acpi_device_id *ids, 1088838955e2SHoan Tran struct acpi_device *adev) 1089838955e2SHoan Tran { 1090838955e2SHoan Tran const struct acpi_device_id *match_id = NULL; 1091838955e2SHoan Tran const struct acpi_device_id *id; 1092838955e2SHoan Tran 1093838955e2SHoan Tran for (id = ids; id->id[0] || id->cls; id++) { 1094838955e2SHoan Tran if (!acpi_match_device_ids(adev, id)) 1095838955e2SHoan Tran match_id = id; 1096838955e2SHoan Tran else if (match_id) 1097838955e2SHoan Tran break; 1098838955e2SHoan Tran } 1099838955e2SHoan Tran 1100838955e2SHoan Tran return match_id; 1101838955e2SHoan Tran } 1102838955e2SHoan Tran 1103832c927dSTai Nguyen static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level, 1104832c927dSTai Nguyen void *data, void **return_value) 1105832c927dSTai Nguyen { 1106838955e2SHoan Tran const struct acpi_device_id *acpi_id; 1107832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = data; 1108832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1109832c927dSTai Nguyen struct acpi_device *adev; 1110832c927dSTai Nguyen 1111832c927dSTai Nguyen if (acpi_bus_get_device(handle, &adev)) 1112832c927dSTai Nguyen return AE_OK; 1113832c927dSTai Nguyen if (acpi_bus_get_status(adev) || !adev->status.present) 1114832c927dSTai Nguyen return AE_OK; 1115832c927dSTai Nguyen 1116838955e2SHoan Tran acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev); 1117838955e2SHoan Tran if (!acpi_id) 1118838955e2SHoan Tran return AE_OK; 1119832c927dSTai Nguyen 1120838955e2SHoan Tran ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data); 1121832c927dSTai Nguyen if (!ctx) 1122832c927dSTai Nguyen return AE_OK; 1123832c927dSTai Nguyen 1124832c927dSTai Nguyen if (xgene_pmu_dev_add(xgene_pmu, ctx)) { 1125832c927dSTai Nguyen /* Can't add the PMU device, skip it */ 1126832c927dSTai Nguyen devm_kfree(xgene_pmu->dev, ctx); 1127832c927dSTai Nguyen return AE_OK; 1128832c927dSTai Nguyen } 1129832c927dSTai Nguyen 1130832c927dSTai Nguyen switch (ctx->inf.type) { 1131832c927dSTai Nguyen case PMU_TYPE_L3C: 1132832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->l3cpmus); 1133832c927dSTai Nguyen break; 1134832c927dSTai Nguyen case PMU_TYPE_IOB: 1135832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->iobpmus); 1136832c927dSTai Nguyen break; 1137832c927dSTai Nguyen case PMU_TYPE_MCB: 1138832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcbpmus); 1139832c927dSTai Nguyen break; 1140832c927dSTai Nguyen case PMU_TYPE_MC: 1141832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcpmus); 1142832c927dSTai Nguyen break; 1143832c927dSTai Nguyen } 1144832c927dSTai Nguyen return AE_OK; 1145832c927dSTai Nguyen } 1146832c927dSTai Nguyen 1147832c927dSTai Nguyen static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1148832c927dSTai Nguyen struct platform_device *pdev) 1149832c927dSTai Nguyen { 1150832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1151832c927dSTai Nguyen acpi_handle handle; 1152832c927dSTai Nguyen acpi_status status; 1153832c927dSTai Nguyen 1154832c927dSTai Nguyen handle = ACPI_HANDLE(dev); 1155832c927dSTai Nguyen if (!handle) 1156832c927dSTai Nguyen return -EINVAL; 1157832c927dSTai Nguyen 1158832c927dSTai Nguyen status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1, 1159832c927dSTai Nguyen acpi_pmu_dev_add, NULL, xgene_pmu, NULL); 1160832c927dSTai Nguyen if (ACPI_FAILURE(status)) { 1161832c927dSTai Nguyen dev_err(dev, "failed to probe PMU devices\n"); 1162832c927dSTai Nguyen return -ENODEV; 1163832c927dSTai Nguyen } 1164832c927dSTai Nguyen 1165832c927dSTai Nguyen return 0; 1166832c927dSTai Nguyen } 1167832c927dSTai Nguyen #else 1168832c927dSTai Nguyen static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1169832c927dSTai Nguyen struct platform_device *pdev) 1170832c927dSTai Nguyen { 1171832c927dSTai Nguyen return 0; 1172832c927dSTai Nguyen } 1173832c927dSTai Nguyen #endif 1174832c927dSTai Nguyen 1175832c927dSTai Nguyen static struct 1176832c927dSTai Nguyen xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu, 1177832c927dSTai Nguyen struct device_node *np, u32 type) 1178832c927dSTai Nguyen { 1179832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1180832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1181832c927dSTai Nguyen struct hw_pmu_info *inf; 1182832c927dSTai Nguyen void __iomem *dev_csr; 1183832c927dSTai Nguyen struct resource res; 1184832c927dSTai Nguyen int enable_bit; 1185832c927dSTai Nguyen int rc; 1186832c927dSTai Nguyen 1187832c927dSTai Nguyen ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1188832c927dSTai Nguyen if (!ctx) 1189832c927dSTai Nguyen return NULL; 1190832c927dSTai Nguyen rc = of_address_to_resource(np, 0, &res); 1191832c927dSTai Nguyen if (rc < 0) { 1192832c927dSTai Nguyen dev_err(dev, "PMU type %d: No resource address found\n", type); 1193832c927dSTai Nguyen goto err; 1194832c927dSTai Nguyen } 1195832c927dSTai Nguyen dev_csr = devm_ioremap_resource(dev, &res); 1196832c927dSTai Nguyen if (IS_ERR(dev_csr)) { 1197832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to map resource\n", type); 1198832c927dSTai Nguyen goto err; 1199832c927dSTai Nguyen } 1200832c927dSTai Nguyen 1201832c927dSTai Nguyen /* A PMU device node without enable-bit-index is always enabled */ 1202832c927dSTai Nguyen if (of_property_read_u32(np, "enable-bit-index", &enable_bit)) 1203832c927dSTai Nguyen enable_bit = 0; 1204832c927dSTai Nguyen 1205832c927dSTai Nguyen ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); 1206832c927dSTai Nguyen if (!ctx->name) { 1207832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to get device name\n", type); 1208832c927dSTai Nguyen goto err; 1209832c927dSTai Nguyen } 1210832c927dSTai Nguyen inf = &ctx->inf; 1211832c927dSTai Nguyen inf->type = type; 1212832c927dSTai Nguyen inf->csr = dev_csr; 1213832c927dSTai Nguyen inf->enable_mask = 1 << enable_bit; 1214832c927dSTai Nguyen 1215832c927dSTai Nguyen return ctx; 1216832c927dSTai Nguyen err: 1217832c927dSTai Nguyen devm_kfree(dev, ctx); 1218832c927dSTai Nguyen return NULL; 1219832c927dSTai Nguyen } 1220832c927dSTai Nguyen 1221832c927dSTai Nguyen static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1222832c927dSTai Nguyen struct platform_device *pdev) 1223832c927dSTai Nguyen { 1224832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1225832c927dSTai Nguyen struct device_node *np; 1226832c927dSTai Nguyen 1227832c927dSTai Nguyen for_each_child_of_node(pdev->dev.of_node, np) { 1228832c927dSTai Nguyen if (!of_device_is_available(np)) 1229832c927dSTai Nguyen continue; 1230832c927dSTai Nguyen 1231832c927dSTai Nguyen if (of_device_is_compatible(np, "apm,xgene-pmu-l3c")) 1232832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C); 1233832c927dSTai Nguyen else if (of_device_is_compatible(np, "apm,xgene-pmu-iob")) 1234832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB); 1235832c927dSTai Nguyen else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb")) 1236832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB); 1237832c927dSTai Nguyen else if (of_device_is_compatible(np, "apm,xgene-pmu-mc")) 1238832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC); 1239832c927dSTai Nguyen else 1240832c927dSTai Nguyen ctx = NULL; 1241832c927dSTai Nguyen 1242832c927dSTai Nguyen if (!ctx) 1243832c927dSTai Nguyen continue; 1244832c927dSTai Nguyen 1245832c927dSTai Nguyen if (xgene_pmu_dev_add(xgene_pmu, ctx)) { 1246832c927dSTai Nguyen /* Can't add the PMU device, skip it */ 1247832c927dSTai Nguyen devm_kfree(xgene_pmu->dev, ctx); 1248832c927dSTai Nguyen continue; 1249832c927dSTai Nguyen } 1250832c927dSTai Nguyen 1251832c927dSTai Nguyen switch (ctx->inf.type) { 1252832c927dSTai Nguyen case PMU_TYPE_L3C: 1253832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->l3cpmus); 1254832c927dSTai Nguyen break; 1255832c927dSTai Nguyen case PMU_TYPE_IOB: 1256832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->iobpmus); 1257832c927dSTai Nguyen break; 1258832c927dSTai Nguyen case PMU_TYPE_MCB: 1259832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcbpmus); 1260832c927dSTai Nguyen break; 1261832c927dSTai Nguyen case PMU_TYPE_MC: 1262832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcpmus); 1263832c927dSTai Nguyen break; 1264832c927dSTai Nguyen } 1265832c927dSTai Nguyen } 1266832c927dSTai Nguyen 1267832c927dSTai Nguyen return 0; 1268832c927dSTai Nguyen } 1269832c927dSTai Nguyen 1270832c927dSTai Nguyen static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1271832c927dSTai Nguyen struct platform_device *pdev) 1272832c927dSTai Nguyen { 1273832c927dSTai Nguyen if (has_acpi_companion(&pdev->dev)) 1274832c927dSTai Nguyen return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev); 1275832c927dSTai Nguyen return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev); 1276832c927dSTai Nguyen } 1277832c927dSTai Nguyen 1278832c927dSTai Nguyen static const struct xgene_pmu_data xgene_pmu_data = { 1279832c927dSTai Nguyen .id = PCP_PMU_V1, 1280832c927dSTai Nguyen }; 1281832c927dSTai Nguyen 1282832c927dSTai Nguyen static const struct xgene_pmu_data xgene_pmu_v2_data = { 1283832c927dSTai Nguyen .id = PCP_PMU_V2, 1284832c927dSTai Nguyen }; 1285832c927dSTai Nguyen 1286e35e0a04SHoan Tran static const struct xgene_pmu_ops xgene_pmu_ops = { 1287e35e0a04SHoan Tran .mask_int = xgene_pmu_mask_int, 1288e35e0a04SHoan Tran .unmask_int = xgene_pmu_unmask_int, 1289e35e0a04SHoan Tran .read_counter = xgene_pmu_read_counter32, 1290e35e0a04SHoan Tran .write_counter = xgene_pmu_write_counter32, 1291e35e0a04SHoan Tran .write_evttype = xgene_pmu_write_evttype, 1292e35e0a04SHoan Tran .write_agentmsk = xgene_pmu_write_agentmsk, 1293e35e0a04SHoan Tran .write_agent1msk = xgene_pmu_write_agent1msk, 1294e35e0a04SHoan Tran .enable_counter = xgene_pmu_enable_counter, 1295e35e0a04SHoan Tran .disable_counter = xgene_pmu_disable_counter, 1296e35e0a04SHoan Tran .enable_counter_int = xgene_pmu_enable_counter_int, 1297e35e0a04SHoan Tran .disable_counter_int = xgene_pmu_disable_counter_int, 1298e35e0a04SHoan Tran .reset_counters = xgene_pmu_reset_counters, 1299e35e0a04SHoan Tran .start_counters = xgene_pmu_start_counters, 1300e35e0a04SHoan Tran .stop_counters = xgene_pmu_stop_counters, 1301e35e0a04SHoan Tran }; 1302e35e0a04SHoan Tran 1303832c927dSTai Nguyen static const struct of_device_id xgene_pmu_of_match[] = { 1304832c927dSTai Nguyen { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data }, 1305832c927dSTai Nguyen { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data }, 1306832c927dSTai Nguyen {}, 1307832c927dSTai Nguyen }; 1308832c927dSTai Nguyen MODULE_DEVICE_TABLE(of, xgene_pmu_of_match); 1309832c927dSTai Nguyen #ifdef CONFIG_ACPI 1310832c927dSTai Nguyen static const struct acpi_device_id xgene_pmu_acpi_match[] = { 1311832c927dSTai Nguyen {"APMC0D5B", PCP_PMU_V1}, 1312832c927dSTai Nguyen {"APMC0D5C", PCP_PMU_V2}, 1313832c927dSTai Nguyen {}, 1314832c927dSTai Nguyen }; 1315832c927dSTai Nguyen MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match); 1316832c927dSTai Nguyen #endif 1317832c927dSTai Nguyen 1318832c927dSTai Nguyen static int xgene_pmu_probe(struct platform_device *pdev) 1319832c927dSTai Nguyen { 1320832c927dSTai Nguyen const struct xgene_pmu_data *dev_data; 1321832c927dSTai Nguyen const struct of_device_id *of_id; 1322832c927dSTai Nguyen struct xgene_pmu *xgene_pmu; 1323832c927dSTai Nguyen struct resource *res; 1324832c927dSTai Nguyen int irq, rc; 1325832c927dSTai Nguyen int version; 1326832c927dSTai Nguyen 1327832c927dSTai Nguyen xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL); 1328832c927dSTai Nguyen if (!xgene_pmu) 1329832c927dSTai Nguyen return -ENOMEM; 1330832c927dSTai Nguyen xgene_pmu->dev = &pdev->dev; 1331832c927dSTai Nguyen platform_set_drvdata(pdev, xgene_pmu); 1332832c927dSTai Nguyen 1333832c927dSTai Nguyen version = -EINVAL; 1334832c927dSTai Nguyen of_id = of_match_device(xgene_pmu_of_match, &pdev->dev); 1335832c927dSTai Nguyen if (of_id) { 1336832c927dSTai Nguyen dev_data = (const struct xgene_pmu_data *) of_id->data; 1337832c927dSTai Nguyen version = dev_data->id; 1338832c927dSTai Nguyen } 1339832c927dSTai Nguyen 1340832c927dSTai Nguyen #ifdef CONFIG_ACPI 1341832c927dSTai Nguyen if (ACPI_COMPANION(&pdev->dev)) { 1342832c927dSTai Nguyen const struct acpi_device_id *acpi_id; 1343832c927dSTai Nguyen 1344832c927dSTai Nguyen acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev); 1345832c927dSTai Nguyen if (acpi_id) 1346832c927dSTai Nguyen version = (int) acpi_id->driver_data; 1347832c927dSTai Nguyen } 1348832c927dSTai Nguyen #endif 1349832c927dSTai Nguyen if (version < 0) 1350832c927dSTai Nguyen return -ENODEV; 1351832c927dSTai Nguyen 1352e35e0a04SHoan Tran xgene_pmu->ops = &xgene_pmu_ops; 1353e35e0a04SHoan Tran 1354832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->l3cpmus); 1355832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->iobpmus); 1356832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->mcbpmus); 1357832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->mcpmus); 1358832c927dSTai Nguyen 1359832c927dSTai Nguyen xgene_pmu->version = version; 1360832c927dSTai Nguyen dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version); 1361832c927dSTai Nguyen 1362832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1363832c927dSTai Nguyen xgene_pmu->pcppmu_csr = devm_ioremap_resource(&pdev->dev, res); 1364832c927dSTai Nguyen if (IS_ERR(xgene_pmu->pcppmu_csr)) { 1365832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n"); 1366832c927dSTai Nguyen rc = PTR_ERR(xgene_pmu->pcppmu_csr); 1367832c927dSTai Nguyen goto err; 1368832c927dSTai Nguyen } 1369832c927dSTai Nguyen 1370832c927dSTai Nguyen irq = platform_get_irq(pdev, 0); 1371832c927dSTai Nguyen if (irq < 0) { 1372832c927dSTai Nguyen dev_err(&pdev->dev, "No IRQ resource\n"); 1373832c927dSTai Nguyen rc = -EINVAL; 1374832c927dSTai Nguyen goto err; 1375832c927dSTai Nguyen } 1376832c927dSTai Nguyen rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr, 1377832c927dSTai Nguyen IRQF_NOBALANCING | IRQF_NO_THREAD, 1378832c927dSTai Nguyen dev_name(&pdev->dev), xgene_pmu); 1379832c927dSTai Nguyen if (rc) { 1380832c927dSTai Nguyen dev_err(&pdev->dev, "Could not request IRQ %d\n", irq); 1381832c927dSTai Nguyen goto err; 1382832c927dSTai Nguyen } 1383832c927dSTai Nguyen 1384832c927dSTai Nguyen raw_spin_lock_init(&xgene_pmu->lock); 1385832c927dSTai Nguyen 1386832c927dSTai Nguyen /* Check for active MCBs and MCUs */ 1387832c927dSTai Nguyen rc = xgene_pmu_probe_active_mcb_mcu(xgene_pmu, pdev); 1388832c927dSTai Nguyen if (rc) { 1389832c927dSTai Nguyen dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n"); 1390832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x1; 1391832c927dSTai Nguyen xgene_pmu->mc_active_mask = 0x1; 1392832c927dSTai Nguyen } 1393832c927dSTai Nguyen 1394832c927dSTai Nguyen /* Pick one core to use for cpumask attributes */ 1395832c927dSTai Nguyen cpumask_set_cpu(smp_processor_id(), &xgene_pmu->cpu); 1396832c927dSTai Nguyen 1397832c927dSTai Nguyen /* Make sure that the overflow interrupt is handled by this CPU */ 1398832c927dSTai Nguyen rc = irq_set_affinity(irq, &xgene_pmu->cpu); 1399832c927dSTai Nguyen if (rc) { 1400832c927dSTai Nguyen dev_err(&pdev->dev, "Failed to set interrupt affinity!\n"); 1401832c927dSTai Nguyen goto err; 1402832c927dSTai Nguyen } 1403832c927dSTai Nguyen 1404832c927dSTai Nguyen /* Walk through the tree for all PMU perf devices */ 1405832c927dSTai Nguyen rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev); 1406832c927dSTai Nguyen if (rc) { 1407832c927dSTai Nguyen dev_err(&pdev->dev, "No PMU perf devices found!\n"); 1408832c927dSTai Nguyen goto err; 1409832c927dSTai Nguyen } 1410832c927dSTai Nguyen 1411832c927dSTai Nguyen /* Enable interrupt */ 1412e35e0a04SHoan Tran xgene_pmu->ops->unmask_int(xgene_pmu); 1413832c927dSTai Nguyen 1414832c927dSTai Nguyen return 0; 1415832c927dSTai Nguyen 1416832c927dSTai Nguyen err: 1417832c927dSTai Nguyen if (xgene_pmu->pcppmu_csr) 1418832c927dSTai Nguyen devm_iounmap(&pdev->dev, xgene_pmu->pcppmu_csr); 1419832c927dSTai Nguyen devm_kfree(&pdev->dev, xgene_pmu); 1420832c927dSTai Nguyen 1421832c927dSTai Nguyen return rc; 1422832c927dSTai Nguyen } 1423832c927dSTai Nguyen 1424832c927dSTai Nguyen static void 1425832c927dSTai Nguyen xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus) 1426832c927dSTai Nguyen { 1427832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1428832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1429832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev; 1430832c927dSTai Nguyen 1431832c927dSTai Nguyen list_for_each_entry(ctx, pmus, next) { 1432832c927dSTai Nguyen pmu_dev = ctx->pmu_dev; 1433832c927dSTai Nguyen if (pmu_dev->inf->csr) 1434832c927dSTai Nguyen devm_iounmap(dev, pmu_dev->inf->csr); 1435832c927dSTai Nguyen devm_kfree(dev, ctx); 1436832c927dSTai Nguyen devm_kfree(dev, pmu_dev); 1437832c927dSTai Nguyen } 1438832c927dSTai Nguyen } 1439832c927dSTai Nguyen 1440832c927dSTai Nguyen static int xgene_pmu_remove(struct platform_device *pdev) 1441832c927dSTai Nguyen { 1442832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev); 1443832c927dSTai Nguyen 1444832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus); 1445832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus); 1446832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus); 1447832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus); 1448832c927dSTai Nguyen 1449832c927dSTai Nguyen if (xgene_pmu->pcppmu_csr) 1450832c927dSTai Nguyen devm_iounmap(&pdev->dev, xgene_pmu->pcppmu_csr); 1451832c927dSTai Nguyen devm_kfree(&pdev->dev, xgene_pmu); 1452832c927dSTai Nguyen 1453832c927dSTai Nguyen return 0; 1454832c927dSTai Nguyen } 1455832c927dSTai Nguyen 1456832c927dSTai Nguyen static struct platform_driver xgene_pmu_driver = { 1457832c927dSTai Nguyen .probe = xgene_pmu_probe, 1458832c927dSTai Nguyen .remove = xgene_pmu_remove, 1459832c927dSTai Nguyen .driver = { 1460832c927dSTai Nguyen .name = "xgene-pmu", 1461832c927dSTai Nguyen .of_match_table = xgene_pmu_of_match, 1462832c927dSTai Nguyen .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match), 1463832c927dSTai Nguyen }, 1464832c927dSTai Nguyen }; 1465832c927dSTai Nguyen 1466832c927dSTai Nguyen builtin_platform_driver(xgene_pmu_driver); 1467