11ccea77eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2832c927dSTai Nguyen /* 3832c927dSTai Nguyen * APM X-Gene SoC PMU (Performance Monitor Unit) 4832c927dSTai Nguyen * 5832c927dSTai Nguyen * Copyright (c) 2016, Applied Micro Circuits Corporation 6832c927dSTai Nguyen * Author: Hoan Tran <hotran@apm.com> 7832c927dSTai Nguyen * Tai Nguyen <ttnguyen@apm.com> 8832c927dSTai Nguyen */ 9832c927dSTai Nguyen 10832c927dSTai Nguyen #include <linux/acpi.h> 11832c927dSTai Nguyen #include <linux/clk.h> 12cbb72a3cSHoan Tran #include <linux/cpuhotplug.h> 13832c927dSTai Nguyen #include <linux/cpumask.h> 14832c927dSTai Nguyen #include <linux/interrupt.h> 15832c927dSTai Nguyen #include <linux/io.h> 16832c927dSTai Nguyen #include <linux/mfd/syscon.h> 17c0bfc549SStephen Boyd #include <linux/module.h> 18832c927dSTai Nguyen #include <linux/of_address.h> 19832c927dSTai Nguyen #include <linux/of_fdt.h> 20832c927dSTai Nguyen #include <linux/of_irq.h> 21832c927dSTai Nguyen #include <linux/of_platform.h> 22832c927dSTai Nguyen #include <linux/perf_event.h> 23832c927dSTai Nguyen #include <linux/platform_device.h> 24832c927dSTai Nguyen #include <linux/regmap.h> 25832c927dSTai Nguyen #include <linux/slab.h> 26832c927dSTai Nguyen 27832c927dSTai Nguyen #define CSW_CSWCR 0x0000 28832c927dSTai Nguyen #define CSW_CSWCR_DUALMCB_MASK BIT(0) 29c0f7f7acSHoan Tran #define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0x0C) >> 2) 30c0f7f7acSHoan Tran #define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0x30) >> 4) 31832c927dSTai Nguyen #define MCBADDRMR 0x0000 32832c927dSTai Nguyen #define MCBADDRMR_DUALMCU_MODE_MASK BIT(2) 33832c927dSTai Nguyen 34832c927dSTai Nguyen #define PCPPMU_INTSTATUS_REG 0x000 35832c927dSTai Nguyen #define PCPPMU_INTMASK_REG 0x004 36832c927dSTai Nguyen #define PCPPMU_INTMASK 0x0000000F 37832c927dSTai Nguyen #define PCPPMU_INTENMASK 0xFFFFFFFF 38832c927dSTai Nguyen #define PCPPMU_INTCLRMASK 0xFFFFFFF0 39832c927dSTai Nguyen #define PCPPMU_INT_MCU BIT(0) 40832c927dSTai Nguyen #define PCPPMU_INT_MCB BIT(1) 41832c927dSTai Nguyen #define PCPPMU_INT_L3C BIT(2) 42832c927dSTai Nguyen #define PCPPMU_INT_IOB BIT(3) 43832c927dSTai Nguyen 44c0f7f7acSHoan Tran #define PCPPMU_V3_INTMASK 0x00FF33FF 45c0f7f7acSHoan Tran #define PCPPMU_V3_INTENMASK 0xFFFFFFFF 46c0f7f7acSHoan Tran #define PCPPMU_V3_INTCLRMASK 0xFF00CC00 47c0f7f7acSHoan Tran #define PCPPMU_V3_INT_MCU 0x000000FF 48c0f7f7acSHoan Tran #define PCPPMU_V3_INT_MCB 0x00000300 49c0f7f7acSHoan Tran #define PCPPMU_V3_INT_L3C 0x00FF0000 50c0f7f7acSHoan Tran #define PCPPMU_V3_INT_IOB 0x00003000 51c0f7f7acSHoan Tran 52832c927dSTai Nguyen #define PMU_MAX_COUNTERS 4 53c0f7f7acSHoan Tran #define PMU_CNT_MAX_PERIOD 0xFFFFFFFFULL 54c0f7f7acSHoan Tran #define PMU_V3_CNT_MAX_PERIOD 0xFFFFFFFFFFFFFFFFULL 55832c927dSTai Nguyen #define PMU_OVERFLOW_MASK 0xF 56832c927dSTai Nguyen #define PMU_PMCR_E BIT(0) 57832c927dSTai Nguyen #define PMU_PMCR_P BIT(1) 58832c927dSTai Nguyen 59832c927dSTai Nguyen #define PMU_PMEVCNTR0 0x000 60832c927dSTai Nguyen #define PMU_PMEVCNTR1 0x004 61832c927dSTai Nguyen #define PMU_PMEVCNTR2 0x008 62832c927dSTai Nguyen #define PMU_PMEVCNTR3 0x00C 63832c927dSTai Nguyen #define PMU_PMEVTYPER0 0x400 64832c927dSTai Nguyen #define PMU_PMEVTYPER1 0x404 65832c927dSTai Nguyen #define PMU_PMEVTYPER2 0x408 66832c927dSTai Nguyen #define PMU_PMEVTYPER3 0x40C 67832c927dSTai Nguyen #define PMU_PMAMR0 0xA00 68832c927dSTai Nguyen #define PMU_PMAMR1 0xA04 69832c927dSTai Nguyen #define PMU_PMCNTENSET 0xC00 70832c927dSTai Nguyen #define PMU_PMCNTENCLR 0xC20 71832c927dSTai Nguyen #define PMU_PMINTENSET 0xC40 72832c927dSTai Nguyen #define PMU_PMINTENCLR 0xC60 73832c927dSTai Nguyen #define PMU_PMOVSR 0xC80 74832c927dSTai Nguyen #define PMU_PMCR 0xE04 75832c927dSTai Nguyen 76c0f7f7acSHoan Tran /* PMU registers for V3 */ 77c0f7f7acSHoan Tran #define PMU_PMOVSCLR 0xC80 78c0f7f7acSHoan Tran #define PMU_PMOVSSET 0xCC0 79c0f7f7acSHoan Tran 80832c927dSTai Nguyen #define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu) 81832c927dSTai Nguyen #define GET_CNTR(ev) (ev->hw.idx) 82832c927dSTai Nguyen #define GET_EVENTID(ev) (ev->hw.config & 0xFFULL) 83832c927dSTai Nguyen #define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL) 84832c927dSTai Nguyen #define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL) 85832c927dSTai Nguyen 86832c927dSTai Nguyen struct hw_pmu_info { 87832c927dSTai Nguyen u32 type; 88832c927dSTai Nguyen u32 enable_mask; 89832c927dSTai Nguyen void __iomem *csr; 90832c927dSTai Nguyen }; 91832c927dSTai Nguyen 92832c927dSTai Nguyen struct xgene_pmu_dev { 93832c927dSTai Nguyen struct hw_pmu_info *inf; 94832c927dSTai Nguyen struct xgene_pmu *parent; 95832c927dSTai Nguyen struct pmu pmu; 96832c927dSTai Nguyen u8 max_counters; 97832c927dSTai Nguyen DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS); 98832c927dSTai Nguyen u64 max_period; 99832c927dSTai Nguyen const struct attribute_group **attr_groups; 100832c927dSTai Nguyen struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS]; 101832c927dSTai Nguyen }; 102832c927dSTai Nguyen 103e35e0a04SHoan Tran struct xgene_pmu_ops { 104e35e0a04SHoan Tran void (*mask_int)(struct xgene_pmu *pmu); 105e35e0a04SHoan Tran void (*unmask_int)(struct xgene_pmu *pmu); 106e35e0a04SHoan Tran u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx); 107e35e0a04SHoan Tran void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val); 108e35e0a04SHoan Tran void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val); 109e35e0a04SHoan Tran void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val); 110e35e0a04SHoan Tran void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val); 111e35e0a04SHoan Tran void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx); 112e35e0a04SHoan Tran void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx); 113e35e0a04SHoan Tran void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx); 114e35e0a04SHoan Tran void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx); 115e35e0a04SHoan Tran void (*reset_counters)(struct xgene_pmu_dev *pmu_dev); 116e35e0a04SHoan Tran void (*start_counters)(struct xgene_pmu_dev *pmu_dev); 117e35e0a04SHoan Tran void (*stop_counters)(struct xgene_pmu_dev *pmu_dev); 118e35e0a04SHoan Tran }; 119e35e0a04SHoan Tran 120832c927dSTai Nguyen struct xgene_pmu { 121832c927dSTai Nguyen struct device *dev; 122cbb72a3cSHoan Tran struct hlist_node node; 123832c927dSTai Nguyen int version; 124832c927dSTai Nguyen void __iomem *pcppmu_csr; 125832c927dSTai Nguyen u32 mcb_active_mask; 126832c927dSTai Nguyen u32 mc_active_mask; 127c0f7f7acSHoan Tran u32 l3c_active_mask; 128832c927dSTai Nguyen cpumask_t cpu; 129cbb72a3cSHoan Tran int irq; 130832c927dSTai Nguyen raw_spinlock_t lock; 131e35e0a04SHoan Tran const struct xgene_pmu_ops *ops; 132832c927dSTai Nguyen struct list_head l3cpmus; 133832c927dSTai Nguyen struct list_head iobpmus; 134832c927dSTai Nguyen struct list_head mcbpmus; 135832c927dSTai Nguyen struct list_head mcpmus; 136832c927dSTai Nguyen }; 137832c927dSTai Nguyen 138832c927dSTai Nguyen struct xgene_pmu_dev_ctx { 139832c927dSTai Nguyen char *name; 140832c927dSTai Nguyen struct list_head next; 141832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev; 142832c927dSTai Nguyen struct hw_pmu_info inf; 143832c927dSTai Nguyen }; 144832c927dSTai Nguyen 145832c927dSTai Nguyen struct xgene_pmu_data { 146832c927dSTai Nguyen int id; 147832c927dSTai Nguyen u32 data; 148832c927dSTai Nguyen }; 149832c927dSTai Nguyen 150832c927dSTai Nguyen enum xgene_pmu_version { 151832c927dSTai Nguyen PCP_PMU_V1 = 1, 152832c927dSTai Nguyen PCP_PMU_V2, 153c0f7f7acSHoan Tran PCP_PMU_V3, 154832c927dSTai Nguyen }; 155832c927dSTai Nguyen 156832c927dSTai Nguyen enum xgene_pmu_dev_type { 157832c927dSTai Nguyen PMU_TYPE_L3C = 0, 158832c927dSTai Nguyen PMU_TYPE_IOB, 159c0f7f7acSHoan Tran PMU_TYPE_IOB_SLOW, 160832c927dSTai Nguyen PMU_TYPE_MCB, 161832c927dSTai Nguyen PMU_TYPE_MC, 162832c927dSTai Nguyen }; 163832c927dSTai Nguyen 164832c927dSTai Nguyen /* 165832c927dSTai Nguyen * sysfs format attributes 166832c927dSTai Nguyen */ 167832c927dSTai Nguyen static ssize_t xgene_pmu_format_show(struct device *dev, 168832c927dSTai Nguyen struct device_attribute *attr, char *buf) 169832c927dSTai Nguyen { 170832c927dSTai Nguyen struct dev_ext_attribute *eattr; 171832c927dSTai Nguyen 172832c927dSTai Nguyen eattr = container_of(attr, struct dev_ext_attribute, attr); 173832c927dSTai Nguyen return sprintf(buf, "%s\n", (char *) eattr->var); 174832c927dSTai Nguyen } 175832c927dSTai Nguyen 176832c927dSTai Nguyen #define XGENE_PMU_FORMAT_ATTR(_name, _config) \ 177832c927dSTai Nguyen (&((struct dev_ext_attribute[]) { \ 178832c927dSTai Nguyen { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \ 179832c927dSTai Nguyen .var = (void *) _config, } \ 180832c927dSTai Nguyen })[0].attr.attr) 181832c927dSTai Nguyen 182832c927dSTai Nguyen static struct attribute *l3c_pmu_format_attrs[] = { 183832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"), 184832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"), 185832c927dSTai Nguyen NULL, 186832c927dSTai Nguyen }; 187832c927dSTai Nguyen 188832c927dSTai Nguyen static struct attribute *iob_pmu_format_attrs[] = { 189832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"), 190832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"), 191832c927dSTai Nguyen NULL, 192832c927dSTai Nguyen }; 193832c927dSTai Nguyen 194832c927dSTai Nguyen static struct attribute *mcb_pmu_format_attrs[] = { 195832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"), 196832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"), 197832c927dSTai Nguyen NULL, 198832c927dSTai Nguyen }; 199832c927dSTai Nguyen 200832c927dSTai Nguyen static struct attribute *mc_pmu_format_attrs[] = { 201832c927dSTai Nguyen XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"), 202832c927dSTai Nguyen NULL, 203832c927dSTai Nguyen }; 204832c927dSTai Nguyen 205832c927dSTai Nguyen static const struct attribute_group l3c_pmu_format_attr_group = { 206832c927dSTai Nguyen .name = "format", 207832c927dSTai Nguyen .attrs = l3c_pmu_format_attrs, 208832c927dSTai Nguyen }; 209832c927dSTai Nguyen 210832c927dSTai Nguyen static const struct attribute_group iob_pmu_format_attr_group = { 211832c927dSTai Nguyen .name = "format", 212832c927dSTai Nguyen .attrs = iob_pmu_format_attrs, 213832c927dSTai Nguyen }; 214832c927dSTai Nguyen 215832c927dSTai Nguyen static const struct attribute_group mcb_pmu_format_attr_group = { 216832c927dSTai Nguyen .name = "format", 217832c927dSTai Nguyen .attrs = mcb_pmu_format_attrs, 218832c927dSTai Nguyen }; 219832c927dSTai Nguyen 220832c927dSTai Nguyen static const struct attribute_group mc_pmu_format_attr_group = { 221832c927dSTai Nguyen .name = "format", 222832c927dSTai Nguyen .attrs = mc_pmu_format_attrs, 223832c927dSTai Nguyen }; 224832c927dSTai Nguyen 225c0f7f7acSHoan Tran static struct attribute *l3c_pmu_v3_format_attrs[] = { 226c0f7f7acSHoan Tran XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"), 227c0f7f7acSHoan Tran NULL, 228c0f7f7acSHoan Tran }; 229c0f7f7acSHoan Tran 230c0f7f7acSHoan Tran static struct attribute *iob_pmu_v3_format_attrs[] = { 231c0f7f7acSHoan Tran XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"), 232c0f7f7acSHoan Tran NULL, 233c0f7f7acSHoan Tran }; 234c0f7f7acSHoan Tran 235c0f7f7acSHoan Tran static struct attribute *iob_slow_pmu_v3_format_attrs[] = { 236c0f7f7acSHoan Tran XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"), 237c0f7f7acSHoan Tran NULL, 238c0f7f7acSHoan Tran }; 239c0f7f7acSHoan Tran 240c0f7f7acSHoan Tran static struct attribute *mcb_pmu_v3_format_attrs[] = { 241c0f7f7acSHoan Tran XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"), 242c0f7f7acSHoan Tran NULL, 243c0f7f7acSHoan Tran }; 244c0f7f7acSHoan Tran 245c0f7f7acSHoan Tran static struct attribute *mc_pmu_v3_format_attrs[] = { 246c0f7f7acSHoan Tran XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"), 247c0f7f7acSHoan Tran NULL, 248c0f7f7acSHoan Tran }; 249c0f7f7acSHoan Tran 250c0f7f7acSHoan Tran static const struct attribute_group l3c_pmu_v3_format_attr_group = { 251c0f7f7acSHoan Tran .name = "format", 252c0f7f7acSHoan Tran .attrs = l3c_pmu_v3_format_attrs, 253c0f7f7acSHoan Tran }; 254c0f7f7acSHoan Tran 255c0f7f7acSHoan Tran static const struct attribute_group iob_pmu_v3_format_attr_group = { 256c0f7f7acSHoan Tran .name = "format", 257c0f7f7acSHoan Tran .attrs = iob_pmu_v3_format_attrs, 258c0f7f7acSHoan Tran }; 259c0f7f7acSHoan Tran 260c0f7f7acSHoan Tran static const struct attribute_group iob_slow_pmu_v3_format_attr_group = { 261c0f7f7acSHoan Tran .name = "format", 262c0f7f7acSHoan Tran .attrs = iob_slow_pmu_v3_format_attrs, 263c0f7f7acSHoan Tran }; 264c0f7f7acSHoan Tran 265c0f7f7acSHoan Tran static const struct attribute_group mcb_pmu_v3_format_attr_group = { 266c0f7f7acSHoan Tran .name = "format", 267c0f7f7acSHoan Tran .attrs = mcb_pmu_v3_format_attrs, 268c0f7f7acSHoan Tran }; 269c0f7f7acSHoan Tran 270c0f7f7acSHoan Tran static const struct attribute_group mc_pmu_v3_format_attr_group = { 271c0f7f7acSHoan Tran .name = "format", 272c0f7f7acSHoan Tran .attrs = mc_pmu_v3_format_attrs, 273c0f7f7acSHoan Tran }; 274c0f7f7acSHoan Tran 275832c927dSTai Nguyen /* 276832c927dSTai Nguyen * sysfs event attributes 277832c927dSTai Nguyen */ 278832c927dSTai Nguyen static ssize_t xgene_pmu_event_show(struct device *dev, 279832c927dSTai Nguyen struct device_attribute *attr, char *buf) 280832c927dSTai Nguyen { 281832c927dSTai Nguyen struct dev_ext_attribute *eattr; 282832c927dSTai Nguyen 283832c927dSTai Nguyen eattr = container_of(attr, struct dev_ext_attribute, attr); 284832c927dSTai Nguyen return sprintf(buf, "config=0x%lx\n", (unsigned long) eattr->var); 285832c927dSTai Nguyen } 286832c927dSTai Nguyen 287832c927dSTai Nguyen #define XGENE_PMU_EVENT_ATTR(_name, _config) \ 288832c927dSTai Nguyen (&((struct dev_ext_attribute[]) { \ 289832c927dSTai Nguyen { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_event_show, NULL), \ 290832c927dSTai Nguyen .var = (void *) _config, } \ 291832c927dSTai Nguyen })[0].attr.attr) 292832c927dSTai Nguyen 293832c927dSTai Nguyen static struct attribute *l3c_pmu_events_attrs[] = { 294832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 295832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 296832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(read-hit, 0x02), 297832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(read-miss, 0x03), 298832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06), 299832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07), 300832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(tq-full, 0x08), 301832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(ackq-full, 0x09), 302832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a), 303832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b), 304832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(odb-full, 0x0c), 305832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d), 306832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e), 307832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f), 308832c927dSTai Nguyen NULL, 309832c927dSTai Nguyen }; 310832c927dSTai Nguyen 311832c927dSTai Nguyen static struct attribute *iob_pmu_events_attrs[] = { 312832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 313832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 314832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-read, 0x02), 315832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03), 316832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-read, 0x04), 317832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05), 318832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06), 319832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07), 320832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-write, 0x10), 321832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11), 322832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-write, 0x13), 323832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14), 324832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16), 325832c927dSTai Nguyen NULL, 326832c927dSTai Nguyen }; 327832c927dSTai Nguyen 328832c927dSTai Nguyen static struct attribute *mcb_pmu_events_attrs[] = { 329832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 330832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 331832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-read, 0x02), 332832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03), 333832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04), 334832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05), 335832c927dSTai Nguyen NULL, 336832c927dSTai Nguyen }; 337832c927dSTai Nguyen 338832c927dSTai Nguyen static struct attribute *mc_pmu_events_attrs[] = { 339832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 340832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01), 341832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02), 342832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03), 343832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04), 344832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05), 345832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06), 346832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07), 347832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08), 348832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09), 349832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a), 350832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b), 351832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c), 352832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d), 353832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e), 354832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f), 355832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10), 356832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11), 357832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-request, 0x12), 358832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13), 359832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14), 360832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15), 361832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16), 362832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17), 363832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18), 364832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19), 365832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a), 366832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b), 367832c927dSTai Nguyen XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c), 368832c927dSTai Nguyen NULL, 369832c927dSTai Nguyen }; 370832c927dSTai Nguyen 371832c927dSTai Nguyen static const struct attribute_group l3c_pmu_events_attr_group = { 372832c927dSTai Nguyen .name = "events", 373832c927dSTai Nguyen .attrs = l3c_pmu_events_attrs, 374832c927dSTai Nguyen }; 375832c927dSTai Nguyen 376832c927dSTai Nguyen static const struct attribute_group iob_pmu_events_attr_group = { 377832c927dSTai Nguyen .name = "events", 378832c927dSTai Nguyen .attrs = iob_pmu_events_attrs, 379832c927dSTai Nguyen }; 380832c927dSTai Nguyen 381832c927dSTai Nguyen static const struct attribute_group mcb_pmu_events_attr_group = { 382832c927dSTai Nguyen .name = "events", 383832c927dSTai Nguyen .attrs = mcb_pmu_events_attrs, 384832c927dSTai Nguyen }; 385832c927dSTai Nguyen 386832c927dSTai Nguyen static const struct attribute_group mc_pmu_events_attr_group = { 387832c927dSTai Nguyen .name = "events", 388832c927dSTai Nguyen .attrs = mc_pmu_events_attrs, 389832c927dSTai Nguyen }; 390832c927dSTai Nguyen 391c0f7f7acSHoan Tran static struct attribute *l3c_pmu_v3_events_attrs[] = { 392c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 393c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(read-hit, 0x01), 394c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(read-miss, 0x02), 395c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(index-flush-eviction, 0x03), 396c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(write-caused-replacement, 0x04), 397c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(write-not-caused-replacement, 0x05), 398c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(clean-eviction, 0x06), 399c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(dirty-eviction, 0x07), 400c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(read, 0x08), 401c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(write, 0x09), 402c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(request, 0x0a), 403c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b), 404c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(tq-full, 0x0c), 405c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ackq-full, 0x0d), 406c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wdb-full, 0x0e), 407c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(odb-full, 0x10), 408c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wbq-full, 0x11), 409c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall, 0x12), 410c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall, 0x13), 411c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall, 0x14), 412c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(total-insertion, 0x15), 413c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(sip-insertions-r-set, 0x16), 414c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear, 0x17), 415c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(dip-insertions-r-set, 0x18), 416c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear, 0x19), 417c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set, 0x1a), 418c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(egression, 0x1b), 419c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(replacement, 0x1c), 420c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(old-replacement, 0x1d), 421c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(young-replacement, 0x1e), 422c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(r-set-replacement, 0x1f), 423c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(r-clear-replacement, 0x20), 424c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(old-r-replacement, 0x21), 425c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(old-nr-replacement, 0x22), 426c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(young-r-replacement, 0x23), 427c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(young-nr-replacement, 0x24), 428c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(bloomfilter-clearing, 0x25), 429c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(generation-flip, 0x26), 430c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(vcc-droop-detected, 0x27), 431c0f7f7acSHoan Tran NULL, 432c0f7f7acSHoan Tran }; 433c0f7f7acSHoan Tran 434c0f7f7acSHoan Tran static struct attribute *iob_fast_pmu_v3_events_attrs[] = { 435c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 436c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all, 0x01), 437c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd, 0x02), 438c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr, 0x03), 439c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-all-cp-req, 0x04), 440c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-cp-blk-req, 0x05), 441c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req, 0x06), 442c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-cp-rd-req, 0x07), 443c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-cp-wr-req, 0x08), 444c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ba-all-req, 0x09), 445c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ba-rd-req, 0x0a), 446c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ba-wr-req, 0x0b), 447c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued, 0x10), 448c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued, 0x11), 449c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12), 450c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13), 451c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable, 0x14), 452c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15), 453c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req, 0x16), 454c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req, 0x17), 455c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data, 0x18), 456c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS, 0x1b), 457c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c), 458c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d), 459c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops, 0x20), 460c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop, 0x21), 461c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit, 0x22), 462c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop, 0x23), 463c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit, 0x24), 464c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop, 0x25), 465c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit, 0x26), 466c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-req-buffer-full, 0x28), 467c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full, 0x29), 468c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a), 469c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full, 0x2b), 470c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c), 471c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full, 0x2d), 472c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e), 473c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure, 0x2f), 474c0f7f7acSHoan Tran NULL, 475c0f7f7acSHoan Tran }; 476c0f7f7acSHoan Tran 477c0f7f7acSHoan Tran static struct attribute *iob_slow_pmu_v3_events_attrs[] = { 478c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 479c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req, 0x01), 480c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req, 0x02), 481c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req, 0x03), 482c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req, 0x04), 483c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ba-all-axi-req, 0x07), 484c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ba-axi-rd-req, 0x08), 485c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ba-axi-wr-req, 0x09), 486c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ba-free-list-empty, 0x10), 487c0f7f7acSHoan Tran NULL, 488c0f7f7acSHoan Tran }; 489c0f7f7acSHoan Tran 490c0f7f7acSHoan Tran static struct attribute *mcb_pmu_v3_events_attrs[] = { 491c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 492c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(req-receive, 0x01), 493c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-req-recv, 0x02), 494c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-req-recv-2, 0x03), 495c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-req-recv, 0x04), 496c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-req-recv-2, 0x05), 497c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu, 0x06), 498c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2, 0x07), 499c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu, 0x08), 500c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2, 0x09), 501c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a), 502c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b), 503c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c), 504c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req, 0x0d), 505c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2, 0x0e), 506c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu, 0x0f), 507c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(gack-recv, 0x10), 508c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-gack-recv, 0x11), 509c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-gack-recv, 0x12), 510c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cancel-rd-gack, 0x13), 511c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cancel-wr-gack, 0x14), 512c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall, 0x15), 513c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked, 0x16), 514c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall, 0x17), 515c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked, 0x18), 516c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked, 0x19), 517c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-req-table-full, 0x1a), 518c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-stat-table-full, 0x1b), 519c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-wr-table-full, 0x1c), 520c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp, 0x1d), 521c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp, 0x1e), 522c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-retryack-resp, 0x1f), 523c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp, 0x20), 524c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload, 0x21), 525c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass, 0x22), 526c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(volt-droop-detect, 0x23), 527c0f7f7acSHoan Tran NULL, 528c0f7f7acSHoan Tran }; 529c0f7f7acSHoan Tran 530c0f7f7acSHoan Tran static struct attribute *mc_pmu_v3_events_attrs[] = { 531c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(cycle-count, 0x00), 532c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(act-sent, 0x01), 533c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pre-sent, 0x02), 534c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-sent, 0x03), 535c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rda-sent, 0x04), 536c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-sent, 0x05), 537c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wra-sent, 0x06), 538c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(pd-entry-vld, 0x07), 539c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(sref-entry-vld, 0x08), 540c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(prea-sent, 0x09), 541c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(ref-sent, 0x0a), 542c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-rda-sent, 0x0b), 543c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-wra-sent, 0x0c), 544c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(raw-hazard, 0x0d), 545c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(war-hazard, 0x0e), 546c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(waw-hazard, 0x0f), 547c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rar-hazard, 0x10), 548c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard, 0x11), 549c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld, 0x12), 550c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(lprd-req-vld, 0x13), 551c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(hprd-req-vld, 0x14), 552c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld, 0x15), 553c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-req-vld, 0x16), 554c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(partial-wr-req-vld, 0x17), 555c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-retry, 0x18), 556c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-retry, 0x19), 557c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(retry-gnt, 0x1a), 558c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rank-change, 0x1b), 559c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(dir-change, 0x1c), 560c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rank-dir-change, 0x1d), 561c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rank-active, 0x1e), 562c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rank-idle, 0x1f), 563c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rank-pd, 0x20), 564c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rank-sref, 0x21), 565c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh, 0x22), 566c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh, 0x23), 567c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh, 0x24), 568c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(phy-updt-complt, 0x25), 569c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(tz-fail, 0x26), 570c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(dram-errc, 0x27), 571c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(dram-errd, 0x28), 572c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(rd-enq, 0x29), 573c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(wr-enq, 0x2a), 574c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(tmac-limit-reached, 0x2b), 575c0f7f7acSHoan Tran XGENE_PMU_EVENT_ATTR(tmaw-tracker-full, 0x2c), 576c0f7f7acSHoan Tran NULL, 577c0f7f7acSHoan Tran }; 578c0f7f7acSHoan Tran 579c0f7f7acSHoan Tran static const struct attribute_group l3c_pmu_v3_events_attr_group = { 580c0f7f7acSHoan Tran .name = "events", 581c0f7f7acSHoan Tran .attrs = l3c_pmu_v3_events_attrs, 582c0f7f7acSHoan Tran }; 583c0f7f7acSHoan Tran 584c0f7f7acSHoan Tran static const struct attribute_group iob_fast_pmu_v3_events_attr_group = { 585c0f7f7acSHoan Tran .name = "events", 586c0f7f7acSHoan Tran .attrs = iob_fast_pmu_v3_events_attrs, 587c0f7f7acSHoan Tran }; 588c0f7f7acSHoan Tran 589c0f7f7acSHoan Tran static const struct attribute_group iob_slow_pmu_v3_events_attr_group = { 590c0f7f7acSHoan Tran .name = "events", 591c0f7f7acSHoan Tran .attrs = iob_slow_pmu_v3_events_attrs, 592c0f7f7acSHoan Tran }; 593c0f7f7acSHoan Tran 594c0f7f7acSHoan Tran static const struct attribute_group mcb_pmu_v3_events_attr_group = { 595c0f7f7acSHoan Tran .name = "events", 596c0f7f7acSHoan Tran .attrs = mcb_pmu_v3_events_attrs, 597c0f7f7acSHoan Tran }; 598c0f7f7acSHoan Tran 599c0f7f7acSHoan Tran static const struct attribute_group mc_pmu_v3_events_attr_group = { 600c0f7f7acSHoan Tran .name = "events", 601c0f7f7acSHoan Tran .attrs = mc_pmu_v3_events_attrs, 602c0f7f7acSHoan Tran }; 603c0f7f7acSHoan Tran 604832c927dSTai Nguyen /* 605832c927dSTai Nguyen * sysfs cpumask attributes 606832c927dSTai Nguyen */ 607832c927dSTai Nguyen static ssize_t xgene_pmu_cpumask_show(struct device *dev, 608832c927dSTai Nguyen struct device_attribute *attr, char *buf) 609832c927dSTai Nguyen { 610832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev)); 611832c927dSTai Nguyen 612832c927dSTai Nguyen return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu); 613832c927dSTai Nguyen } 614832c927dSTai Nguyen 615832c927dSTai Nguyen static DEVICE_ATTR(cpumask, S_IRUGO, xgene_pmu_cpumask_show, NULL); 616832c927dSTai Nguyen 617832c927dSTai Nguyen static struct attribute *xgene_pmu_cpumask_attrs[] = { 618832c927dSTai Nguyen &dev_attr_cpumask.attr, 619832c927dSTai Nguyen NULL, 620832c927dSTai Nguyen }; 621832c927dSTai Nguyen 622832c927dSTai Nguyen static const struct attribute_group pmu_cpumask_attr_group = { 623832c927dSTai Nguyen .attrs = xgene_pmu_cpumask_attrs, 624832c927dSTai Nguyen }; 625832c927dSTai Nguyen 626832c927dSTai Nguyen /* 627c0f7f7acSHoan Tran * Per PMU device attribute groups of PMU v1 and v2 628832c927dSTai Nguyen */ 629832c927dSTai Nguyen static const struct attribute_group *l3c_pmu_attr_groups[] = { 630832c927dSTai Nguyen &l3c_pmu_format_attr_group, 631832c927dSTai Nguyen &pmu_cpumask_attr_group, 632832c927dSTai Nguyen &l3c_pmu_events_attr_group, 633832c927dSTai Nguyen NULL 634832c927dSTai Nguyen }; 635832c927dSTai Nguyen 636832c927dSTai Nguyen static const struct attribute_group *iob_pmu_attr_groups[] = { 637832c927dSTai Nguyen &iob_pmu_format_attr_group, 638832c927dSTai Nguyen &pmu_cpumask_attr_group, 639832c927dSTai Nguyen &iob_pmu_events_attr_group, 640832c927dSTai Nguyen NULL 641832c927dSTai Nguyen }; 642832c927dSTai Nguyen 643832c927dSTai Nguyen static const struct attribute_group *mcb_pmu_attr_groups[] = { 644832c927dSTai Nguyen &mcb_pmu_format_attr_group, 645832c927dSTai Nguyen &pmu_cpumask_attr_group, 646832c927dSTai Nguyen &mcb_pmu_events_attr_group, 647832c927dSTai Nguyen NULL 648832c927dSTai Nguyen }; 649832c927dSTai Nguyen 650832c927dSTai Nguyen static const struct attribute_group *mc_pmu_attr_groups[] = { 651832c927dSTai Nguyen &mc_pmu_format_attr_group, 652832c927dSTai Nguyen &pmu_cpumask_attr_group, 653832c927dSTai Nguyen &mc_pmu_events_attr_group, 654832c927dSTai Nguyen NULL 655832c927dSTai Nguyen }; 656832c927dSTai Nguyen 657c0f7f7acSHoan Tran /* 658c0f7f7acSHoan Tran * Per PMU device attribute groups of PMU v3 659c0f7f7acSHoan Tran */ 660c0f7f7acSHoan Tran static const struct attribute_group *l3c_pmu_v3_attr_groups[] = { 661c0f7f7acSHoan Tran &l3c_pmu_v3_format_attr_group, 662c0f7f7acSHoan Tran &pmu_cpumask_attr_group, 663c0f7f7acSHoan Tran &l3c_pmu_v3_events_attr_group, 664c0f7f7acSHoan Tran NULL 665c0f7f7acSHoan Tran }; 666c0f7f7acSHoan Tran 667c0f7f7acSHoan Tran static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = { 668c0f7f7acSHoan Tran &iob_pmu_v3_format_attr_group, 669c0f7f7acSHoan Tran &pmu_cpumask_attr_group, 670c0f7f7acSHoan Tran &iob_fast_pmu_v3_events_attr_group, 671c0f7f7acSHoan Tran NULL 672c0f7f7acSHoan Tran }; 673c0f7f7acSHoan Tran 674c0f7f7acSHoan Tran static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = { 675c0f7f7acSHoan Tran &iob_slow_pmu_v3_format_attr_group, 676c0f7f7acSHoan Tran &pmu_cpumask_attr_group, 677c0f7f7acSHoan Tran &iob_slow_pmu_v3_events_attr_group, 678c0f7f7acSHoan Tran NULL 679c0f7f7acSHoan Tran }; 680c0f7f7acSHoan Tran 681c0f7f7acSHoan Tran static const struct attribute_group *mcb_pmu_v3_attr_groups[] = { 682c0f7f7acSHoan Tran &mcb_pmu_v3_format_attr_group, 683c0f7f7acSHoan Tran &pmu_cpumask_attr_group, 684c0f7f7acSHoan Tran &mcb_pmu_v3_events_attr_group, 685c0f7f7acSHoan Tran NULL 686c0f7f7acSHoan Tran }; 687c0f7f7acSHoan Tran 688c0f7f7acSHoan Tran static const struct attribute_group *mc_pmu_v3_attr_groups[] = { 689c0f7f7acSHoan Tran &mc_pmu_v3_format_attr_group, 690c0f7f7acSHoan Tran &pmu_cpumask_attr_group, 691c0f7f7acSHoan Tran &mc_pmu_v3_events_attr_group, 692c0f7f7acSHoan Tran NULL 693c0f7f7acSHoan Tran }; 694c0f7f7acSHoan Tran 695832c927dSTai Nguyen static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev) 696832c927dSTai Nguyen { 697832c927dSTai Nguyen int cntr; 698832c927dSTai Nguyen 699832c927dSTai Nguyen cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask, 700832c927dSTai Nguyen pmu_dev->max_counters); 701832c927dSTai Nguyen if (cntr == pmu_dev->max_counters) 702832c927dSTai Nguyen return -ENOSPC; 703832c927dSTai Nguyen set_bit(cntr, pmu_dev->cntr_assign_mask); 704832c927dSTai Nguyen 705832c927dSTai Nguyen return cntr; 706832c927dSTai Nguyen } 707832c927dSTai Nguyen 708832c927dSTai Nguyen static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr) 709832c927dSTai Nguyen { 710832c927dSTai Nguyen clear_bit(cntr, pmu_dev->cntr_assign_mask); 711832c927dSTai Nguyen } 712832c927dSTai Nguyen 713832c927dSTai Nguyen static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu) 714832c927dSTai Nguyen { 715832c927dSTai Nguyen writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 716832c927dSTai Nguyen } 717832c927dSTai Nguyen 718c0f7f7acSHoan Tran static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu) 719c0f7f7acSHoan Tran { 720c0f7f7acSHoan Tran writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 721c0f7f7acSHoan Tran } 722c0f7f7acSHoan Tran 723832c927dSTai Nguyen static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu) 724832c927dSTai Nguyen { 725832c927dSTai Nguyen writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 726832c927dSTai Nguyen } 727832c927dSTai Nguyen 728c0f7f7acSHoan Tran static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu) 729c0f7f7acSHoan Tran { 730c0f7f7acSHoan Tran writel(PCPPMU_V3_INTCLRMASK, 731c0f7f7acSHoan Tran xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG); 732c0f7f7acSHoan Tran } 733c0f7f7acSHoan Tran 734e35e0a04SHoan Tran static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev, 735e35e0a04SHoan Tran int idx) 736832c927dSTai Nguyen { 737832c927dSTai Nguyen return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); 738832c927dSTai Nguyen } 739832c927dSTai Nguyen 740c0f7f7acSHoan Tran static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev, 741c0f7f7acSHoan Tran int idx) 742c0f7f7acSHoan Tran { 743c0f7f7acSHoan Tran u32 lo, hi; 744c0f7f7acSHoan Tran 745c0f7f7acSHoan Tran /* 746c0f7f7acSHoan Tran * v3 has 64-bit counter registers composed by 2 32-bit registers 747c0f7f7acSHoan Tran * This can be a problem if the counter increases and carries 748c0f7f7acSHoan Tran * out of bit [31] between 2 reads. The extra reads would help 749c0f7f7acSHoan Tran * to prevent this issue. 750c0f7f7acSHoan Tran */ 751c0f7f7acSHoan Tran do { 752c0f7f7acSHoan Tran hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1); 753c0f7f7acSHoan Tran lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx); 754c0f7f7acSHoan Tran } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1)); 755c0f7f7acSHoan Tran 756c0f7f7acSHoan Tran return (((u64)hi << 32) | lo); 757c0f7f7acSHoan Tran } 758c0f7f7acSHoan Tran 759832c927dSTai Nguyen static inline void 760e35e0a04SHoan Tran xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) 761832c927dSTai Nguyen { 762832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); 763832c927dSTai Nguyen } 764832c927dSTai Nguyen 765832c927dSTai Nguyen static inline void 766c0f7f7acSHoan Tran xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val) 767c0f7f7acSHoan Tran { 768c0f7f7acSHoan Tran u32 cnt_lo, cnt_hi; 769c0f7f7acSHoan Tran 770c0f7f7acSHoan Tran cnt_hi = upper_32_bits(val); 771c0f7f7acSHoan Tran cnt_lo = lower_32_bits(val); 772c0f7f7acSHoan Tran 773c0f7f7acSHoan Tran /* v3 has 64-bit counter registers composed by 2 32-bit registers */ 774c0f7f7acSHoan Tran xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo); 775c0f7f7acSHoan Tran xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi); 776c0f7f7acSHoan Tran } 777c0f7f7acSHoan Tran 778c0f7f7acSHoan Tran static inline void 779832c927dSTai Nguyen xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val) 780832c927dSTai Nguyen { 781832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx)); 782832c927dSTai Nguyen } 783832c927dSTai Nguyen 784832c927dSTai Nguyen static inline void 785832c927dSTai Nguyen xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) 786832c927dSTai Nguyen { 787832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMAMR0); 788832c927dSTai Nguyen } 789832c927dSTai Nguyen 790832c927dSTai Nguyen static inline void 791c0f7f7acSHoan Tran xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { } 792c0f7f7acSHoan Tran 793c0f7f7acSHoan Tran static inline void 794832c927dSTai Nguyen xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) 795832c927dSTai Nguyen { 796832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMAMR1); 797832c927dSTai Nguyen } 798832c927dSTai Nguyen 799832c927dSTai Nguyen static inline void 800c0f7f7acSHoan Tran xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { } 801c0f7f7acSHoan Tran 802c0f7f7acSHoan Tran static inline void 803832c927dSTai Nguyen xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx) 804832c927dSTai Nguyen { 805832c927dSTai Nguyen u32 val; 806832c927dSTai Nguyen 807832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET); 808832c927dSTai Nguyen val |= 1 << idx; 809832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET); 810832c927dSTai Nguyen } 811832c927dSTai Nguyen 812832c927dSTai Nguyen static inline void 813832c927dSTai Nguyen xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx) 814832c927dSTai Nguyen { 815832c927dSTai Nguyen u32 val; 816832c927dSTai Nguyen 817832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR); 818832c927dSTai Nguyen val |= 1 << idx; 819832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR); 820832c927dSTai Nguyen } 821832c927dSTai Nguyen 822832c927dSTai Nguyen static inline void 823832c927dSTai Nguyen xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx) 824832c927dSTai Nguyen { 825832c927dSTai Nguyen u32 val; 826832c927dSTai Nguyen 827832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMINTENSET); 828832c927dSTai Nguyen val |= 1 << idx; 829832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMINTENSET); 830832c927dSTai Nguyen } 831832c927dSTai Nguyen 832832c927dSTai Nguyen static inline void 833832c927dSTai Nguyen xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx) 834832c927dSTai Nguyen { 835832c927dSTai Nguyen u32 val; 836832c927dSTai Nguyen 837832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR); 838832c927dSTai Nguyen val |= 1 << idx; 839832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR); 840832c927dSTai Nguyen } 841832c927dSTai Nguyen 842832c927dSTai Nguyen static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev) 843832c927dSTai Nguyen { 844832c927dSTai Nguyen u32 val; 845832c927dSTai Nguyen 846832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCR); 847832c927dSTai Nguyen val |= PMU_PMCR_P; 848832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCR); 849832c927dSTai Nguyen } 850832c927dSTai Nguyen 851832c927dSTai Nguyen static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev) 852832c927dSTai Nguyen { 853832c927dSTai Nguyen u32 val; 854832c927dSTai Nguyen 855832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCR); 856832c927dSTai Nguyen val |= PMU_PMCR_E; 857832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCR); 858832c927dSTai Nguyen } 859832c927dSTai Nguyen 860832c927dSTai Nguyen static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev) 861832c927dSTai Nguyen { 862832c927dSTai Nguyen u32 val; 863832c927dSTai Nguyen 864832c927dSTai Nguyen val = readl(pmu_dev->inf->csr + PMU_PMCR); 865832c927dSTai Nguyen val &= ~PMU_PMCR_E; 866832c927dSTai Nguyen writel(val, pmu_dev->inf->csr + PMU_PMCR); 867832c927dSTai Nguyen } 868832c927dSTai Nguyen 869832c927dSTai Nguyen static void xgene_perf_pmu_enable(struct pmu *pmu) 870832c927dSTai Nguyen { 871832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu); 872e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 873832c927dSTai Nguyen int enabled = bitmap_weight(pmu_dev->cntr_assign_mask, 874832c927dSTai Nguyen pmu_dev->max_counters); 875832c927dSTai Nguyen 876832c927dSTai Nguyen if (!enabled) 877832c927dSTai Nguyen return; 878832c927dSTai Nguyen 879e35e0a04SHoan Tran xgene_pmu->ops->start_counters(pmu_dev); 880832c927dSTai Nguyen } 881832c927dSTai Nguyen 882832c927dSTai Nguyen static void xgene_perf_pmu_disable(struct pmu *pmu) 883832c927dSTai Nguyen { 884832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu); 885e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 886832c927dSTai Nguyen 887e35e0a04SHoan Tran xgene_pmu->ops->stop_counters(pmu_dev); 888832c927dSTai Nguyen } 889832c927dSTai Nguyen 890832c927dSTai Nguyen static int xgene_perf_event_init(struct perf_event *event) 891832c927dSTai Nguyen { 892832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 893832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 894832c927dSTai Nguyen struct perf_event *sibling; 895832c927dSTai Nguyen 896832c927dSTai Nguyen /* Test the event attr type check for PMU enumeration */ 897832c927dSTai Nguyen if (event->attr.type != event->pmu->type) 898832c927dSTai Nguyen return -ENOENT; 899832c927dSTai Nguyen 900832c927dSTai Nguyen /* 901832c927dSTai Nguyen * SOC PMU counters are shared across all cores. 902832c927dSTai Nguyen * Therefore, it does not support per-process mode. 903832c927dSTai Nguyen * Also, it does not support event sampling mode. 904832c927dSTai Nguyen */ 905832c927dSTai Nguyen if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 906832c927dSTai Nguyen return -EINVAL; 907832c927dSTai Nguyen 908832c927dSTai Nguyen if (event->cpu < 0) 909832c927dSTai Nguyen return -EINVAL; 910832c927dSTai Nguyen /* 911832c927dSTai Nguyen * Many perf core operations (eg. events rotation) operate on a 912832c927dSTai Nguyen * single CPU context. This is obvious for CPU PMUs, where one 913832c927dSTai Nguyen * expects the same sets of events being observed on all CPUs, 914832c927dSTai Nguyen * but can lead to issues for off-core PMUs, where each 915832c927dSTai Nguyen * event could be theoretically assigned to a different CPU. To 916832c927dSTai Nguyen * mitigate this, we enforce CPU assignment to one, selected 917832c927dSTai Nguyen * processor (the one described in the "cpumask" attribute). 918832c927dSTai Nguyen */ 919832c927dSTai Nguyen event->cpu = cpumask_first(&pmu_dev->parent->cpu); 920832c927dSTai Nguyen 921832c927dSTai Nguyen hw->config = event->attr.config; 922832c927dSTai Nguyen /* 923832c927dSTai Nguyen * Each bit of the config1 field represents an agent from which the 924832c927dSTai Nguyen * request of the event come. The event is counted only if it's caused 925832c927dSTai Nguyen * by a request of an agent has the bit cleared. 926832c927dSTai Nguyen * By default, the event is counted for all agents. 927832c927dSTai Nguyen */ 928832c927dSTai Nguyen hw->config_base = event->attr.config1; 929832c927dSTai Nguyen 930832c927dSTai Nguyen /* 931832c927dSTai Nguyen * We must NOT create groups containing mixed PMUs, although software 932832c927dSTai Nguyen * events are acceptable 933832c927dSTai Nguyen */ 934832c927dSTai Nguyen if (event->group_leader->pmu != event->pmu && 935832c927dSTai Nguyen !is_software_event(event->group_leader)) 936832c927dSTai Nguyen return -EINVAL; 937832c927dSTai Nguyen 938edb39592SPeter Zijlstra for_each_sibling_event(sibling, event->group_leader) { 939832c927dSTai Nguyen if (sibling->pmu != event->pmu && 940832c927dSTai Nguyen !is_software_event(sibling)) 941832c927dSTai Nguyen return -EINVAL; 942edb39592SPeter Zijlstra } 943832c927dSTai Nguyen 944832c927dSTai Nguyen return 0; 945832c927dSTai Nguyen } 946832c927dSTai Nguyen 947832c927dSTai Nguyen static void xgene_perf_enable_event(struct perf_event *event) 948832c927dSTai Nguyen { 949832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 950e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 951832c927dSTai Nguyen 952e35e0a04SHoan Tran xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event), 953e35e0a04SHoan Tran GET_EVENTID(event)); 954e35e0a04SHoan Tran xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event))); 955832c927dSTai Nguyen if (pmu_dev->inf->type == PMU_TYPE_IOB) 956e35e0a04SHoan Tran xgene_pmu->ops->write_agent1msk(pmu_dev, 957e35e0a04SHoan Tran ~((u32)GET_AGENT1ID(event))); 958832c927dSTai Nguyen 959e35e0a04SHoan Tran xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event)); 960e35e0a04SHoan Tran xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event)); 961832c927dSTai Nguyen } 962832c927dSTai Nguyen 963832c927dSTai Nguyen static void xgene_perf_disable_event(struct perf_event *event) 964832c927dSTai Nguyen { 965832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 966e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 967832c927dSTai Nguyen 968e35e0a04SHoan Tran xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event)); 969e35e0a04SHoan Tran xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event)); 970832c927dSTai Nguyen } 971832c927dSTai Nguyen 972832c927dSTai Nguyen static void xgene_perf_event_set_period(struct perf_event *event) 973832c927dSTai Nguyen { 974832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 975e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 976832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 977832c927dSTai Nguyen /* 978c0f7f7acSHoan Tran * For 32 bit counter, it has a period of 2^32. To account for the 979c0f7f7acSHoan Tran * possibility of extreme interrupt latency we program for a period of 980c0f7f7acSHoan Tran * half that. Hopefully, we can handle the interrupt before another 2^31 981832c927dSTai Nguyen * events occur and the counter overtakes its previous value. 982c0f7f7acSHoan Tran * For 64 bit counter, we don't expect it overflow. 983832c927dSTai Nguyen */ 984832c927dSTai Nguyen u64 val = 1ULL << 31; 985832c927dSTai Nguyen 986832c927dSTai Nguyen local64_set(&hw->prev_count, val); 987e35e0a04SHoan Tran xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val); 988832c927dSTai Nguyen } 989832c927dSTai Nguyen 990832c927dSTai Nguyen static void xgene_perf_event_update(struct perf_event *event) 991832c927dSTai Nguyen { 992832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 993e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 994832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 995832c927dSTai Nguyen u64 delta, prev_raw_count, new_raw_count; 996832c927dSTai Nguyen 997832c927dSTai Nguyen again: 998832c927dSTai Nguyen prev_raw_count = local64_read(&hw->prev_count); 999e35e0a04SHoan Tran new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event)); 1000832c927dSTai Nguyen 1001832c927dSTai Nguyen if (local64_cmpxchg(&hw->prev_count, prev_raw_count, 1002832c927dSTai Nguyen new_raw_count) != prev_raw_count) 1003832c927dSTai Nguyen goto again; 1004832c927dSTai Nguyen 1005832c927dSTai Nguyen delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period; 1006832c927dSTai Nguyen 1007832c927dSTai Nguyen local64_add(delta, &event->count); 1008832c927dSTai Nguyen } 1009832c927dSTai Nguyen 1010832c927dSTai Nguyen static void xgene_perf_read(struct perf_event *event) 1011832c927dSTai Nguyen { 1012832c927dSTai Nguyen xgene_perf_event_update(event); 1013832c927dSTai Nguyen } 1014832c927dSTai Nguyen 1015832c927dSTai Nguyen static void xgene_perf_start(struct perf_event *event, int flags) 1016832c927dSTai Nguyen { 1017832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 1018e35e0a04SHoan Tran struct xgene_pmu *xgene_pmu = pmu_dev->parent; 1019832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 1020832c927dSTai Nguyen 1021832c927dSTai Nguyen if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED))) 1022832c927dSTai Nguyen return; 1023832c927dSTai Nguyen 1024832c927dSTai Nguyen WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE)); 1025832c927dSTai Nguyen hw->state = 0; 1026832c927dSTai Nguyen 1027832c927dSTai Nguyen xgene_perf_event_set_period(event); 1028832c927dSTai Nguyen 1029832c927dSTai Nguyen if (flags & PERF_EF_RELOAD) { 1030832c927dSTai Nguyen u64 prev_raw_count = local64_read(&hw->prev_count); 1031832c927dSTai Nguyen 1032e35e0a04SHoan Tran xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event), 1033e35e0a04SHoan Tran prev_raw_count); 1034832c927dSTai Nguyen } 1035832c927dSTai Nguyen 1036832c927dSTai Nguyen xgene_perf_enable_event(event); 1037832c927dSTai Nguyen perf_event_update_userpage(event); 1038832c927dSTai Nguyen } 1039832c927dSTai Nguyen 1040832c927dSTai Nguyen static void xgene_perf_stop(struct perf_event *event, int flags) 1041832c927dSTai Nguyen { 1042832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 1043832c927dSTai Nguyen 1044832c927dSTai Nguyen if (hw->state & PERF_HES_UPTODATE) 1045832c927dSTai Nguyen return; 1046832c927dSTai Nguyen 1047832c927dSTai Nguyen xgene_perf_disable_event(event); 1048832c927dSTai Nguyen WARN_ON_ONCE(hw->state & PERF_HES_STOPPED); 1049832c927dSTai Nguyen hw->state |= PERF_HES_STOPPED; 1050832c927dSTai Nguyen 1051832c927dSTai Nguyen if (hw->state & PERF_HES_UPTODATE) 1052832c927dSTai Nguyen return; 1053832c927dSTai Nguyen 1054832c927dSTai Nguyen xgene_perf_read(event); 1055832c927dSTai Nguyen hw->state |= PERF_HES_UPTODATE; 1056832c927dSTai Nguyen } 1057832c927dSTai Nguyen 1058832c927dSTai Nguyen static int xgene_perf_add(struct perf_event *event, int flags) 1059832c927dSTai Nguyen { 1060832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 1061832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 1062832c927dSTai Nguyen 1063832c927dSTai Nguyen hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1064832c927dSTai Nguyen 1065832c927dSTai Nguyen /* Allocate an event counter */ 1066832c927dSTai Nguyen hw->idx = get_next_avail_cntr(pmu_dev); 1067832c927dSTai Nguyen if (hw->idx < 0) 1068832c927dSTai Nguyen return -EAGAIN; 1069832c927dSTai Nguyen 1070832c927dSTai Nguyen /* Update counter event pointer for Interrupt handler */ 1071832c927dSTai Nguyen pmu_dev->pmu_counter_event[hw->idx] = event; 1072832c927dSTai Nguyen 1073832c927dSTai Nguyen if (flags & PERF_EF_START) 1074832c927dSTai Nguyen xgene_perf_start(event, PERF_EF_RELOAD); 1075832c927dSTai Nguyen 1076832c927dSTai Nguyen return 0; 1077832c927dSTai Nguyen } 1078832c927dSTai Nguyen 1079832c927dSTai Nguyen static void xgene_perf_del(struct perf_event *event, int flags) 1080832c927dSTai Nguyen { 1081832c927dSTai Nguyen struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu); 1082832c927dSTai Nguyen struct hw_perf_event *hw = &event->hw; 1083832c927dSTai Nguyen 1084832c927dSTai Nguyen xgene_perf_stop(event, PERF_EF_UPDATE); 1085832c927dSTai Nguyen 1086832c927dSTai Nguyen /* clear the assigned counter */ 1087832c927dSTai Nguyen clear_avail_cntr(pmu_dev, GET_CNTR(event)); 1088832c927dSTai Nguyen 1089832c927dSTai Nguyen perf_event_update_userpage(event); 1090832c927dSTai Nguyen pmu_dev->pmu_counter_event[hw->idx] = NULL; 1091832c927dSTai Nguyen } 1092832c927dSTai Nguyen 1093832c927dSTai Nguyen static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name) 1094832c927dSTai Nguyen { 1095832c927dSTai Nguyen struct xgene_pmu *xgene_pmu; 1096832c927dSTai Nguyen 1097c0f7f7acSHoan Tran if (pmu_dev->parent->version == PCP_PMU_V3) 1098c0f7f7acSHoan Tran pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD; 1099c0f7f7acSHoan Tran else 1100c0f7f7acSHoan Tran pmu_dev->max_period = PMU_CNT_MAX_PERIOD; 1101832c927dSTai Nguyen /* First version PMU supports only single event counter */ 1102832c927dSTai Nguyen xgene_pmu = pmu_dev->parent; 1103832c927dSTai Nguyen if (xgene_pmu->version == PCP_PMU_V1) 1104832c927dSTai Nguyen pmu_dev->max_counters = 1; 1105832c927dSTai Nguyen else 1106832c927dSTai Nguyen pmu_dev->max_counters = PMU_MAX_COUNTERS; 1107832c927dSTai Nguyen 1108832c927dSTai Nguyen /* Perf driver registration */ 1109832c927dSTai Nguyen pmu_dev->pmu = (struct pmu) { 1110832c927dSTai Nguyen .attr_groups = pmu_dev->attr_groups, 1111832c927dSTai Nguyen .task_ctx_nr = perf_invalid_context, 1112832c927dSTai Nguyen .pmu_enable = xgene_perf_pmu_enable, 1113832c927dSTai Nguyen .pmu_disable = xgene_perf_pmu_disable, 1114832c927dSTai Nguyen .event_init = xgene_perf_event_init, 1115832c927dSTai Nguyen .add = xgene_perf_add, 1116832c927dSTai Nguyen .del = xgene_perf_del, 1117832c927dSTai Nguyen .start = xgene_perf_start, 1118832c927dSTai Nguyen .stop = xgene_perf_stop, 1119832c927dSTai Nguyen .read = xgene_perf_read, 1120a66b0010SAndrew Murray .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 1121832c927dSTai Nguyen }; 1122832c927dSTai Nguyen 1123832c927dSTai Nguyen /* Hardware counter init */ 1124e35e0a04SHoan Tran xgene_pmu->ops->stop_counters(pmu_dev); 1125e35e0a04SHoan Tran xgene_pmu->ops->reset_counters(pmu_dev); 1126832c927dSTai Nguyen 1127832c927dSTai Nguyen return perf_pmu_register(&pmu_dev->pmu, name, -1); 1128832c927dSTai Nguyen } 1129832c927dSTai Nguyen 1130832c927dSTai Nguyen static int 1131832c927dSTai Nguyen xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx) 1132832c927dSTai Nguyen { 1133832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1134832c927dSTai Nguyen struct xgene_pmu_dev *pmu; 1135832c927dSTai Nguyen 1136832c927dSTai Nguyen pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL); 1137832c927dSTai Nguyen if (!pmu) 1138832c927dSTai Nguyen return -ENOMEM; 1139832c927dSTai Nguyen pmu->parent = xgene_pmu; 1140832c927dSTai Nguyen pmu->inf = &ctx->inf; 1141832c927dSTai Nguyen ctx->pmu_dev = pmu; 1142832c927dSTai Nguyen 1143832c927dSTai Nguyen switch (pmu->inf->type) { 1144832c927dSTai Nguyen case PMU_TYPE_L3C: 1145c0f7f7acSHoan Tran if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask)) 1146c1be2ddbSTai Nguyen return -ENODEV; 1147c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) 1148c0f7f7acSHoan Tran pmu->attr_groups = l3c_pmu_v3_attr_groups; 1149c0f7f7acSHoan Tran else 1150832c927dSTai Nguyen pmu->attr_groups = l3c_pmu_attr_groups; 1151832c927dSTai Nguyen break; 1152832c927dSTai Nguyen case PMU_TYPE_IOB: 1153c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) 1154c0f7f7acSHoan Tran pmu->attr_groups = iob_fast_pmu_v3_attr_groups; 1155c0f7f7acSHoan Tran else 1156832c927dSTai Nguyen pmu->attr_groups = iob_pmu_attr_groups; 1157832c927dSTai Nguyen break; 1158c0f7f7acSHoan Tran case PMU_TYPE_IOB_SLOW: 1159c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) 1160c0f7f7acSHoan Tran pmu->attr_groups = iob_slow_pmu_v3_attr_groups; 1161c0f7f7acSHoan Tran break; 1162832c927dSTai Nguyen case PMU_TYPE_MCB: 1163832c927dSTai Nguyen if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask)) 1164c1be2ddbSTai Nguyen return -ENODEV; 1165c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) 1166c0f7f7acSHoan Tran pmu->attr_groups = mcb_pmu_v3_attr_groups; 1167c0f7f7acSHoan Tran else 1168832c927dSTai Nguyen pmu->attr_groups = mcb_pmu_attr_groups; 1169832c927dSTai Nguyen break; 1170832c927dSTai Nguyen case PMU_TYPE_MC: 1171832c927dSTai Nguyen if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask)) 1172c1be2ddbSTai Nguyen return -ENODEV; 1173c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) 1174c0f7f7acSHoan Tran pmu->attr_groups = mc_pmu_v3_attr_groups; 1175c0f7f7acSHoan Tran else 1176832c927dSTai Nguyen pmu->attr_groups = mc_pmu_attr_groups; 1177832c927dSTai Nguyen break; 1178832c927dSTai Nguyen default: 1179832c927dSTai Nguyen return -EINVAL; 1180832c927dSTai Nguyen } 1181832c927dSTai Nguyen 1182c1be2ddbSTai Nguyen if (xgene_init_perf(pmu, ctx->name)) { 1183832c927dSTai Nguyen dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name); 1184c1be2ddbSTai Nguyen return -ENODEV; 1185832c927dSTai Nguyen } 1186832c927dSTai Nguyen 1187832c927dSTai Nguyen dev_info(dev, "%s PMU registered\n", ctx->name); 1188832c927dSTai Nguyen 1189c1be2ddbSTai Nguyen return 0; 1190832c927dSTai Nguyen } 1191832c927dSTai Nguyen 1192832c927dSTai Nguyen static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev) 1193832c927dSTai Nguyen { 1194832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = pmu_dev->parent; 1195c0f7f7acSHoan Tran void __iomem *csr = pmu_dev->inf->csr; 1196832c927dSTai Nguyen u32 pmovsr; 1197832c927dSTai Nguyen int idx; 1198832c927dSTai Nguyen 1199c0f7f7acSHoan Tran xgene_pmu->ops->stop_counters(pmu_dev); 1200c0f7f7acSHoan Tran 1201c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) 1202c0f7f7acSHoan Tran pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK; 1203c0f7f7acSHoan Tran else 1204c0f7f7acSHoan Tran pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK; 1205c0f7f7acSHoan Tran 1206832c927dSTai Nguyen if (!pmovsr) 1207c0f7f7acSHoan Tran goto out; 1208832c927dSTai Nguyen 1209832c927dSTai Nguyen /* Clear interrupt flag */ 1210832c927dSTai Nguyen if (xgene_pmu->version == PCP_PMU_V1) 1211c0f7f7acSHoan Tran writel(0x0, csr + PMU_PMOVSR); 1212c0f7f7acSHoan Tran else if (xgene_pmu->version == PCP_PMU_V2) 1213c0f7f7acSHoan Tran writel(pmovsr, csr + PMU_PMOVSR); 1214832c927dSTai Nguyen else 1215c0f7f7acSHoan Tran writel(pmovsr, csr + PMU_PMOVSCLR); 1216832c927dSTai Nguyen 1217832c927dSTai Nguyen for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) { 1218832c927dSTai Nguyen struct perf_event *event = pmu_dev->pmu_counter_event[idx]; 1219832c927dSTai Nguyen int overflowed = pmovsr & BIT(idx); 1220832c927dSTai Nguyen 1221832c927dSTai Nguyen /* Ignore if we don't have an event. */ 1222832c927dSTai Nguyen if (!event || !overflowed) 1223832c927dSTai Nguyen continue; 1224832c927dSTai Nguyen xgene_perf_event_update(event); 1225832c927dSTai Nguyen xgene_perf_event_set_period(event); 1226832c927dSTai Nguyen } 1227c0f7f7acSHoan Tran 1228c0f7f7acSHoan Tran out: 1229c0f7f7acSHoan Tran xgene_pmu->ops->start_counters(pmu_dev); 1230832c927dSTai Nguyen } 1231832c927dSTai Nguyen 1232832c927dSTai Nguyen static irqreturn_t xgene_pmu_isr(int irq, void *dev_id) 1233832c927dSTai Nguyen { 1234c0f7f7acSHoan Tran u32 intr_mcu, intr_mcb, intr_l3c, intr_iob; 1235832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1236832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = dev_id; 1237832c927dSTai Nguyen unsigned long flags; 1238832c927dSTai Nguyen u32 val; 1239832c927dSTai Nguyen 1240832c927dSTai Nguyen raw_spin_lock_irqsave(&xgene_pmu->lock, flags); 1241832c927dSTai Nguyen 1242832c927dSTai Nguyen /* Get Interrupt PMU source */ 1243832c927dSTai Nguyen val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG); 1244c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) { 1245c0f7f7acSHoan Tran intr_mcu = PCPPMU_V3_INT_MCU; 1246c0f7f7acSHoan Tran intr_mcb = PCPPMU_V3_INT_MCB; 1247c0f7f7acSHoan Tran intr_l3c = PCPPMU_V3_INT_L3C; 1248c0f7f7acSHoan Tran intr_iob = PCPPMU_V3_INT_IOB; 1249c0f7f7acSHoan Tran } else { 1250c0f7f7acSHoan Tran intr_mcu = PCPPMU_INT_MCU; 1251c0f7f7acSHoan Tran intr_mcb = PCPPMU_INT_MCB; 1252c0f7f7acSHoan Tran intr_l3c = PCPPMU_INT_L3C; 1253c0f7f7acSHoan Tran intr_iob = PCPPMU_INT_IOB; 1254c0f7f7acSHoan Tran } 1255c0f7f7acSHoan Tran if (val & intr_mcu) { 1256832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) { 1257832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 1258832c927dSTai Nguyen } 1259832c927dSTai Nguyen } 1260c0f7f7acSHoan Tran if (val & intr_mcb) { 1261832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) { 1262832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 1263832c927dSTai Nguyen } 1264832c927dSTai Nguyen } 1265c0f7f7acSHoan Tran if (val & intr_l3c) { 1266832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) { 1267832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 1268832c927dSTai Nguyen } 1269832c927dSTai Nguyen } 1270c0f7f7acSHoan Tran if (val & intr_iob) { 1271832c927dSTai Nguyen list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) { 1272832c927dSTai Nguyen _xgene_pmu_isr(irq, ctx->pmu_dev); 1273832c927dSTai Nguyen } 1274832c927dSTai Nguyen } 1275832c927dSTai Nguyen 1276832c927dSTai Nguyen raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags); 1277832c927dSTai Nguyen 1278832c927dSTai Nguyen return IRQ_HANDLED; 1279832c927dSTai Nguyen } 1280832c927dSTai Nguyen 1281c0f7f7acSHoan Tran static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1282832c927dSTai Nguyen struct platform_device *pdev) 1283832c927dSTai Nguyen { 1284832c927dSTai Nguyen void __iomem *csw_csr, *mcba_csr, *mcbb_csr; 1285832c927dSTai Nguyen struct resource *res; 1286832c927dSTai Nguyen unsigned int reg; 1287832c927dSTai Nguyen 1288832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1289832c927dSTai Nguyen csw_csr = devm_ioremap_resource(&pdev->dev, res); 1290832c927dSTai Nguyen if (IS_ERR(csw_csr)) { 1291832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n"); 1292832c927dSTai Nguyen return PTR_ERR(csw_csr); 1293832c927dSTai Nguyen } 1294832c927dSTai Nguyen 1295832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1296832c927dSTai Nguyen mcba_csr = devm_ioremap_resource(&pdev->dev, res); 1297832c927dSTai Nguyen if (IS_ERR(mcba_csr)) { 1298832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n"); 1299832c927dSTai Nguyen return PTR_ERR(mcba_csr); 1300832c927dSTai Nguyen } 1301832c927dSTai Nguyen 1302832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1303832c927dSTai Nguyen mcbb_csr = devm_ioremap_resource(&pdev->dev, res); 1304832c927dSTai Nguyen if (IS_ERR(mcbb_csr)) { 1305832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n"); 1306832c927dSTai Nguyen return PTR_ERR(mcbb_csr); 1307832c927dSTai Nguyen } 1308832c927dSTai Nguyen 1309c0f7f7acSHoan Tran xgene_pmu->l3c_active_mask = 0x1; 1310c0f7f7acSHoan Tran 1311832c927dSTai Nguyen reg = readl(csw_csr + CSW_CSWCR); 1312832c927dSTai Nguyen if (reg & CSW_CSWCR_DUALMCB_MASK) { 1313832c927dSTai Nguyen /* Dual MCB active */ 1314832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x3; 1315832c927dSTai Nguyen /* Probe all active MC(s) */ 1316832c927dSTai Nguyen reg = readl(mcbb_csr + CSW_CSWCR); 1317832c927dSTai Nguyen xgene_pmu->mc_active_mask = 1318832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; 1319832c927dSTai Nguyen } else { 1320832c927dSTai Nguyen /* Single MCB active */ 1321832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x1; 1322832c927dSTai Nguyen /* Probe all active MC(s) */ 1323832c927dSTai Nguyen reg = readl(mcba_csr + CSW_CSWCR); 1324832c927dSTai Nguyen xgene_pmu->mc_active_mask = 1325832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; 1326832c927dSTai Nguyen } 1327832c927dSTai Nguyen 1328832c927dSTai Nguyen return 0; 1329832c927dSTai Nguyen } 1330832c927dSTai Nguyen 1331c0f7f7acSHoan Tran static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1332c0f7f7acSHoan Tran struct platform_device *pdev) 1333c0f7f7acSHoan Tran { 1334c0f7f7acSHoan Tran void __iomem *csw_csr; 1335c0f7f7acSHoan Tran struct resource *res; 1336c0f7f7acSHoan Tran unsigned int reg; 1337c0f7f7acSHoan Tran u32 mcb0routing; 1338c0f7f7acSHoan Tran u32 mcb1routing; 1339c0f7f7acSHoan Tran 1340c0f7f7acSHoan Tran res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1341c0f7f7acSHoan Tran csw_csr = devm_ioremap_resource(&pdev->dev, res); 1342c0f7f7acSHoan Tran if (IS_ERR(csw_csr)) { 1343c0f7f7acSHoan Tran dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n"); 1344c0f7f7acSHoan Tran return PTR_ERR(csw_csr); 1345c0f7f7acSHoan Tran } 1346c0f7f7acSHoan Tran 1347c0f7f7acSHoan Tran reg = readl(csw_csr + CSW_CSWCR); 1348c0f7f7acSHoan Tran mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg); 1349c0f7f7acSHoan Tran mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg); 1350c0f7f7acSHoan Tran if (reg & CSW_CSWCR_DUALMCB_MASK) { 1351c0f7f7acSHoan Tran /* Dual MCB active */ 1352c0f7f7acSHoan Tran xgene_pmu->mcb_active_mask = 0x3; 1353c0f7f7acSHoan Tran /* Probe all active L3C(s), maximum is 8 */ 1354c0f7f7acSHoan Tran xgene_pmu->l3c_active_mask = 0xFF; 1355c0f7f7acSHoan Tran /* Probe all active MC(s), maximum is 8 */ 1356c0f7f7acSHoan Tran if ((mcb0routing == 0x2) && (mcb1routing == 0x2)) 1357c0f7f7acSHoan Tran xgene_pmu->mc_active_mask = 0xFF; 1358c0f7f7acSHoan Tran else if ((mcb0routing == 0x1) && (mcb1routing == 0x1)) 1359c0f7f7acSHoan Tran xgene_pmu->mc_active_mask = 0x33; 1360c0f7f7acSHoan Tran else 1361c0f7f7acSHoan Tran xgene_pmu->mc_active_mask = 0x11; 1362c0f7f7acSHoan Tran } else { 1363c0f7f7acSHoan Tran /* Single MCB active */ 1364c0f7f7acSHoan Tran xgene_pmu->mcb_active_mask = 0x1; 1365c0f7f7acSHoan Tran /* Probe all active L3C(s), maximum is 4 */ 1366c0f7f7acSHoan Tran xgene_pmu->l3c_active_mask = 0x0F; 1367c0f7f7acSHoan Tran /* Probe all active MC(s), maximum is 4 */ 1368c0f7f7acSHoan Tran if (mcb0routing == 0x2) 1369c0f7f7acSHoan Tran xgene_pmu->mc_active_mask = 0x0F; 1370c0f7f7acSHoan Tran else if (mcb0routing == 0x1) 1371c0f7f7acSHoan Tran xgene_pmu->mc_active_mask = 0x03; 1372c0f7f7acSHoan Tran else 1373c0f7f7acSHoan Tran xgene_pmu->mc_active_mask = 0x01; 1374c0f7f7acSHoan Tran } 1375c0f7f7acSHoan Tran 1376c0f7f7acSHoan Tran return 0; 1377c0f7f7acSHoan Tran } 1378c0f7f7acSHoan Tran 1379c0f7f7acSHoan Tran static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1380832c927dSTai Nguyen struct platform_device *pdev) 1381832c927dSTai Nguyen { 1382832c927dSTai Nguyen struct regmap *csw_map, *mcba_map, *mcbb_map; 1383832c927dSTai Nguyen struct device_node *np = pdev->dev.of_node; 1384832c927dSTai Nguyen unsigned int reg; 1385832c927dSTai Nguyen 1386832c927dSTai Nguyen csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw"); 1387832c927dSTai Nguyen if (IS_ERR(csw_map)) { 1388832c927dSTai Nguyen dev_err(&pdev->dev, "unable to get syscon regmap csw\n"); 1389832c927dSTai Nguyen return PTR_ERR(csw_map); 1390832c927dSTai Nguyen } 1391832c927dSTai Nguyen 1392832c927dSTai Nguyen mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba"); 1393832c927dSTai Nguyen if (IS_ERR(mcba_map)) { 1394832c927dSTai Nguyen dev_err(&pdev->dev, "unable to get syscon regmap mcba\n"); 1395832c927dSTai Nguyen return PTR_ERR(mcba_map); 1396832c927dSTai Nguyen } 1397832c927dSTai Nguyen 1398832c927dSTai Nguyen mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb"); 1399832c927dSTai Nguyen if (IS_ERR(mcbb_map)) { 1400832c927dSTai Nguyen dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n"); 1401832c927dSTai Nguyen return PTR_ERR(mcbb_map); 1402832c927dSTai Nguyen } 1403832c927dSTai Nguyen 1404c0f7f7acSHoan Tran xgene_pmu->l3c_active_mask = 0x1; 1405832c927dSTai Nguyen if (regmap_read(csw_map, CSW_CSWCR, ®)) 1406832c927dSTai Nguyen return -EINVAL; 1407832c927dSTai Nguyen 1408832c927dSTai Nguyen if (reg & CSW_CSWCR_DUALMCB_MASK) { 1409832c927dSTai Nguyen /* Dual MCB active */ 1410832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x3; 1411832c927dSTai Nguyen /* Probe all active MC(s) */ 1412832c927dSTai Nguyen if (regmap_read(mcbb_map, MCBADDRMR, ®)) 1413832c927dSTai Nguyen return 0; 1414832c927dSTai Nguyen xgene_pmu->mc_active_mask = 1415832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; 1416832c927dSTai Nguyen } else { 1417832c927dSTai Nguyen /* Single MCB active */ 1418832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x1; 1419832c927dSTai Nguyen /* Probe all active MC(s) */ 1420832c927dSTai Nguyen if (regmap_read(mcba_map, MCBADDRMR, ®)) 1421832c927dSTai Nguyen return 0; 1422832c927dSTai Nguyen xgene_pmu->mc_active_mask = 1423832c927dSTai Nguyen (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; 1424832c927dSTai Nguyen } 1425832c927dSTai Nguyen 1426832c927dSTai Nguyen return 0; 1427832c927dSTai Nguyen } 1428832c927dSTai Nguyen 1429c0f7f7acSHoan Tran static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu, 1430832c927dSTai Nguyen struct platform_device *pdev) 1431832c927dSTai Nguyen { 1432c0f7f7acSHoan Tran if (has_acpi_companion(&pdev->dev)) { 1433c0f7f7acSHoan Tran if (xgene_pmu->version == PCP_PMU_V3) 1434c0f7f7acSHoan Tran return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu, 1435c0f7f7acSHoan Tran pdev); 1436c0f7f7acSHoan Tran else 1437c0f7f7acSHoan Tran return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, 1438c0f7f7acSHoan Tran pdev); 1439c0f7f7acSHoan Tran } 1440c0f7f7acSHoan Tran return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev); 1441832c927dSTai Nguyen } 1442832c927dSTai Nguyen 1443832c927dSTai Nguyen static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id) 1444832c927dSTai Nguyen { 1445832c927dSTai Nguyen switch (type) { 1446832c927dSTai Nguyen case PMU_TYPE_L3C: 1447832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id); 1448832c927dSTai Nguyen case PMU_TYPE_IOB: 1449832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id); 1450c0f7f7acSHoan Tran case PMU_TYPE_IOB_SLOW: 1451a45fc268SHoan Tran return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d", id); 1452832c927dSTai Nguyen case PMU_TYPE_MCB: 1453832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id); 1454832c927dSTai Nguyen case PMU_TYPE_MC: 1455832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id); 1456832c927dSTai Nguyen default: 1457832c927dSTai Nguyen return devm_kasprintf(dev, GFP_KERNEL, "unknown"); 1458832c927dSTai Nguyen } 1459832c927dSTai Nguyen } 1460832c927dSTai Nguyen 1461832c927dSTai Nguyen #if defined(CONFIG_ACPI) 1462832c927dSTai Nguyen static int acpi_pmu_dev_add_resource(struct acpi_resource *ares, void *data) 1463832c927dSTai Nguyen { 1464832c927dSTai Nguyen struct resource *res = data; 1465832c927dSTai Nguyen 1466832c927dSTai Nguyen if (ares->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) 1467832c927dSTai Nguyen acpi_dev_resource_memory(ares, res); 1468832c927dSTai Nguyen 1469832c927dSTai Nguyen /* Always tell the ACPI core to skip this resource */ 1470832c927dSTai Nguyen return 1; 1471832c927dSTai Nguyen } 1472832c927dSTai Nguyen 1473832c927dSTai Nguyen static struct 1474832c927dSTai Nguyen xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu, 1475832c927dSTai Nguyen struct acpi_device *adev, u32 type) 1476832c927dSTai Nguyen { 1477832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1478832c927dSTai Nguyen struct list_head resource_list; 1479832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1480832c927dSTai Nguyen const union acpi_object *obj; 1481832c927dSTai Nguyen struct hw_pmu_info *inf; 1482832c927dSTai Nguyen void __iomem *dev_csr; 1483832c927dSTai Nguyen struct resource res; 1484832c927dSTai Nguyen int enable_bit; 1485832c927dSTai Nguyen int rc; 1486832c927dSTai Nguyen 1487832c927dSTai Nguyen ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1488832c927dSTai Nguyen if (!ctx) 1489832c927dSTai Nguyen return NULL; 1490832c927dSTai Nguyen 1491832c927dSTai Nguyen INIT_LIST_HEAD(&resource_list); 1492832c927dSTai Nguyen rc = acpi_dev_get_resources(adev, &resource_list, 1493832c927dSTai Nguyen acpi_pmu_dev_add_resource, &res); 1494832c927dSTai Nguyen acpi_dev_free_resource_list(&resource_list); 14959a1a1f40STai Nguyen if (rc < 0) { 1496832c927dSTai Nguyen dev_err(dev, "PMU type %d: No resource address found\n", type); 1497c1be2ddbSTai Nguyen return NULL; 1498832c927dSTai Nguyen } 1499832c927dSTai Nguyen 1500832c927dSTai Nguyen dev_csr = devm_ioremap_resource(dev, &res); 1501832c927dSTai Nguyen if (IS_ERR(dev_csr)) { 1502832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to map resource\n", type); 1503c1be2ddbSTai Nguyen return NULL; 1504832c927dSTai Nguyen } 1505832c927dSTai Nguyen 1506832c927dSTai Nguyen /* A PMU device node without enable-bit-index is always enabled */ 1507832c927dSTai Nguyen rc = acpi_dev_get_property(adev, "enable-bit-index", 1508832c927dSTai Nguyen ACPI_TYPE_INTEGER, &obj); 1509832c927dSTai Nguyen if (rc < 0) 1510832c927dSTai Nguyen enable_bit = 0; 1511832c927dSTai Nguyen else 1512832c927dSTai Nguyen enable_bit = (int) obj->integer.value; 1513832c927dSTai Nguyen 1514832c927dSTai Nguyen ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); 1515832c927dSTai Nguyen if (!ctx->name) { 1516832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to get device name\n", type); 1517c1be2ddbSTai Nguyen return NULL; 1518832c927dSTai Nguyen } 1519832c927dSTai Nguyen inf = &ctx->inf; 1520832c927dSTai Nguyen inf->type = type; 1521832c927dSTai Nguyen inf->csr = dev_csr; 1522832c927dSTai Nguyen inf->enable_mask = 1 << enable_bit; 1523832c927dSTai Nguyen 1524832c927dSTai Nguyen return ctx; 1525832c927dSTai Nguyen } 1526832c927dSTai Nguyen 1527838955e2SHoan Tran static const struct acpi_device_id xgene_pmu_acpi_type_match[] = { 1528838955e2SHoan Tran {"APMC0D5D", PMU_TYPE_L3C}, 1529838955e2SHoan Tran {"APMC0D5E", PMU_TYPE_IOB}, 1530838955e2SHoan Tran {"APMC0D5F", PMU_TYPE_MCB}, 1531838955e2SHoan Tran {"APMC0D60", PMU_TYPE_MC}, 1532c0f7f7acSHoan Tran {"APMC0D84", PMU_TYPE_L3C}, 1533c0f7f7acSHoan Tran {"APMC0D85", PMU_TYPE_IOB}, 1534c0f7f7acSHoan Tran {"APMC0D86", PMU_TYPE_IOB_SLOW}, 1535c0f7f7acSHoan Tran {"APMC0D87", PMU_TYPE_MCB}, 1536c0f7f7acSHoan Tran {"APMC0D88", PMU_TYPE_MC}, 1537838955e2SHoan Tran {}, 1538838955e2SHoan Tran }; 1539838955e2SHoan Tran 1540838955e2SHoan Tran static const struct acpi_device_id *xgene_pmu_acpi_match_type( 1541838955e2SHoan Tran const struct acpi_device_id *ids, 1542838955e2SHoan Tran struct acpi_device *adev) 1543838955e2SHoan Tran { 1544838955e2SHoan Tran const struct acpi_device_id *match_id = NULL; 1545838955e2SHoan Tran const struct acpi_device_id *id; 1546838955e2SHoan Tran 1547838955e2SHoan Tran for (id = ids; id->id[0] || id->cls; id++) { 1548838955e2SHoan Tran if (!acpi_match_device_ids(adev, id)) 1549838955e2SHoan Tran match_id = id; 1550838955e2SHoan Tran else if (match_id) 1551838955e2SHoan Tran break; 1552838955e2SHoan Tran } 1553838955e2SHoan Tran 1554838955e2SHoan Tran return match_id; 1555838955e2SHoan Tran } 1556838955e2SHoan Tran 1557832c927dSTai Nguyen static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level, 1558832c927dSTai Nguyen void *data, void **return_value) 1559832c927dSTai Nguyen { 1560838955e2SHoan Tran const struct acpi_device_id *acpi_id; 1561832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = data; 1562832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1563832c927dSTai Nguyen struct acpi_device *adev; 1564832c927dSTai Nguyen 1565832c927dSTai Nguyen if (acpi_bus_get_device(handle, &adev)) 1566832c927dSTai Nguyen return AE_OK; 1567832c927dSTai Nguyen if (acpi_bus_get_status(adev) || !adev->status.present) 1568832c927dSTai Nguyen return AE_OK; 1569832c927dSTai Nguyen 1570838955e2SHoan Tran acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev); 1571838955e2SHoan Tran if (!acpi_id) 1572838955e2SHoan Tran return AE_OK; 1573832c927dSTai Nguyen 1574838955e2SHoan Tran ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data); 1575832c927dSTai Nguyen if (!ctx) 1576832c927dSTai Nguyen return AE_OK; 1577832c927dSTai Nguyen 1578832c927dSTai Nguyen if (xgene_pmu_dev_add(xgene_pmu, ctx)) { 1579832c927dSTai Nguyen /* Can't add the PMU device, skip it */ 1580832c927dSTai Nguyen devm_kfree(xgene_pmu->dev, ctx); 1581832c927dSTai Nguyen return AE_OK; 1582832c927dSTai Nguyen } 1583832c927dSTai Nguyen 1584832c927dSTai Nguyen switch (ctx->inf.type) { 1585832c927dSTai Nguyen case PMU_TYPE_L3C: 1586832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->l3cpmus); 1587832c927dSTai Nguyen break; 1588832c927dSTai Nguyen case PMU_TYPE_IOB: 1589832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->iobpmus); 1590832c927dSTai Nguyen break; 1591c0f7f7acSHoan Tran case PMU_TYPE_IOB_SLOW: 1592c0f7f7acSHoan Tran list_add(&ctx->next, &xgene_pmu->iobpmus); 1593c0f7f7acSHoan Tran break; 1594832c927dSTai Nguyen case PMU_TYPE_MCB: 1595832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcbpmus); 1596832c927dSTai Nguyen break; 1597832c927dSTai Nguyen case PMU_TYPE_MC: 1598832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcpmus); 1599832c927dSTai Nguyen break; 1600832c927dSTai Nguyen } 1601832c927dSTai Nguyen return AE_OK; 1602832c927dSTai Nguyen } 1603832c927dSTai Nguyen 1604832c927dSTai Nguyen static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1605832c927dSTai Nguyen struct platform_device *pdev) 1606832c927dSTai Nguyen { 1607832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1608832c927dSTai Nguyen acpi_handle handle; 1609832c927dSTai Nguyen acpi_status status; 1610832c927dSTai Nguyen 1611832c927dSTai Nguyen handle = ACPI_HANDLE(dev); 1612832c927dSTai Nguyen if (!handle) 1613832c927dSTai Nguyen return -EINVAL; 1614832c927dSTai Nguyen 1615832c927dSTai Nguyen status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1, 1616832c927dSTai Nguyen acpi_pmu_dev_add, NULL, xgene_pmu, NULL); 1617832c927dSTai Nguyen if (ACPI_FAILURE(status)) { 1618832c927dSTai Nguyen dev_err(dev, "failed to probe PMU devices\n"); 1619832c927dSTai Nguyen return -ENODEV; 1620832c927dSTai Nguyen } 1621832c927dSTai Nguyen 1622832c927dSTai Nguyen return 0; 1623832c927dSTai Nguyen } 1624832c927dSTai Nguyen #else 1625832c927dSTai Nguyen static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1626832c927dSTai Nguyen struct platform_device *pdev) 1627832c927dSTai Nguyen { 1628832c927dSTai Nguyen return 0; 1629832c927dSTai Nguyen } 1630832c927dSTai Nguyen #endif 1631832c927dSTai Nguyen 1632832c927dSTai Nguyen static struct 1633832c927dSTai Nguyen xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu, 1634832c927dSTai Nguyen struct device_node *np, u32 type) 1635832c927dSTai Nguyen { 1636832c927dSTai Nguyen struct device *dev = xgene_pmu->dev; 1637832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1638832c927dSTai Nguyen struct hw_pmu_info *inf; 1639832c927dSTai Nguyen void __iomem *dev_csr; 1640832c927dSTai Nguyen struct resource res; 1641832c927dSTai Nguyen int enable_bit; 1642832c927dSTai Nguyen 1643832c927dSTai Nguyen ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1644832c927dSTai Nguyen if (!ctx) 1645832c927dSTai Nguyen return NULL; 1646c1be2ddbSTai Nguyen 1647c1be2ddbSTai Nguyen if (of_address_to_resource(np, 0, &res) < 0) { 1648832c927dSTai Nguyen dev_err(dev, "PMU type %d: No resource address found\n", type); 1649c1be2ddbSTai Nguyen return NULL; 1650832c927dSTai Nguyen } 1651c1be2ddbSTai Nguyen 1652832c927dSTai Nguyen dev_csr = devm_ioremap_resource(dev, &res); 1653832c927dSTai Nguyen if (IS_ERR(dev_csr)) { 1654832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to map resource\n", type); 1655c1be2ddbSTai Nguyen return NULL; 1656832c927dSTai Nguyen } 1657832c927dSTai Nguyen 1658832c927dSTai Nguyen /* A PMU device node without enable-bit-index is always enabled */ 1659832c927dSTai Nguyen if (of_property_read_u32(np, "enable-bit-index", &enable_bit)) 1660832c927dSTai Nguyen enable_bit = 0; 1661832c927dSTai Nguyen 1662832c927dSTai Nguyen ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); 1663832c927dSTai Nguyen if (!ctx->name) { 1664832c927dSTai Nguyen dev_err(dev, "PMU type %d: Fail to get device name\n", type); 1665c1be2ddbSTai Nguyen return NULL; 1666832c927dSTai Nguyen } 1667c1be2ddbSTai Nguyen 1668832c927dSTai Nguyen inf = &ctx->inf; 1669832c927dSTai Nguyen inf->type = type; 1670832c927dSTai Nguyen inf->csr = dev_csr; 1671832c927dSTai Nguyen inf->enable_mask = 1 << enable_bit; 1672832c927dSTai Nguyen 1673832c927dSTai Nguyen return ctx; 1674832c927dSTai Nguyen } 1675832c927dSTai Nguyen 1676832c927dSTai Nguyen static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1677832c927dSTai Nguyen struct platform_device *pdev) 1678832c927dSTai Nguyen { 1679832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1680832c927dSTai Nguyen struct device_node *np; 1681832c927dSTai Nguyen 1682832c927dSTai Nguyen for_each_child_of_node(pdev->dev.of_node, np) { 1683832c927dSTai Nguyen if (!of_device_is_available(np)) 1684832c927dSTai Nguyen continue; 1685832c927dSTai Nguyen 1686832c927dSTai Nguyen if (of_device_is_compatible(np, "apm,xgene-pmu-l3c")) 1687832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C); 1688832c927dSTai Nguyen else if (of_device_is_compatible(np, "apm,xgene-pmu-iob")) 1689832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB); 1690832c927dSTai Nguyen else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb")) 1691832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB); 1692832c927dSTai Nguyen else if (of_device_is_compatible(np, "apm,xgene-pmu-mc")) 1693832c927dSTai Nguyen ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC); 1694832c927dSTai Nguyen else 1695832c927dSTai Nguyen ctx = NULL; 1696832c927dSTai Nguyen 1697832c927dSTai Nguyen if (!ctx) 1698832c927dSTai Nguyen continue; 1699832c927dSTai Nguyen 1700832c927dSTai Nguyen if (xgene_pmu_dev_add(xgene_pmu, ctx)) { 1701832c927dSTai Nguyen /* Can't add the PMU device, skip it */ 1702832c927dSTai Nguyen devm_kfree(xgene_pmu->dev, ctx); 1703832c927dSTai Nguyen continue; 1704832c927dSTai Nguyen } 1705832c927dSTai Nguyen 1706832c927dSTai Nguyen switch (ctx->inf.type) { 1707832c927dSTai Nguyen case PMU_TYPE_L3C: 1708832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->l3cpmus); 1709832c927dSTai Nguyen break; 1710832c927dSTai Nguyen case PMU_TYPE_IOB: 1711832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->iobpmus); 1712832c927dSTai Nguyen break; 1713c0f7f7acSHoan Tran case PMU_TYPE_IOB_SLOW: 1714c0f7f7acSHoan Tran list_add(&ctx->next, &xgene_pmu->iobpmus); 1715c0f7f7acSHoan Tran break; 1716832c927dSTai Nguyen case PMU_TYPE_MCB: 1717832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcbpmus); 1718832c927dSTai Nguyen break; 1719832c927dSTai Nguyen case PMU_TYPE_MC: 1720832c927dSTai Nguyen list_add(&ctx->next, &xgene_pmu->mcpmus); 1721832c927dSTai Nguyen break; 1722832c927dSTai Nguyen } 1723832c927dSTai Nguyen } 1724832c927dSTai Nguyen 1725832c927dSTai Nguyen return 0; 1726832c927dSTai Nguyen } 1727832c927dSTai Nguyen 1728832c927dSTai Nguyen static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu, 1729832c927dSTai Nguyen struct platform_device *pdev) 1730832c927dSTai Nguyen { 1731832c927dSTai Nguyen if (has_acpi_companion(&pdev->dev)) 1732832c927dSTai Nguyen return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev); 1733832c927dSTai Nguyen return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev); 1734832c927dSTai Nguyen } 1735832c927dSTai Nguyen 1736832c927dSTai Nguyen static const struct xgene_pmu_data xgene_pmu_data = { 1737832c927dSTai Nguyen .id = PCP_PMU_V1, 1738832c927dSTai Nguyen }; 1739832c927dSTai Nguyen 1740832c927dSTai Nguyen static const struct xgene_pmu_data xgene_pmu_v2_data = { 1741832c927dSTai Nguyen .id = PCP_PMU_V2, 1742832c927dSTai Nguyen }; 1743832c927dSTai Nguyen 1744e35e0a04SHoan Tran static const struct xgene_pmu_ops xgene_pmu_ops = { 1745e35e0a04SHoan Tran .mask_int = xgene_pmu_mask_int, 1746e35e0a04SHoan Tran .unmask_int = xgene_pmu_unmask_int, 1747e35e0a04SHoan Tran .read_counter = xgene_pmu_read_counter32, 1748e35e0a04SHoan Tran .write_counter = xgene_pmu_write_counter32, 1749e35e0a04SHoan Tran .write_evttype = xgene_pmu_write_evttype, 1750e35e0a04SHoan Tran .write_agentmsk = xgene_pmu_write_agentmsk, 1751e35e0a04SHoan Tran .write_agent1msk = xgene_pmu_write_agent1msk, 1752e35e0a04SHoan Tran .enable_counter = xgene_pmu_enable_counter, 1753e35e0a04SHoan Tran .disable_counter = xgene_pmu_disable_counter, 1754e35e0a04SHoan Tran .enable_counter_int = xgene_pmu_enable_counter_int, 1755e35e0a04SHoan Tran .disable_counter_int = xgene_pmu_disable_counter_int, 1756e35e0a04SHoan Tran .reset_counters = xgene_pmu_reset_counters, 1757e35e0a04SHoan Tran .start_counters = xgene_pmu_start_counters, 1758e35e0a04SHoan Tran .stop_counters = xgene_pmu_stop_counters, 1759e35e0a04SHoan Tran }; 1760e35e0a04SHoan Tran 1761c0f7f7acSHoan Tran static const struct xgene_pmu_ops xgene_pmu_v3_ops = { 1762c0f7f7acSHoan Tran .mask_int = xgene_pmu_v3_mask_int, 1763c0f7f7acSHoan Tran .unmask_int = xgene_pmu_v3_unmask_int, 1764c0f7f7acSHoan Tran .read_counter = xgene_pmu_read_counter64, 1765c0f7f7acSHoan Tran .write_counter = xgene_pmu_write_counter64, 1766c0f7f7acSHoan Tran .write_evttype = xgene_pmu_write_evttype, 1767c0f7f7acSHoan Tran .write_agentmsk = xgene_pmu_v3_write_agentmsk, 1768c0f7f7acSHoan Tran .write_agent1msk = xgene_pmu_v3_write_agent1msk, 1769c0f7f7acSHoan Tran .enable_counter = xgene_pmu_enable_counter, 1770c0f7f7acSHoan Tran .disable_counter = xgene_pmu_disable_counter, 1771c0f7f7acSHoan Tran .enable_counter_int = xgene_pmu_enable_counter_int, 1772c0f7f7acSHoan Tran .disable_counter_int = xgene_pmu_disable_counter_int, 1773c0f7f7acSHoan Tran .reset_counters = xgene_pmu_reset_counters, 1774c0f7f7acSHoan Tran .start_counters = xgene_pmu_start_counters, 1775c0f7f7acSHoan Tran .stop_counters = xgene_pmu_stop_counters, 1776c0f7f7acSHoan Tran }; 1777c0f7f7acSHoan Tran 1778832c927dSTai Nguyen static const struct of_device_id xgene_pmu_of_match[] = { 1779832c927dSTai Nguyen { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data }, 1780832c927dSTai Nguyen { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data }, 1781832c927dSTai Nguyen {}, 1782832c927dSTai Nguyen }; 1783832c927dSTai Nguyen MODULE_DEVICE_TABLE(of, xgene_pmu_of_match); 1784832c927dSTai Nguyen #ifdef CONFIG_ACPI 1785832c927dSTai Nguyen static const struct acpi_device_id xgene_pmu_acpi_match[] = { 1786832c927dSTai Nguyen {"APMC0D5B", PCP_PMU_V1}, 1787832c927dSTai Nguyen {"APMC0D5C", PCP_PMU_V2}, 1788c0f7f7acSHoan Tran {"APMC0D83", PCP_PMU_V3}, 1789832c927dSTai Nguyen {}, 1790832c927dSTai Nguyen }; 1791832c927dSTai Nguyen MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match); 1792832c927dSTai Nguyen #endif 1793832c927dSTai Nguyen 1794cbb72a3cSHoan Tran static int xgene_pmu_online_cpu(unsigned int cpu, struct hlist_node *node) 1795cbb72a3cSHoan Tran { 1796cbb72a3cSHoan Tran struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu, 1797cbb72a3cSHoan Tran node); 1798cbb72a3cSHoan Tran 1799cbb72a3cSHoan Tran if (cpumask_empty(&xgene_pmu->cpu)) 1800cbb72a3cSHoan Tran cpumask_set_cpu(cpu, &xgene_pmu->cpu); 1801cbb72a3cSHoan Tran 1802cbb72a3cSHoan Tran /* Overflow interrupt also should use the same CPU */ 1803cbb72a3cSHoan Tran WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu)); 1804cbb72a3cSHoan Tran 1805cbb72a3cSHoan Tran return 0; 1806cbb72a3cSHoan Tran } 1807cbb72a3cSHoan Tran 1808cbb72a3cSHoan Tran static int xgene_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) 1809cbb72a3cSHoan Tran { 1810cbb72a3cSHoan Tran struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu, 1811cbb72a3cSHoan Tran node); 1812cbb72a3cSHoan Tran struct xgene_pmu_dev_ctx *ctx; 1813cbb72a3cSHoan Tran unsigned int target; 1814cbb72a3cSHoan Tran 1815cbb72a3cSHoan Tran if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu)) 1816cbb72a3cSHoan Tran return 0; 1817cbb72a3cSHoan Tran target = cpumask_any_but(cpu_online_mask, cpu); 1818cbb72a3cSHoan Tran if (target >= nr_cpu_ids) 1819cbb72a3cSHoan Tran return 0; 1820cbb72a3cSHoan Tran 1821cbb72a3cSHoan Tran list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) { 1822cbb72a3cSHoan Tran perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target); 1823cbb72a3cSHoan Tran } 1824cbb72a3cSHoan Tran list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) { 1825cbb72a3cSHoan Tran perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target); 1826cbb72a3cSHoan Tran } 1827cbb72a3cSHoan Tran list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) { 1828cbb72a3cSHoan Tran perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target); 1829cbb72a3cSHoan Tran } 1830cbb72a3cSHoan Tran list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) { 1831cbb72a3cSHoan Tran perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target); 1832cbb72a3cSHoan Tran } 1833cbb72a3cSHoan Tran 1834cbb72a3cSHoan Tran cpumask_set_cpu(target, &xgene_pmu->cpu); 1835cbb72a3cSHoan Tran /* Overflow interrupt also should use the same CPU */ 1836cbb72a3cSHoan Tran WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu)); 1837cbb72a3cSHoan Tran 1838cbb72a3cSHoan Tran return 0; 1839cbb72a3cSHoan Tran } 1840cbb72a3cSHoan Tran 1841832c927dSTai Nguyen static int xgene_pmu_probe(struct platform_device *pdev) 1842832c927dSTai Nguyen { 1843832c927dSTai Nguyen const struct xgene_pmu_data *dev_data; 1844832c927dSTai Nguyen const struct of_device_id *of_id; 1845832c927dSTai Nguyen struct xgene_pmu *xgene_pmu; 1846832c927dSTai Nguyen struct resource *res; 1847832c927dSTai Nguyen int irq, rc; 1848832c927dSTai Nguyen int version; 1849832c927dSTai Nguyen 1850cbb72a3cSHoan Tran /* Install a hook to update the reader CPU in case it goes offline */ 1851cbb72a3cSHoan Tran rc = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE, 1852cbb72a3cSHoan Tran "CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE", 1853cbb72a3cSHoan Tran xgene_pmu_online_cpu, 1854cbb72a3cSHoan Tran xgene_pmu_offline_cpu); 1855cbb72a3cSHoan Tran if (rc) 1856cbb72a3cSHoan Tran return rc; 1857cbb72a3cSHoan Tran 1858832c927dSTai Nguyen xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL); 1859832c927dSTai Nguyen if (!xgene_pmu) 1860832c927dSTai Nguyen return -ENOMEM; 1861832c927dSTai Nguyen xgene_pmu->dev = &pdev->dev; 1862832c927dSTai Nguyen platform_set_drvdata(pdev, xgene_pmu); 1863832c927dSTai Nguyen 1864832c927dSTai Nguyen version = -EINVAL; 1865832c927dSTai Nguyen of_id = of_match_device(xgene_pmu_of_match, &pdev->dev); 1866832c927dSTai Nguyen if (of_id) { 1867832c927dSTai Nguyen dev_data = (const struct xgene_pmu_data *) of_id->data; 1868832c927dSTai Nguyen version = dev_data->id; 1869832c927dSTai Nguyen } 1870832c927dSTai Nguyen 1871832c927dSTai Nguyen #ifdef CONFIG_ACPI 1872832c927dSTai Nguyen if (ACPI_COMPANION(&pdev->dev)) { 1873832c927dSTai Nguyen const struct acpi_device_id *acpi_id; 1874832c927dSTai Nguyen 1875832c927dSTai Nguyen acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev); 1876832c927dSTai Nguyen if (acpi_id) 1877832c927dSTai Nguyen version = (int) acpi_id->driver_data; 1878832c927dSTai Nguyen } 1879832c927dSTai Nguyen #endif 1880832c927dSTai Nguyen if (version < 0) 1881832c927dSTai Nguyen return -ENODEV; 1882832c927dSTai Nguyen 1883c0f7f7acSHoan Tran if (version == PCP_PMU_V3) 1884c0f7f7acSHoan Tran xgene_pmu->ops = &xgene_pmu_v3_ops; 1885c0f7f7acSHoan Tran else 1886e35e0a04SHoan Tran xgene_pmu->ops = &xgene_pmu_ops; 1887e35e0a04SHoan Tran 1888832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->l3cpmus); 1889832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->iobpmus); 1890832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->mcbpmus); 1891832c927dSTai Nguyen INIT_LIST_HEAD(&xgene_pmu->mcpmus); 1892832c927dSTai Nguyen 1893832c927dSTai Nguyen xgene_pmu->version = version; 1894832c927dSTai Nguyen dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version); 1895832c927dSTai Nguyen 1896832c927dSTai Nguyen res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1897832c927dSTai Nguyen xgene_pmu->pcppmu_csr = devm_ioremap_resource(&pdev->dev, res); 1898832c927dSTai Nguyen if (IS_ERR(xgene_pmu->pcppmu_csr)) { 1899832c927dSTai Nguyen dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n"); 1900c1be2ddbSTai Nguyen return PTR_ERR(xgene_pmu->pcppmu_csr); 1901832c927dSTai Nguyen } 1902832c927dSTai Nguyen 1903832c927dSTai Nguyen irq = platform_get_irq(pdev, 0); 1904228f855fSStephen Boyd if (irq < 0) 1905c1be2ddbSTai Nguyen return -EINVAL; 1906cbb72a3cSHoan Tran 1907832c927dSTai Nguyen rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr, 1908832c927dSTai Nguyen IRQF_NOBALANCING | IRQF_NO_THREAD, 1909832c927dSTai Nguyen dev_name(&pdev->dev), xgene_pmu); 1910832c927dSTai Nguyen if (rc) { 1911832c927dSTai Nguyen dev_err(&pdev->dev, "Could not request IRQ %d\n", irq); 1912c1be2ddbSTai Nguyen return rc; 1913832c927dSTai Nguyen } 1914832c927dSTai Nguyen 1915cbb72a3cSHoan Tran xgene_pmu->irq = irq; 1916cbb72a3cSHoan Tran 1917832c927dSTai Nguyen raw_spin_lock_init(&xgene_pmu->lock); 1918832c927dSTai Nguyen 1919832c927dSTai Nguyen /* Check for active MCBs and MCUs */ 1920c0f7f7acSHoan Tran rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev); 1921832c927dSTai Nguyen if (rc) { 1922832c927dSTai Nguyen dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n"); 1923832c927dSTai Nguyen xgene_pmu->mcb_active_mask = 0x1; 1924832c927dSTai Nguyen xgene_pmu->mc_active_mask = 0x1; 1925832c927dSTai Nguyen } 1926832c927dSTai Nguyen 1927cbb72a3cSHoan Tran /* Add this instance to the list used by the hotplug callback */ 1928cbb72a3cSHoan Tran rc = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE, 1929cbb72a3cSHoan Tran &xgene_pmu->node); 1930832c927dSTai Nguyen if (rc) { 1931cbb72a3cSHoan Tran dev_err(&pdev->dev, "Error %d registering hotplug", rc); 1932c1be2ddbSTai Nguyen return rc; 1933832c927dSTai Nguyen } 1934832c927dSTai Nguyen 1935832c927dSTai Nguyen /* Walk through the tree for all PMU perf devices */ 1936832c927dSTai Nguyen rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev); 1937832c927dSTai Nguyen if (rc) { 1938832c927dSTai Nguyen dev_err(&pdev->dev, "No PMU perf devices found!\n"); 1939cbb72a3cSHoan Tran goto out_unregister; 1940832c927dSTai Nguyen } 1941832c927dSTai Nguyen 1942832c927dSTai Nguyen /* Enable interrupt */ 1943e35e0a04SHoan Tran xgene_pmu->ops->unmask_int(xgene_pmu); 1944832c927dSTai Nguyen 1945832c927dSTai Nguyen return 0; 1946cbb72a3cSHoan Tran 1947cbb72a3cSHoan Tran out_unregister: 1948cbb72a3cSHoan Tran cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE, 1949cbb72a3cSHoan Tran &xgene_pmu->node); 1950cbb72a3cSHoan Tran return rc; 1951832c927dSTai Nguyen } 1952832c927dSTai Nguyen 1953832c927dSTai Nguyen static void 1954832c927dSTai Nguyen xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus) 1955832c927dSTai Nguyen { 1956832c927dSTai Nguyen struct xgene_pmu_dev_ctx *ctx; 1957832c927dSTai Nguyen 1958832c927dSTai Nguyen list_for_each_entry(ctx, pmus, next) { 1959c1be2ddbSTai Nguyen perf_pmu_unregister(&ctx->pmu_dev->pmu); 1960832c927dSTai Nguyen } 1961832c927dSTai Nguyen } 1962832c927dSTai Nguyen 1963832c927dSTai Nguyen static int xgene_pmu_remove(struct platform_device *pdev) 1964832c927dSTai Nguyen { 1965832c927dSTai Nguyen struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev); 1966832c927dSTai Nguyen 1967832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus); 1968832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus); 1969832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus); 1970832c927dSTai Nguyen xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus); 1971cbb72a3cSHoan Tran cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE, 1972cbb72a3cSHoan Tran &xgene_pmu->node); 1973832c927dSTai Nguyen 1974832c927dSTai Nguyen return 0; 1975832c927dSTai Nguyen } 1976832c927dSTai Nguyen 1977832c927dSTai Nguyen static struct platform_driver xgene_pmu_driver = { 1978832c927dSTai Nguyen .probe = xgene_pmu_probe, 1979832c927dSTai Nguyen .remove = xgene_pmu_remove, 1980832c927dSTai Nguyen .driver = { 1981832c927dSTai Nguyen .name = "xgene-pmu", 1982832c927dSTai Nguyen .of_match_table = xgene_pmu_of_match, 1983832c927dSTai Nguyen .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match), 1984832c927dSTai Nguyen }, 1985832c927dSTai Nguyen }; 1986832c927dSTai Nguyen 1987832c927dSTai Nguyen builtin_platform_driver(xgene_pmu_driver); 1988