1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2016 Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/init.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/perf_event.h> 17 #include <linux/slab.h> 18 19 #define COUNTER_CNTL 0x0 20 #define COUNTER_READ 0x20 21 22 #define COUNTER_DPCR1 0x30 23 24 #define CNTL_OVER 0x1 25 #define CNTL_CLEAR 0x2 26 #define CNTL_EN 0x4 27 #define CNTL_EN_MASK 0xFFFFFFFB 28 #define CNTL_CLEAR_MASK 0xFFFFFFFD 29 #define CNTL_OVER_MASK 0xFFFFFFFE 30 31 #define CNTL_CSV_SHIFT 24 32 #define CNTL_CSV_MASK (0xFF << CNTL_CSV_SHIFT) 33 34 #define EVENT_CYCLES_ID 0 35 #define EVENT_CYCLES_COUNTER 0 36 #define NUM_COUNTERS 4 37 38 #define AXI_MASKING_REVERT 0xffff0000 /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */ 39 40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) 41 42 #define DDR_PERF_DEV_NAME "imx8_ddr" 43 #define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu" 44 45 static DEFINE_IDA(ddr_ida); 46 47 /* DDR Perf hardware feature */ 48 #define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */ 49 50 struct fsl_ddr_devtype_data { 51 unsigned int quirks; /* quirks needed for different DDR Perf core */ 52 }; 53 54 static const struct fsl_ddr_devtype_data imx8_devtype_data; 55 56 static const struct fsl_ddr_devtype_data imx8m_devtype_data = { 57 .quirks = DDR_CAP_AXI_ID_FILTER, 58 }; 59 60 static const struct of_device_id imx_ddr_pmu_dt_ids[] = { 61 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data}, 62 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data}, 63 { /* sentinel */ } 64 }; 65 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); 66 67 struct ddr_pmu { 68 struct pmu pmu; 69 void __iomem *base; 70 unsigned int cpu; 71 struct hlist_node node; 72 struct device *dev; 73 struct perf_event *events[NUM_COUNTERS]; 74 int active_events; 75 enum cpuhp_state cpuhp_state; 76 const struct fsl_ddr_devtype_data *devtype_data; 77 int irq; 78 int id; 79 }; 80 81 static ssize_t ddr_perf_cpumask_show(struct device *dev, 82 struct device_attribute *attr, char *buf) 83 { 84 struct ddr_pmu *pmu = dev_get_drvdata(dev); 85 86 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); 87 } 88 89 static struct device_attribute ddr_perf_cpumask_attr = 90 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL); 91 92 static struct attribute *ddr_perf_cpumask_attrs[] = { 93 &ddr_perf_cpumask_attr.attr, 94 NULL, 95 }; 96 97 static struct attribute_group ddr_perf_cpumask_attr_group = { 98 .attrs = ddr_perf_cpumask_attrs, 99 }; 100 101 static ssize_t 102 ddr_pmu_event_show(struct device *dev, struct device_attribute *attr, 103 char *page) 104 { 105 struct perf_pmu_events_attr *pmu_attr; 106 107 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 108 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 109 } 110 111 #define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \ 112 (&((struct perf_pmu_events_attr[]) { \ 113 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\ 114 .id = _id, } \ 115 })[0].attr.attr) 116 117 static struct attribute *ddr_perf_events_attrs[] = { 118 IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID), 119 IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01), 120 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04), 121 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05), 122 IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08), 123 IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09), 124 IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10), 125 IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11), 126 IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12), 127 IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20), 128 IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21), 129 IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22), 130 IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23), 131 IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24), 132 IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25), 133 IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26), 134 IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27), 135 IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29), 136 IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a), 137 IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b), 138 IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30), 139 IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31), 140 IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32), 141 IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33), 142 IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34), 143 IMX8_DDR_PMU_EVENT_ATTR(read, 0x35), 144 IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36), 145 IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37), 146 IMX8_DDR_PMU_EVENT_ATTR(write, 0x38), 147 IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39), 148 IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41), 149 IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42), 150 NULL, 151 }; 152 153 static struct attribute_group ddr_perf_events_attr_group = { 154 .name = "events", 155 .attrs = ddr_perf_events_attrs, 156 }; 157 158 PMU_FORMAT_ATTR(event, "config:0-7"); 159 PMU_FORMAT_ATTR(axi_id, "config1:0-15"); 160 PMU_FORMAT_ATTR(axi_mask, "config1:16-31"); 161 162 static struct attribute *ddr_perf_format_attrs[] = { 163 &format_attr_event.attr, 164 &format_attr_axi_id.attr, 165 &format_attr_axi_mask.attr, 166 NULL, 167 }; 168 169 static struct attribute_group ddr_perf_format_attr_group = { 170 .name = "format", 171 .attrs = ddr_perf_format_attrs, 172 }; 173 174 static const struct attribute_group *attr_groups[] = { 175 &ddr_perf_events_attr_group, 176 &ddr_perf_format_attr_group, 177 &ddr_perf_cpumask_attr_group, 178 NULL, 179 }; 180 181 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) 182 { 183 int i; 184 185 /* 186 * Always map cycle event to counter 0 187 * Cycles counter is dedicated for cycle event 188 * can't used for the other events 189 */ 190 if (event == EVENT_CYCLES_ID) { 191 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL) 192 return EVENT_CYCLES_COUNTER; 193 else 194 return -ENOENT; 195 } 196 197 for (i = 1; i < NUM_COUNTERS; i++) { 198 if (pmu->events[i] == NULL) 199 return i; 200 } 201 202 return -ENOENT; 203 } 204 205 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter) 206 { 207 pmu->events[counter] = NULL; 208 } 209 210 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) 211 { 212 return readl_relaxed(pmu->base + COUNTER_READ + counter * 4); 213 } 214 215 static bool ddr_perf_is_filtered(struct perf_event *event) 216 { 217 return event->attr.config == 0x41 || event->attr.config == 0x42; 218 } 219 220 static u32 ddr_perf_filter_val(struct perf_event *event) 221 { 222 return event->attr.config1; 223 } 224 225 static bool ddr_perf_filters_compatible(struct perf_event *a, 226 struct perf_event *b) 227 { 228 if (!ddr_perf_is_filtered(a)) 229 return true; 230 if (!ddr_perf_is_filtered(b)) 231 return true; 232 return ddr_perf_filter_val(a) == ddr_perf_filter_val(b); 233 } 234 235 static int ddr_perf_event_init(struct perf_event *event) 236 { 237 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 238 struct hw_perf_event *hwc = &event->hw; 239 struct perf_event *sibling; 240 241 if (event->attr.type != event->pmu->type) 242 return -ENOENT; 243 244 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 245 return -EOPNOTSUPP; 246 247 if (event->cpu < 0) { 248 dev_warn(pmu->dev, "Can't provide per-task data!\n"); 249 return -EOPNOTSUPP; 250 } 251 252 /* 253 * We must NOT create groups containing mixed PMUs, although software 254 * events are acceptable (for example to create a CCN group 255 * periodically read when a hrtimer aka cpu-clock leader triggers). 256 */ 257 if (event->group_leader->pmu != event->pmu && 258 !is_software_event(event->group_leader)) 259 return -EINVAL; 260 261 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { 262 if (!ddr_perf_filters_compatible(event, event->group_leader)) 263 return -EINVAL; 264 for_each_sibling_event(sibling, event->group_leader) { 265 if (!ddr_perf_filters_compatible(event, sibling)) 266 return -EINVAL; 267 } 268 } 269 270 for_each_sibling_event(sibling, event->group_leader) { 271 if (sibling->pmu != event->pmu && 272 !is_software_event(sibling)) 273 return -EINVAL; 274 } 275 276 event->cpu = pmu->cpu; 277 hwc->idx = -1; 278 279 return 0; 280 } 281 282 283 static void ddr_perf_event_update(struct perf_event *event) 284 { 285 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 286 struct hw_perf_event *hwc = &event->hw; 287 u64 delta, prev_raw_count, new_raw_count; 288 int counter = hwc->idx; 289 290 do { 291 prev_raw_count = local64_read(&hwc->prev_count); 292 new_raw_count = ddr_perf_read_counter(pmu, counter); 293 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 294 new_raw_count) != prev_raw_count); 295 296 delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; 297 298 local64_add(delta, &event->count); 299 } 300 301 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, 302 int counter, bool enable) 303 { 304 u8 reg = counter * 4 + COUNTER_CNTL; 305 int val; 306 307 if (enable) { 308 /* 309 * must disable first, then enable again 310 * otherwise, cycle counter will not work 311 * if previous state is enabled. 312 */ 313 writel(0, pmu->base + reg); 314 val = CNTL_EN | CNTL_CLEAR; 315 val |= FIELD_PREP(CNTL_CSV_MASK, config); 316 writel(val, pmu->base + reg); 317 } else { 318 /* Disable counter */ 319 writel(0, pmu->base + reg); 320 } 321 } 322 323 static void ddr_perf_event_start(struct perf_event *event, int flags) 324 { 325 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 326 struct hw_perf_event *hwc = &event->hw; 327 int counter = hwc->idx; 328 329 local64_set(&hwc->prev_count, 0); 330 331 ddr_perf_counter_enable(pmu, event->attr.config, counter, true); 332 333 hwc->state = 0; 334 } 335 336 static int ddr_perf_event_add(struct perf_event *event, int flags) 337 { 338 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 339 struct hw_perf_event *hwc = &event->hw; 340 int counter; 341 int cfg = event->attr.config; 342 int cfg1 = event->attr.config1; 343 344 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { 345 int i; 346 347 for (i = 1; i < NUM_COUNTERS; i++) { 348 if (pmu->events[i] && 349 !ddr_perf_filters_compatible(event, pmu->events[i])) 350 return -EINVAL; 351 } 352 353 if (ddr_perf_is_filtered(event)) { 354 /* revert axi id masking(axi_mask) value */ 355 cfg1 ^= AXI_MASKING_REVERT; 356 writel(cfg1, pmu->base + COUNTER_DPCR1); 357 } 358 } 359 360 counter = ddr_perf_alloc_counter(pmu, cfg); 361 if (counter < 0) { 362 dev_dbg(pmu->dev, "There are not enough counters\n"); 363 return -EOPNOTSUPP; 364 } 365 366 pmu->events[counter] = event; 367 pmu->active_events++; 368 hwc->idx = counter; 369 370 hwc->state |= PERF_HES_STOPPED; 371 372 if (flags & PERF_EF_START) 373 ddr_perf_event_start(event, flags); 374 375 return 0; 376 } 377 378 static void ddr_perf_event_stop(struct perf_event *event, int flags) 379 { 380 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 381 struct hw_perf_event *hwc = &event->hw; 382 int counter = hwc->idx; 383 384 ddr_perf_counter_enable(pmu, event->attr.config, counter, false); 385 ddr_perf_event_update(event); 386 387 hwc->state |= PERF_HES_STOPPED; 388 } 389 390 static void ddr_perf_event_del(struct perf_event *event, int flags) 391 { 392 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 393 struct hw_perf_event *hwc = &event->hw; 394 int counter = hwc->idx; 395 396 ddr_perf_event_stop(event, PERF_EF_UPDATE); 397 398 ddr_perf_free_counter(pmu, counter); 399 pmu->active_events--; 400 hwc->idx = -1; 401 } 402 403 static void ddr_perf_pmu_enable(struct pmu *pmu) 404 { 405 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); 406 407 /* enable cycle counter if cycle is not active event list */ 408 if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) 409 ddr_perf_counter_enable(ddr_pmu, 410 EVENT_CYCLES_ID, 411 EVENT_CYCLES_COUNTER, 412 true); 413 } 414 415 static void ddr_perf_pmu_disable(struct pmu *pmu) 416 { 417 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); 418 419 if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) 420 ddr_perf_counter_enable(ddr_pmu, 421 EVENT_CYCLES_ID, 422 EVENT_CYCLES_COUNTER, 423 false); 424 } 425 426 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, 427 struct device *dev) 428 { 429 *pmu = (struct ddr_pmu) { 430 .pmu = (struct pmu) { 431 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 432 .task_ctx_nr = perf_invalid_context, 433 .attr_groups = attr_groups, 434 .event_init = ddr_perf_event_init, 435 .add = ddr_perf_event_add, 436 .del = ddr_perf_event_del, 437 .start = ddr_perf_event_start, 438 .stop = ddr_perf_event_stop, 439 .read = ddr_perf_event_update, 440 .pmu_enable = ddr_perf_pmu_enable, 441 .pmu_disable = ddr_perf_pmu_disable, 442 }, 443 .base = base, 444 .dev = dev, 445 }; 446 447 pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL); 448 return pmu->id; 449 } 450 451 static irqreturn_t ddr_perf_irq_handler(int irq, void *p) 452 { 453 int i; 454 struct ddr_pmu *pmu = (struct ddr_pmu *) p; 455 struct perf_event *event, *cycle_event = NULL; 456 457 /* all counter will stop if cycle counter disabled */ 458 ddr_perf_counter_enable(pmu, 459 EVENT_CYCLES_ID, 460 EVENT_CYCLES_COUNTER, 461 false); 462 /* 463 * When the cycle counter overflows, all counters are stopped, 464 * and an IRQ is raised. If any other counter overflows, it 465 * continues counting, and no IRQ is raised. 466 * 467 * Cycles occur at least 4 times as often as other events, so we 468 * can update all events on a cycle counter overflow and not 469 * lose events. 470 * 471 */ 472 for (i = 0; i < NUM_COUNTERS; i++) { 473 474 if (!pmu->events[i]) 475 continue; 476 477 event = pmu->events[i]; 478 479 ddr_perf_event_update(event); 480 481 if (event->hw.idx == EVENT_CYCLES_COUNTER) 482 cycle_event = event; 483 } 484 485 ddr_perf_counter_enable(pmu, 486 EVENT_CYCLES_ID, 487 EVENT_CYCLES_COUNTER, 488 true); 489 if (cycle_event) 490 ddr_perf_event_update(cycle_event); 491 492 return IRQ_HANDLED; 493 } 494 495 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) 496 { 497 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node); 498 int target; 499 500 if (cpu != pmu->cpu) 501 return 0; 502 503 target = cpumask_any_but(cpu_online_mask, cpu); 504 if (target >= nr_cpu_ids) 505 return 0; 506 507 perf_pmu_migrate_context(&pmu->pmu, cpu, target); 508 pmu->cpu = target; 509 510 WARN_ON(irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu))); 511 512 return 0; 513 } 514 515 static int ddr_perf_probe(struct platform_device *pdev) 516 { 517 struct ddr_pmu *pmu; 518 struct device_node *np; 519 void __iomem *base; 520 char *name; 521 int num; 522 int ret; 523 int irq; 524 525 base = devm_platform_ioremap_resource(pdev, 0); 526 if (IS_ERR(base)) 527 return PTR_ERR(base); 528 529 np = pdev->dev.of_node; 530 531 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); 532 if (!pmu) 533 return -ENOMEM; 534 535 num = ddr_perf_init(pmu, base, &pdev->dev); 536 537 platform_set_drvdata(pdev, pmu); 538 539 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", 540 num); 541 if (!name) 542 return -ENOMEM; 543 544 pmu->devtype_data = of_device_get_match_data(&pdev->dev); 545 546 pmu->cpu = raw_smp_processor_id(); 547 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 548 DDR_CPUHP_CB_NAME, 549 NULL, 550 ddr_perf_offline_cpu); 551 552 if (ret < 0) { 553 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n"); 554 goto ddr_perf_err; 555 } 556 557 pmu->cpuhp_state = ret; 558 559 /* Register the pmu instance for cpu hotplug */ 560 cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); 561 562 /* Request irq */ 563 irq = of_irq_get(np, 0); 564 if (irq < 0) { 565 dev_err(&pdev->dev, "Failed to get irq: %d", irq); 566 ret = irq; 567 goto ddr_perf_err; 568 } 569 570 ret = devm_request_irq(&pdev->dev, irq, 571 ddr_perf_irq_handler, 572 IRQF_NOBALANCING | IRQF_NO_THREAD, 573 DDR_CPUHP_CB_NAME, 574 pmu); 575 if (ret < 0) { 576 dev_err(&pdev->dev, "Request irq failed: %d", ret); 577 goto ddr_perf_err; 578 } 579 580 pmu->irq = irq; 581 ret = irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu)); 582 if (ret) { 583 dev_err(pmu->dev, "Failed to set interrupt affinity!\n"); 584 goto ddr_perf_err; 585 } 586 587 ret = perf_pmu_register(&pmu->pmu, name, -1); 588 if (ret) 589 goto ddr_perf_err; 590 591 return 0; 592 593 ddr_perf_err: 594 if (pmu->cpuhp_state) 595 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 596 597 ida_simple_remove(&ddr_ida, pmu->id); 598 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret); 599 return ret; 600 } 601 602 static int ddr_perf_remove(struct platform_device *pdev) 603 { 604 struct ddr_pmu *pmu = platform_get_drvdata(pdev); 605 606 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 607 irq_set_affinity_hint(pmu->irq, NULL); 608 609 perf_pmu_unregister(&pmu->pmu); 610 611 ida_simple_remove(&ddr_ida, pmu->id); 612 return 0; 613 } 614 615 static struct platform_driver imx_ddr_pmu_driver = { 616 .driver = { 617 .name = "imx-ddr-pmu", 618 .of_match_table = imx_ddr_pmu_dt_ids, 619 }, 620 .probe = ddr_perf_probe, 621 .remove = ddr_perf_remove, 622 }; 623 624 module_platform_driver(imx_ddr_pmu_driver); 625 MODULE_LICENSE("GPL v2"); 626